2 * ARM MPS2 SCC emulation
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* This is a model of the SCC (Serial Communication Controller)
13 * found in the FPGA images of MPS2 development boards.
15 * Documentation of it can be found in the MPS2 TRM:
16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
17 * and also in the Application Notes documenting individual FPGA images.
20 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "qemu/bitops.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27 #include "hw/registerfields.h"
28 #include "hw/misc/mps2-scc.h"
29 #include "hw/misc/led.h"
30 #include "hw/qdev-properties.h"
36 REG32(CFGDATA_RTN
, 0xa0)
37 REG32(CFGDATA_OUT
, 0xa4)
39 FIELD(CFGCTRL
, DEVICE
, 0, 12)
40 FIELD(CFGCTRL
, RES1
, 12, 8)
41 FIELD(CFGCTRL
, FUNCTION
, 20, 6)
42 FIELD(CFGCTRL
, RES2
, 26, 4)
43 FIELD(CFGCTRL
, WRITE
, 30, 1)
44 FIELD(CFGCTRL
, START
, 31, 1)
46 FIELD(CFGSTAT
, DONE
, 0, 1)
47 FIELD(CFGSTAT
, ERROR
, 1, 1)
52 /* Handle a write via the SYS_CFG channel to the specified function/device.
53 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
55 static bool scc_cfg_write(MPS2SCC
*s
, unsigned function
,
56 unsigned device
, uint32_t value
)
58 trace_mps2_scc_cfg_write(function
, device
, value
);
60 if (function
!= 1 || device
>= NUM_OSCCLK
) {
61 qemu_log_mask(LOG_GUEST_ERROR
,
62 "MPS2 SCC config write: bad function %d device %d\n",
67 s
->oscclk
[device
] = value
;
71 /* Handle a read via the SYS_CFG channel to the specified function/device.
72 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit),
73 * or set *value on success.
75 static bool scc_cfg_read(MPS2SCC
*s
, unsigned function
,
76 unsigned device
, uint32_t *value
)
78 if (function
!= 1 || device
>= NUM_OSCCLK
) {
79 qemu_log_mask(LOG_GUEST_ERROR
,
80 "MPS2 SCC config read: bad function %d device %d\n",
85 *value
= s
->oscclk
[device
];
87 trace_mps2_scc_cfg_read(function
, device
, *value
);
91 static uint64_t mps2_scc_read(void *opaque
, hwaddr offset
, unsigned size
)
93 MPS2SCC
*s
= MPS2_SCC(opaque
);
104 /* These are user-settable DIP switches on the board. We don't
105 * model that, so just return zeroes.
134 qemu_log_mask(LOG_GUEST_ERROR
,
135 "MPS2 SCC read: bad offset %x\n", (int) offset
);
140 trace_mps2_scc_read(offset
, r
, size
);
144 static void mps2_scc_write(void *opaque
, hwaddr offset
, uint64_t value
,
147 MPS2SCC
*s
= MPS2_SCC(opaque
);
149 trace_mps2_scc_write(offset
, value
, size
);
153 /* TODO on some boards bit 0 controls RAM remapping */
158 for (size_t i
= 0; i
< ARRAY_SIZE(s
->led
); i
++) {
159 led_set_state(s
->led
[i
], extract32(value
, i
, 1));
163 s
->cfgdata_out
= value
;
166 /* Writing to CFGCTRL clears SYS_CFGSTAT */
168 s
->cfgctrl
= value
& ~(R_CFGCTRL_RES1_MASK
|
169 R_CFGCTRL_RES2_MASK
|
170 R_CFGCTRL_START_MASK
);
172 if (value
& R_CFGCTRL_START_MASK
) {
173 /* Start bit set -- do a read or write (instantaneously) */
174 int device
= extract32(s
->cfgctrl
, R_CFGCTRL_DEVICE_SHIFT
,
175 R_CFGCTRL_DEVICE_LENGTH
);
176 int function
= extract32(s
->cfgctrl
, R_CFGCTRL_FUNCTION_SHIFT
,
177 R_CFGCTRL_FUNCTION_LENGTH
);
179 s
->cfgstat
= R_CFGSTAT_DONE_MASK
;
180 if (s
->cfgctrl
& R_CFGCTRL_WRITE_MASK
) {
181 if (!scc_cfg_write(s
, function
, device
, s
->cfgdata_out
)) {
182 s
->cfgstat
|= R_CFGSTAT_ERROR_MASK
;
186 if (!scc_cfg_read(s
, function
, device
, &result
)) {
187 s
->cfgstat
|= R_CFGSTAT_ERROR_MASK
;
189 s
->cfgdata_rtn
= result
;
195 /* DLL stands for Digital Locked Loop.
196 * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a
197 * mask of which of the DLL_LOCKED bits [16:23] should be ORed
198 * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0].
199 * For QEMU, our DLLs are always locked, so we can leave bit 0
200 * as 1 always and don't need to recalculate it.
202 s
->dll
= deposit32(s
->dll
, 24, 8, extract32(value
, 24, 8));
205 qemu_log_mask(LOG_GUEST_ERROR
,
206 "MPS2 SCC write: bad offset 0x%x\n", (int) offset
);
211 static const MemoryRegionOps mps2_scc_ops
= {
212 .read
= mps2_scc_read
,
213 .write
= mps2_scc_write
,
214 .endianness
= DEVICE_LITTLE_ENDIAN
,
217 static void mps2_scc_reset(DeviceState
*dev
)
219 MPS2SCC
*s
= MPS2_SCC(dev
);
222 trace_mps2_scc_reset();
227 s
->cfgctrl
= 0x100000;
230 for (i
= 0; i
< NUM_OSCCLK
; i
++) {
231 s
->oscclk
[i
] = s
->oscclk_reset
[i
];
233 for (i
= 0; i
< ARRAY_SIZE(s
->led
); i
++) {
234 device_cold_reset(DEVICE(s
->led
[i
]));
238 static void mps2_scc_init(Object
*obj
)
240 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
241 MPS2SCC
*s
= MPS2_SCC(obj
);
243 memory_region_init_io(&s
->iomem
, obj
, &mps2_scc_ops
, s
, "mps2-scc", 0x1000);
244 sysbus_init_mmio(sbd
, &s
->iomem
);
247 static void mps2_scc_realize(DeviceState
*dev
, Error
**errp
)
249 MPS2SCC
*s
= MPS2_SCC(dev
);
251 for (size_t i
= 0; i
< ARRAY_SIZE(s
->led
); i
++) {
252 char *name
= g_strdup_printf("SCC LED%zu", i
);
253 s
->led
[i
] = led_create_simple(OBJECT(dev
), GPIO_POLARITY_ACTIVE_HIGH
,
254 LED_COLOR_GREEN
, name
);
259 static const VMStateDescription mps2_scc_vmstate
= {
262 .minimum_version_id
= 1,
263 .fields
= (VMStateField
[]) {
264 VMSTATE_UINT32(cfg0
, MPS2SCC
),
265 VMSTATE_UINT32(cfg1
, MPS2SCC
),
266 VMSTATE_UINT32(cfgdata_rtn
, MPS2SCC
),
267 VMSTATE_UINT32(cfgdata_out
, MPS2SCC
),
268 VMSTATE_UINT32(cfgctrl
, MPS2SCC
),
269 VMSTATE_UINT32(cfgstat
, MPS2SCC
),
270 VMSTATE_UINT32(dll
, MPS2SCC
),
271 VMSTATE_UINT32_ARRAY(oscclk
, MPS2SCC
, NUM_OSCCLK
),
272 VMSTATE_END_OF_LIST()
276 static Property mps2_scc_properties
[] = {
277 /* Values for various read-only ID registers (which are specific
278 * to the board model or FPGA image)
280 DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC
, cfg4
, 0),
281 DEFINE_PROP_UINT32("scc-aid", MPS2SCC
, aid
, 0),
282 DEFINE_PROP_UINT32("scc-id", MPS2SCC
, id
, 0),
283 /* These are the initial settings for the source clocks on the board.
284 * In hardware they can be configured via a config file read by the
285 * motherboard configuration controller to suit the FPGA image.
286 * These default values are used by most of the standard FPGA images.
288 DEFINE_PROP_UINT32("oscclk0", MPS2SCC
, oscclk_reset
[0], 50000000),
289 DEFINE_PROP_UINT32("oscclk1", MPS2SCC
, oscclk_reset
[1], 24576000),
290 DEFINE_PROP_UINT32("oscclk2", MPS2SCC
, oscclk_reset
[2], 25000000),
291 DEFINE_PROP_END_OF_LIST(),
294 static void mps2_scc_class_init(ObjectClass
*klass
, void *data
)
296 DeviceClass
*dc
= DEVICE_CLASS(klass
);
298 dc
->realize
= mps2_scc_realize
;
299 dc
->vmsd
= &mps2_scc_vmstate
;
300 dc
->reset
= mps2_scc_reset
;
301 device_class_set_props(dc
, mps2_scc_properties
);
304 static const TypeInfo mps2_scc_info
= {
305 .name
= TYPE_MPS2_SCC
,
306 .parent
= TYPE_SYS_BUS_DEVICE
,
307 .instance_size
= sizeof(MPS2SCC
),
308 .instance_init
= mps2_scc_init
,
309 .class_init
= mps2_scc_class_init
,
312 static void mps2_scc_register_types(void)
314 type_register_static(&mps2_scc_info
);
317 type_init(mps2_scc_register_types
);