hw/ppc/ppc4xx_pci.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  13  *
  14  * Copyright IBM Corp. 2008
  15  *
  16  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  17  */
  18
  19 /* This file implements emulation of the 32-bit PCI controller found in some
  20  * 4xx SoCs, such as the 440EP. */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/irq.h"
  24 #include "hw/ppc/ppc.h"
  25 #include "hw/ppc/ppc4xx.h"
  26 #include "migration/vmstate.h"
  27 #include "qemu/module.h"
  28 #include "sysemu/reset.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "exec/address-spaces.h"
  32 #include "trace.h"
  33 #include "qom/object.h"
  34
  35 struct PCIMasterMap {
  36     uint32_t la;
  37     uint32_t ma;
  38     uint32_t pcila;
  39     uint32_t pciha;
  40 };
  41
  42 struct PCITargetMap {
  43     uint32_t ms;
  44     uint32_t la;
  45 };
  46
  47 OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
  48
  49 #define PPC4xx_PCI_NR_PMMS 3
  50 #define PPC4xx_PCI_NR_PTMS 2
  51
  52 struct PPC4xxPCIState {
  53     PCIHostState parent_obj;
  54
  55     struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
  56     struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
  57     qemu_irq irq[PCI_NUM_PINS];
  58
  59     MemoryRegion container;
  60     MemoryRegion iomem;
  61 };
  62
  63 #define PCIC0_CFGADDR       0x0
  64 #define PCIC0_CFGDATA       0x4
  65
  66 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
  67  * PCI accesses. */
  68 #define PCIL0_PMM0LA        0x0
  69 #define PCIL0_PMM0MA        0x4
  70 #define PCIL0_PMM0PCILA     0x8
  71 #define PCIL0_PMM0PCIHA     0xc
  72 #define PCIL0_PMM1LA        0x10
  73 #define PCIL0_PMM1MA        0x14
  74 #define PCIL0_PMM1PCILA     0x18
  75 #define PCIL0_PMM1PCIHA     0x1c
  76 #define PCIL0_PMM2LA        0x20
  77 #define PCIL0_PMM2MA        0x24
  78 #define PCIL0_PMM2PCILA     0x28
  79 #define PCIL0_PMM2PCIHA     0x2c
  80
  81 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
  82  * PLB accesses. */
  83 #define PCIL0_PTM1MS        0x30
  84 #define PCIL0_PTM1LA        0x34
  85 #define PCIL0_PTM2MS        0x38
  86 #define PCIL0_PTM2LA        0x3c
  87 #define PCI_REG_BASE        0x800000
  88 #define PCI_REG_SIZE        0x40
  89
  90 #define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)
  91
  92 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
  93                                   uint64_t value, unsigned size)
  94 {
  95     struct PPC4xxPCIState *pci = opaque;
  96
  97     /* We ignore all target attempts at PCI configuration, effectively
  98      * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
  99
 100     switch (offset) {
 101     case PCIL0_PMM0LA:
 102         pci->pmm[0].la = value;
 103         break;
 104     case PCIL0_PMM0MA:
 105         pci->pmm[0].ma = value;
 106         break;
 107     case PCIL0_PMM0PCIHA:
 108         pci->pmm[0].pciha = value;
 109         break;
 110     case PCIL0_PMM0PCILA:
 111         pci->pmm[0].pcila = value;
 112         break;
 113
 114     case PCIL0_PMM1LA:
 115         pci->pmm[1].la = value;
 116         break;
 117     case PCIL0_PMM1MA:
 118         pci->pmm[1].ma = value;
 119         break;
 120     case PCIL0_PMM1PCIHA:
 121         pci->pmm[1].pciha = value;
 122         break;
 123     case PCIL0_PMM1PCILA:
 124         pci->pmm[1].pcila = value;
 125         break;
 126
 127     case PCIL0_PMM2LA:
 128         pci->pmm[2].la = value;
 129         break;
 130     case PCIL0_PMM2MA:
 131         pci->pmm[2].ma = value;
 132         break;
 133     case PCIL0_PMM2PCIHA:
 134         pci->pmm[2].pciha = value;
 135         break;
 136     case PCIL0_PMM2PCILA:
 137         pci->pmm[2].pcila = value;
 138         break;
 139
 140     case PCIL0_PTM1MS:
 141         pci->ptm[0].ms = value;
 142         break;
 143     case PCIL0_PTM1LA:
 144         pci->ptm[0].la = value;
 145         break;
 146     case PCIL0_PTM2MS:
 147         pci->ptm[1].ms = value;
 148         break;
 149     case PCIL0_PTM2LA:
 150         pci->ptm[1].la = value;
 151         break;
 152
 153     default:
 154         printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
 155                (unsigned long)offset);
 156         break;
 157     }
 158 }
 159
 160 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
 161                                      unsigned size)
 162 {
 163     struct PPC4xxPCIState *pci = opaque;
 164     uint32_t value;
 165
 166     switch (offset) {
 167     case PCIL0_PMM0LA:
 168         value = pci->pmm[0].la;
 169         break;
 170     case PCIL0_PMM0MA:
 171         value = pci->pmm[0].ma;
 172         break;
 173     case PCIL0_PMM0PCIHA:
 174         value = pci->pmm[0].pciha;
 175         break;
 176     case PCIL0_PMM0PCILA:
 177         value = pci->pmm[0].pcila;
 178         break;
 179
 180     case PCIL0_PMM1LA:
 181         value = pci->pmm[1].la;
 182         break;
 183     case PCIL0_PMM1MA:
 184         value = pci->pmm[1].ma;
 185         break;
 186     case PCIL0_PMM1PCIHA:
 187         value = pci->pmm[1].pciha;
 188         break;
 189     case PCIL0_PMM1PCILA:
 190         value = pci->pmm[1].pcila;
 191         break;
 192
 193     case PCIL0_PMM2LA:
 194         value = pci->pmm[2].la;
 195         break;
 196     case PCIL0_PMM2MA:
 197         value = pci->pmm[2].ma;
 198         break;
 199     case PCIL0_PMM2PCIHA:
 200         value = pci->pmm[2].pciha;
 201         break;
 202     case PCIL0_PMM2PCILA:
 203         value = pci->pmm[2].pcila;
 204         break;
 205
 206     case PCIL0_PTM1MS:
 207         value = pci->ptm[0].ms;
 208         break;
 209     case PCIL0_PTM1LA:
 210         value = pci->ptm[0].la;
 211         break;
 212     case PCIL0_PTM2MS:
 213         value = pci->ptm[1].ms;
 214         break;
 215     case PCIL0_PTM2LA:
 216         value = pci->ptm[1].la;
 217         break;
 218
 219     default:
 220         printf("%s: invalid PCI internal register 0x%lx\n", __func__,
 221                (unsigned long)offset);
 222         value = 0;
 223     }
 224
 225     return value;
 226 }
 227
 228 static const MemoryRegionOps pci_reg_ops = {
 229     .read = ppc4xx_pci_reg_read4,
 230     .write = ppc4xx_pci_reg_write4,
 231     .endianness = DEVICE_LITTLE_ENDIAN,
 232 };
 233
 234 static void ppc4xx_pci_reset(void *opaque)
 235 {
 236     struct PPC4xxPCIState *pci = opaque;
 237
 238     memset(pci->pmm, 0, sizeof(pci->pmm));
 239     memset(pci->ptm, 0, sizeof(pci->ptm));
 240 }
 241
 242 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 243  * may need further refactoring for other boards. */
 244 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 245 {
 246     int slot = PCI_SLOT(pci_dev->devfn);
 247
 248     trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
 249
 250     return slot - 1;
 251 }
 252
 253 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
 254 {
 255     qemu_irq *pci_irqs = opaque;
 256
 257     trace_ppc4xx_pci_set_irq(irq_num);
 258     assert(irq_num >= 0);
 259     qemu_set_irq(pci_irqs[irq_num], level);
 260 }
 261
 262 static const VMStateDescription vmstate_pci_master_map = {
 263     .name = "pci_master_map",
 264     .version_id = 0,
 265     .minimum_version_id = 0,
 266     .fields = (VMStateField[]) {
 267         VMSTATE_UINT32(la, struct PCIMasterMap),
 268         VMSTATE_UINT32(ma, struct PCIMasterMap),
 269         VMSTATE_UINT32(pcila, struct PCIMasterMap),
 270         VMSTATE_UINT32(pciha, struct PCIMasterMap),
 271         VMSTATE_END_OF_LIST()
 272     }
 273 };
 274
 275 static const VMStateDescription vmstate_pci_target_map = {
 276     .name = "pci_target_map",
 277     .version_id = 0,
 278     .minimum_version_id = 0,
 279     .fields = (VMStateField[]) {
 280         VMSTATE_UINT32(ms, struct PCITargetMap),
 281         VMSTATE_UINT32(la, struct PCITargetMap),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static const VMStateDescription vmstate_ppc4xx_pci = {
 287     .name = "ppc4xx_pci",
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .fields = (VMStateField[]) {
 291         VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
 292                              vmstate_pci_master_map,
 293                              struct PCIMasterMap),
 294         VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
 295                              vmstate_pci_target_map,
 296                              struct PCITargetMap),
 297         VMSTATE_END_OF_LIST()
 298     }
 299 };
 300
 301 /* XXX Interrupt acknowledge cycles not supported. */
 302 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
 303 {
 304     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 305     PPC4xxPCIState *s;
 306     PCIHostState *h;
 307     PCIBus *b;
 308     int i;
 309
 310     h = PCI_HOST_BRIDGE(dev);
 311     s = PPC4xx_PCI_HOST_BRIDGE(dev);
 312
 313     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 314         sysbus_init_irq(sbd, &s->irq[i]);
 315     }
 316
 317     b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
 318                               ppc4xx_pci_map_irq, s->irq, get_system_memory(),
 319                               get_system_io(), 0, ARRAY_SIZE(s->irq),
 320                               TYPE_PCI_BUS);
 321     h->bus = b;
 322
 323     pci_create_simple(b, 0, "ppc4xx-host-bridge");
 324
 325     /* XXX split into 2 memory regions, one for config space, one for regs */
 326     memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
 327     memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
 328                           "pci-conf-idx", 4);
 329     memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
 330                           "pci-conf-data", 4);
 331     memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
 332                           "pci.reg", PCI_REG_SIZE);
 333     memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
 334     memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
 335     memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
 336     sysbus_init_mmio(sbd, &s->container);
 337     qemu_register_reset(ppc4xx_pci_reset, s);
 338 }
 339
 340 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
 341 {
 342     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 343     DeviceClass *dc = DEVICE_CLASS(klass);
 344
 345     dc->desc        = "Host bridge";
 346     k->vendor_id    = PCI_VENDOR_ID_IBM;
 347     k->device_id    = PCI_DEVICE_ID_IBM_440GX;
 348     k->class_id     = PCI_CLASS_BRIDGE_OTHER;
 349     /*
 350      * PCI-facing part of the host bridge, not usable without the
 351      * host-facing part, which can't be device_add'ed, yet.
 352      */
 353     dc->user_creatable = false;
 354 }
 355
 356 static const TypeInfo ppc4xx_host_bridge_info = {
 357     .name          = "ppc4xx-host-bridge",
 358     .parent        = TYPE_PCI_DEVICE,
 359     .instance_size = sizeof(PCIDevice),
 360     .class_init    = ppc4xx_host_bridge_class_init,
 361     .interfaces = (InterfaceInfo[]) {
 362         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 363         { },
 364     },
 365 };
 366
 367 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
 368 {
 369     DeviceClass *dc = DEVICE_CLASS(klass);
 370
 371     dc->realize = ppc4xx_pcihost_realize;
 372     dc->vmsd = &vmstate_ppc4xx_pci;
 373 }
 374
 375 static const TypeInfo ppc4xx_pcihost_info = {
 376     .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
 377     .parent        = TYPE_PCI_HOST_BRIDGE,
 378     .instance_size = sizeof(PPC4xxPCIState),
 379     .class_init    = ppc4xx_pcihost_class_init,
 380 };
 381
 382 static void ppc4xx_pci_register_types(void)
 383 {
 384     type_register_static(&ppc4xx_pcihost_info);
 385     type_register_static(&ppc4xx_host_bridge_info);
 386 }
 387
 388 type_init(ppc4xx_pci_register_types)