hw/sd: sd: Bypass the RCA check for CMD13 in SPI mode
[qemu/ar7.git] / hw / block / nvme.h
blobdee6092bd45f67bf74d568d679cdaba19ee97e22
1 #ifndef HW_NVME_H
2 #define HW_NVME_H
4 #include "block/nvme.h"
5 #include "nvme-ns.h"
7 #define NVME_MAX_NAMESPACES 256
9 #define NVME_DEFAULT_ZONE_SIZE (128 * MiB)
10 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
12 typedef struct NvmeParams {
13 char *serial;
14 uint32_t num_queues; /* deprecated since 5.1 */
15 uint32_t max_ioqpairs;
16 uint16_t msix_qsize;
17 uint32_t cmb_size_mb;
18 uint8_t aerl;
19 uint32_t aer_max_queued;
20 uint8_t mdts;
21 bool use_intel_id;
22 uint32_t zasl_bs;
23 bool legacy_cmb;
24 } NvmeParams;
26 typedef struct NvmeAsyncEvent {
27 QTAILQ_ENTRY(NvmeAsyncEvent) entry;
28 NvmeAerResult result;
29 } NvmeAsyncEvent;
31 typedef struct NvmeRequest {
32 struct NvmeSQueue *sq;
33 struct NvmeNamespace *ns;
34 BlockAIOCB *aiocb;
35 uint16_t status;
36 void *opaque;
37 NvmeCqe cqe;
38 NvmeCmd cmd;
39 BlockAcctCookie acct;
40 QEMUSGList qsg;
41 QEMUIOVector iov;
42 QTAILQ_ENTRY(NvmeRequest)entry;
43 } NvmeRequest;
45 static inline const char *nvme_adm_opc_str(uint8_t opc)
47 switch (opc) {
48 case NVME_ADM_CMD_DELETE_SQ: return "NVME_ADM_CMD_DELETE_SQ";
49 case NVME_ADM_CMD_CREATE_SQ: return "NVME_ADM_CMD_CREATE_SQ";
50 case NVME_ADM_CMD_GET_LOG_PAGE: return "NVME_ADM_CMD_GET_LOG_PAGE";
51 case NVME_ADM_CMD_DELETE_CQ: return "NVME_ADM_CMD_DELETE_CQ";
52 case NVME_ADM_CMD_CREATE_CQ: return "NVME_ADM_CMD_CREATE_CQ";
53 case NVME_ADM_CMD_IDENTIFY: return "NVME_ADM_CMD_IDENTIFY";
54 case NVME_ADM_CMD_ABORT: return "NVME_ADM_CMD_ABORT";
55 case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
56 case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
57 case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
58 default: return "NVME_ADM_CMD_UNKNOWN";
62 static inline const char *nvme_io_opc_str(uint8_t opc)
64 switch (opc) {
65 case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH";
66 case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE";
67 case NVME_CMD_READ: return "NVME_NVM_CMD_READ";
68 case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE";
69 case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
70 case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM";
71 case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_MGMT_SEND";
72 case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_MGMT_RECV";
73 case NVME_CMD_ZONE_APPEND: return "NVME_ZONED_CMD_ZONE_APPEND";
74 default: return "NVME_NVM_CMD_UNKNOWN";
78 typedef struct NvmeSQueue {
79 struct NvmeCtrl *ctrl;
80 uint16_t sqid;
81 uint16_t cqid;
82 uint32_t head;
83 uint32_t tail;
84 uint32_t size;
85 uint64_t dma_addr;
86 QEMUTimer *timer;
87 NvmeRequest *io_req;
88 QTAILQ_HEAD(, NvmeRequest) req_list;
89 QTAILQ_HEAD(, NvmeRequest) out_req_list;
90 QTAILQ_ENTRY(NvmeSQueue) entry;
91 } NvmeSQueue;
93 typedef struct NvmeCQueue {
94 struct NvmeCtrl *ctrl;
95 uint8_t phase;
96 uint16_t cqid;
97 uint16_t irq_enabled;
98 uint32_t head;
99 uint32_t tail;
100 uint32_t vector;
101 uint32_t size;
102 uint64_t dma_addr;
103 QEMUTimer *timer;
104 QTAILQ_HEAD(, NvmeSQueue) sq_list;
105 QTAILQ_HEAD(, NvmeRequest) req_list;
106 } NvmeCQueue;
108 #define TYPE_NVME_BUS "nvme-bus"
109 #define NVME_BUS(obj) OBJECT_CHECK(NvmeBus, (obj), TYPE_NVME_BUS)
111 typedef struct NvmeBus {
112 BusState parent_bus;
113 } NvmeBus;
115 #define TYPE_NVME "nvme"
116 #define NVME(obj) \
117 OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
119 typedef struct NvmeFeatureVal {
120 struct {
121 uint16_t temp_thresh_hi;
122 uint16_t temp_thresh_low;
124 uint32_t async_config;
125 } NvmeFeatureVal;
127 typedef struct NvmeCtrl {
128 PCIDevice parent_obj;
129 MemoryRegion bar0;
130 MemoryRegion iomem;
131 NvmeBar bar;
132 NvmeParams params;
133 NvmeBus bus;
134 BlockConf conf;
136 bool qs_created;
137 uint32_t page_size;
138 uint16_t page_bits;
139 uint16_t max_prp_ents;
140 uint16_t cqe_size;
141 uint16_t sqe_size;
142 uint32_t reg_size;
143 uint32_t num_namespaces;
144 uint32_t max_q_ents;
145 uint8_t outstanding_aers;
146 uint32_t irq_status;
147 uint64_t host_timestamp; /* Timestamp sent by the host */
148 uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
149 uint64_t starttime_ms;
150 uint16_t temperature;
151 uint8_t smart_critical_warning;
153 struct {
154 MemoryRegion mem;
155 uint8_t *buf;
156 bool cmse;
157 hwaddr cba;
158 } cmb;
160 struct {
161 HostMemoryBackend *dev;
162 bool cmse;
163 hwaddr cba;
164 } pmr;
166 uint8_t aer_mask;
167 NvmeRequest **aer_reqs;
168 QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
169 int aer_queued;
171 uint8_t zasl;
173 NvmeNamespace namespace;
174 NvmeNamespace *namespaces[NVME_MAX_NAMESPACES];
175 NvmeSQueue **sq;
176 NvmeCQueue **cq;
177 NvmeSQueue admin_sq;
178 NvmeCQueue admin_cq;
179 NvmeIdCtrl id_ctrl;
180 NvmeFeatureVal features;
181 } NvmeCtrl;
183 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
185 if (!nsid || nsid > n->num_namespaces) {
186 return NULL;
189 return n->namespaces[nsid - 1];
192 static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
194 NvmeSQueue *sq = req->sq;
195 NvmeCtrl *n = sq->ctrl;
197 return n->cq[sq->cqid];
200 static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
202 NvmeSQueue *sq = req->sq;
203 return sq->ctrl;
206 int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
208 #endif /* HW_NVME_H */