qjson: Give each of the six structural chars its own token type
[qemu/ar7.git] / target-arm / internals.h
blob347998c8bef942f9d02107a9f2dd4b5f94290c12
1 /*
2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target-arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 /* register banks for CPU modes */
29 #define BANK_USRSYS 0
30 #define BANK_SVC 1
31 #define BANK_ABT 2
32 #define BANK_UND 3
33 #define BANK_IRQ 4
34 #define BANK_FIQ 5
35 #define BANK_HYP 6
36 #define BANK_MON 7
38 static inline bool excp_is_internal(int excp)
40 /* Return true if this exception number represents a QEMU-internal
41 * exception that will not be passed to the guest.
43 return excp == EXCP_INTERRUPT
44 || excp == EXCP_HLT
45 || excp == EXCP_DEBUG
46 || excp == EXCP_HALTED
47 || excp == EXCP_EXCEPTION_EXIT
48 || excp == EXCP_KERNEL_TRAP
49 || excp == EXCP_SEMIHOST
50 || excp == EXCP_STREX;
53 /* Exception names for debug logging; note that not all of these
54 * precisely correspond to architectural exceptions.
56 static const char * const excnames[] = {
57 [EXCP_UDEF] = "Undefined Instruction",
58 [EXCP_SWI] = "SVC",
59 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
60 [EXCP_DATA_ABORT] = "Data Abort",
61 [EXCP_IRQ] = "IRQ",
62 [EXCP_FIQ] = "FIQ",
63 [EXCP_BKPT] = "Breakpoint",
64 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
65 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
66 [EXCP_STREX] = "QEMU intercept of STREX",
67 [EXCP_HVC] = "Hypervisor Call",
68 [EXCP_HYP_TRAP] = "Hypervisor Trap",
69 [EXCP_SMC] = "Secure Monitor Call",
70 [EXCP_VIRQ] = "Virtual IRQ",
71 [EXCP_VFIQ] = "Virtual FIQ",
72 [EXCP_SEMIHOST] = "Semihosting call",
75 static inline void arm_log_exception(int idx)
77 if (qemu_loglevel_mask(CPU_LOG_INT)) {
78 const char *exc = NULL;
80 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
81 exc = excnames[idx];
83 if (!exc) {
84 exc = "unknown";
86 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
90 /* Scale factor for generic timers, ie number of ns per tick.
91 * This gives a 62.5MHz timer.
93 #define GTIMER_SCALE 16
96 * For AArch64, map a given EL to an index in the banked_spsr array.
97 * Note that this mapping and the AArch32 mapping defined in bank_number()
98 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
99 * mandated mapping between each other.
101 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
103 static const unsigned int map[4] = {
104 [1] = BANK_SVC, /* EL1. */
105 [2] = BANK_HYP, /* EL2. */
106 [3] = BANK_MON, /* EL3. */
108 assert(el >= 1 && el <= 3);
109 return map[el];
112 int bank_number(int mode);
113 void switch_mode(CPUARMState *, int);
114 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
115 void arm_translate_init(void);
117 enum arm_fprounding {
118 FPROUNDING_TIEEVEN,
119 FPROUNDING_POSINF,
120 FPROUNDING_NEGINF,
121 FPROUNDING_ZERO,
122 FPROUNDING_TIEAWAY,
123 FPROUNDING_ODD
126 int arm_rmode_to_sf(int rmode);
128 static inline void aarch64_save_sp(CPUARMState *env, int el)
130 if (env->pstate & PSTATE_SP) {
131 env->sp_el[el] = env->xregs[31];
132 } else {
133 env->sp_el[0] = env->xregs[31];
137 static inline void aarch64_restore_sp(CPUARMState *env, int el)
139 if (env->pstate & PSTATE_SP) {
140 env->xregs[31] = env->sp_el[el];
141 } else {
142 env->xregs[31] = env->sp_el[0];
146 static inline void update_spsel(CPUARMState *env, uint32_t imm)
148 unsigned int cur_el = arm_current_el(env);
149 /* Update PSTATE SPSel bit; this requires us to update the
150 * working stack pointer in xregs[31].
152 if (!((imm ^ env->pstate) & PSTATE_SP)) {
153 return;
155 aarch64_save_sp(env, cur_el);
156 env->pstate = deposit32(env->pstate, 0, 1, imm);
158 /* We rely on illegal updates to SPsel from EL0 to get trapped
159 * at translation time.
161 assert(cur_el >= 1 && cur_el <= 3);
162 aarch64_restore_sp(env, cur_el);
166 * arm_pamax
167 * @cpu: ARMCPU
169 * Returns the implementation defined bit-width of physical addresses.
170 * The ARMv8 reference manuals refer to this as PAMax().
172 static inline unsigned int arm_pamax(ARMCPU *cpu)
174 static const unsigned int pamax_map[] = {
175 [0] = 32,
176 [1] = 36,
177 [2] = 40,
178 [3] = 42,
179 [4] = 44,
180 [5] = 48,
182 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
184 /* id_aa64mmfr0 is a read-only register so values outside of the
185 * supported mappings can be considered an implementation error. */
186 assert(parange < ARRAY_SIZE(pamax_map));
187 return pamax_map[parange];
190 /* Return true if extended addresses are enabled.
191 * This is always the case if our translation regime is 64 bit,
192 * but depends on TTBCR.EAE for 32 bit.
194 static inline bool extended_addresses_enabled(CPUARMState *env)
196 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
197 return arm_el_is_aa64(env, 1) ||
198 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
201 /* Valid Syndrome Register EC field values */
202 enum arm_exception_class {
203 EC_UNCATEGORIZED = 0x00,
204 EC_WFX_TRAP = 0x01,
205 EC_CP15RTTRAP = 0x03,
206 EC_CP15RRTTRAP = 0x04,
207 EC_CP14RTTRAP = 0x05,
208 EC_CP14DTTRAP = 0x06,
209 EC_ADVSIMDFPACCESSTRAP = 0x07,
210 EC_FPIDTRAP = 0x08,
211 EC_CP14RRTTRAP = 0x0c,
212 EC_ILLEGALSTATE = 0x0e,
213 EC_AA32_SVC = 0x11,
214 EC_AA32_HVC = 0x12,
215 EC_AA32_SMC = 0x13,
216 EC_AA64_SVC = 0x15,
217 EC_AA64_HVC = 0x16,
218 EC_AA64_SMC = 0x17,
219 EC_SYSTEMREGISTERTRAP = 0x18,
220 EC_INSNABORT = 0x20,
221 EC_INSNABORT_SAME_EL = 0x21,
222 EC_PCALIGNMENT = 0x22,
223 EC_DATAABORT = 0x24,
224 EC_DATAABORT_SAME_EL = 0x25,
225 EC_SPALIGNMENT = 0x26,
226 EC_AA32_FPTRAP = 0x28,
227 EC_AA64_FPTRAP = 0x2c,
228 EC_SERROR = 0x2f,
229 EC_BREAKPOINT = 0x30,
230 EC_BREAKPOINT_SAME_EL = 0x31,
231 EC_SOFTWARESTEP = 0x32,
232 EC_SOFTWARESTEP_SAME_EL = 0x33,
233 EC_WATCHPOINT = 0x34,
234 EC_WATCHPOINT_SAME_EL = 0x35,
235 EC_AA32_BKPT = 0x38,
236 EC_VECTORCATCH = 0x3a,
237 EC_AA64_BKPT = 0x3c,
240 #define ARM_EL_EC_SHIFT 26
241 #define ARM_EL_IL_SHIFT 25
242 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
244 /* Utility functions for constructing various kinds of syndrome value.
245 * Note that in general we follow the AArch64 syndrome values; in a
246 * few cases the value in HSR for exceptions taken to AArch32 Hyp
247 * mode differs slightly, so if we ever implemented Hyp mode then the
248 * syndrome value would need some massaging on exception entry.
249 * (One example of this is that AArch64 defaults to IL bit set for
250 * exceptions which don't specifically indicate information about the
251 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
253 static inline uint32_t syn_uncategorized(void)
255 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
258 static inline uint32_t syn_aa64_svc(uint32_t imm16)
260 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
263 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
265 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
268 static inline uint32_t syn_aa64_smc(uint32_t imm16)
270 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
273 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
275 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
276 | (is_thumb ? 0 : ARM_EL_IL);
279 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
281 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
284 static inline uint32_t syn_aa32_smc(void)
286 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
289 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
291 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
294 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
296 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
297 | (is_thumb ? 0 : ARM_EL_IL);
300 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
301 int crn, int crm, int rt,
302 int isread)
304 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
305 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
306 | (crm << 1) | isread;
309 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
310 int crn, int crm, int rt, int isread,
311 bool is_thumb)
313 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
314 | (is_thumb ? 0 : ARM_EL_IL)
315 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
316 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
319 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
320 int crn, int crm, int rt, int isread,
321 bool is_thumb)
323 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
324 | (is_thumb ? 0 : ARM_EL_IL)
325 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
326 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
329 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
330 int rt, int rt2, int isread,
331 bool is_thumb)
333 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
334 | (is_thumb ? 0 : ARM_EL_IL)
335 | (cv << 24) | (cond << 20) | (opc1 << 16)
336 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
339 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
340 int rt, int rt2, int isread,
341 bool is_thumb)
343 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
344 | (is_thumb ? 0 : ARM_EL_IL)
345 | (cv << 24) | (cond << 20) | (opc1 << 16)
346 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
349 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
351 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
352 | (is_thumb ? 0 : ARM_EL_IL)
353 | (cv << 24) | (cond << 20);
356 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
358 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
359 | (ea << 9) | (s1ptw << 7) | fsc;
362 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
363 int wnr, int fsc)
365 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
366 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
369 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
371 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
372 | (isv << 24) | (ex << 6) | 0x22;
375 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
377 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
378 | (cm << 8) | (wnr << 6) | 0x22;
381 static inline uint32_t syn_breakpoint(int same_el)
383 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
384 | ARM_EL_IL | 0x22;
387 static inline uint32_t syn_wfx(int cv, int cond, int ti)
389 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
390 (cv << 24) | (cond << 20) | ti;
393 /* Update a QEMU watchpoint based on the information the guest has set in the
394 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
396 void hw_watchpoint_update(ARMCPU *cpu, int n);
397 /* Update the QEMU watchpoints for every guest watchpoint. This does a
398 * complete delete-and-reinstate of the QEMU watchpoint list and so is
399 * suitable for use after migration or on reset.
401 void hw_watchpoint_update_all(ARMCPU *cpu);
402 /* Update a QEMU breakpoint based on the information the guest has set in the
403 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
405 void hw_breakpoint_update(ARMCPU *cpu, int n);
406 /* Update the QEMU breakpoints for every guest breakpoint. This does a
407 * complete delete-and-reinstate of the QEMU breakpoint list and so is
408 * suitable for use after migration or on reset.
410 void hw_breakpoint_update_all(ARMCPU *cpu);
412 /* Callback function for when a watchpoint or breakpoint triggers. */
413 void arm_debug_excp_handler(CPUState *cs);
415 #ifdef CONFIG_USER_ONLY
416 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
418 return false;
420 #else
421 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
422 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
423 /* Actually handle a PSCI call */
424 void arm_handle_psci_call(ARMCPU *cpu);
425 #endif
428 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
429 * @s2addr: Address that caused a fault at stage 2
430 * @stage2: True if we faulted at stage 2
431 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
433 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
434 struct ARMMMUFaultInfo {
435 target_ulong s2addr;
436 bool stage2;
437 bool s1ptw;
440 /* Do a page table walk and add page to TLB if possible */
441 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
442 uint32_t *fsr, ARMMMUFaultInfo *fi);
444 #endif