hw: Don't use hw_error() for machine initialization errors
[qemu/ar7.git] / hw / ppc / spapr_iommu.c
blobed28565d8c62863b3b4f0ab3587b36fc30572204
1 /*
2 * QEMU sPAPR IOMMU (TCE) code
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "hw/hw.h"
20 #include "sysemu/kvm.h"
21 #include "hw/qdev.h"
22 #include "kvm_ppc.h"
23 #include "sysemu/dma.h"
24 #include "exec/address-spaces.h"
25 #include "trace.h"
27 #include "hw/ppc/spapr.h"
28 #include "hw/ppc/spapr_vio.h"
30 #include <libfdt.h>
32 enum sPAPRTCEAccess {
33 SPAPR_TCE_FAULT = 0,
34 SPAPR_TCE_RO = 1,
35 SPAPR_TCE_WO = 2,
36 SPAPR_TCE_RW = 3,
39 #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
40 #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
42 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
44 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
46 sPAPRTCETable *tcet;
48 if (liobn & 0xFFFFFFFF00000000ULL) {
49 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
50 liobn);
51 return NULL;
54 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
55 if (tcet->liobn == (uint32_t)liobn) {
56 return tcet;
60 return NULL;
63 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
65 switch (tce & SPAPR_TCE_RW) {
66 case SPAPR_TCE_FAULT:
67 return IOMMU_NONE;
68 case SPAPR_TCE_RO:
69 return IOMMU_RO;
70 case SPAPR_TCE_WO:
71 return IOMMU_WO;
72 default: /* SPAPR_TCE_RW */
73 return IOMMU_RW;
77 /* Called from RCU critical section */
78 static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
79 bool is_write)
81 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
82 uint64_t tce;
83 IOMMUTLBEntry ret = {
84 .target_as = &address_space_memory,
85 .iova = 0,
86 .translated_addr = 0,
87 .addr_mask = ~(hwaddr)0,
88 .perm = IOMMU_NONE,
91 if ((addr >> tcet->page_shift) < tcet->nb_table) {
92 /* Check if we are in bound */
93 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
95 tce = tcet->table[addr >> tcet->page_shift];
96 ret.iova = addr & page_mask;
97 ret.translated_addr = tce & page_mask;
98 ret.addr_mask = ~page_mask;
99 ret.perm = spapr_tce_iommu_access_flags(tce);
101 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
102 ret.addr_mask);
104 return ret;
107 static int spapr_tce_table_post_load(void *opaque, int version_id)
109 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
111 if (tcet->vdev) {
112 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
115 return 0;
118 static const VMStateDescription vmstate_spapr_tce_table = {
119 .name = "spapr_iommu",
120 .version_id = 2,
121 .minimum_version_id = 2,
122 .post_load = spapr_tce_table_post_load,
123 .fields = (VMStateField []) {
124 /* Sanity check */
125 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
126 VMSTATE_UINT32_EQUAL(nb_table, sPAPRTCETable),
128 /* IOMMU state */
129 VMSTATE_BOOL(bypass, sPAPRTCETable),
130 VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t),
132 VMSTATE_END_OF_LIST()
136 static MemoryRegionIOMMUOps spapr_iommu_ops = {
137 .translate = spapr_tce_translate_iommu,
140 static int spapr_tce_table_realize(DeviceState *dev)
142 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
143 uint64_t window_size = (uint64_t)tcet->nb_table << tcet->page_shift;
145 if (kvm_enabled() && !(window_size >> 32)) {
146 tcet->table = kvmppc_create_spapr_tce(tcet->liobn,
147 window_size,
148 &tcet->fd,
149 tcet->need_vfio);
152 if (!tcet->table) {
153 size_t table_size = tcet->nb_table * sizeof(uint64_t);
154 tcet->table = g_malloc0(table_size);
157 trace_spapr_iommu_new_table(tcet->liobn, tcet, tcet->table, tcet->fd);
159 memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops,
160 "iommu-spapr",
161 (uint64_t)tcet->nb_table << tcet->page_shift);
163 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
165 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
166 tcet);
168 return 0;
171 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
173 size_t table_size = tcet->nb_table * sizeof(uint64_t);
174 void *newtable;
176 if (need_vfio == tcet->need_vfio) {
177 /* Nothing to do */
178 return;
181 if (!need_vfio) {
182 /* FIXME: We don't support transition back to KVM accelerated
183 * TCEs yet */
184 return;
187 tcet->need_vfio = true;
189 if (tcet->fd < 0) {
190 /* Table is already in userspace, nothing to be do */
191 return;
194 newtable = g_malloc(table_size);
195 memcpy(newtable, tcet->table, table_size);
197 kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table);
199 tcet->fd = -1;
200 tcet->table = newtable;
203 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
204 uint64_t bus_offset,
205 uint32_t page_shift,
206 uint32_t nb_table,
207 bool need_vfio)
209 sPAPRTCETable *tcet;
210 char tmp[64];
212 if (spapr_tce_find_by_liobn(liobn)) {
213 fprintf(stderr, "Attempted to create TCE table with duplicate"
214 " LIOBN 0x%x\n", liobn);
215 return NULL;
218 if (!nb_table) {
219 return NULL;
222 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
223 tcet->liobn = liobn;
224 tcet->bus_offset = bus_offset;
225 tcet->page_shift = page_shift;
226 tcet->nb_table = nb_table;
227 tcet->need_vfio = need_vfio;
229 snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
230 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
232 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
234 return tcet;
237 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
239 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
241 QLIST_REMOVE(tcet, list);
243 if (!kvm_enabled() ||
244 (kvmppc_remove_spapr_tce(tcet->table, tcet->fd,
245 tcet->nb_table) != 0)) {
246 g_free(tcet->table);
250 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
252 return &tcet->iommu;
255 static void spapr_tce_reset(DeviceState *dev)
257 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
258 size_t table_size = tcet->nb_table * sizeof(uint64_t);
260 memset(tcet->table, 0, table_size);
263 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
264 target_ulong tce)
266 IOMMUTLBEntry entry;
267 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
268 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
270 if (index >= tcet->nb_table) {
271 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
272 TARGET_FMT_lx "\n", ioba);
273 return H_PARAMETER;
276 tcet->table[index] = tce;
278 entry.target_as = &address_space_memory,
279 entry.iova = ioba & page_mask;
280 entry.translated_addr = tce & page_mask;
281 entry.addr_mask = ~page_mask;
282 entry.perm = spapr_tce_iommu_access_flags(tce);
283 memory_region_notify_iommu(&tcet->iommu, entry);
285 return H_SUCCESS;
288 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
289 sPAPRMachineState *spapr,
290 target_ulong opcode, target_ulong *args)
292 int i;
293 target_ulong liobn = args[0];
294 target_ulong ioba = args[1];
295 target_ulong ioba1 = ioba;
296 target_ulong tce_list = args[2];
297 target_ulong npages = args[3];
298 target_ulong ret = H_PARAMETER, tce = 0;
299 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
300 CPUState *cs = CPU(cpu);
301 hwaddr page_mask, page_size;
303 if (!tcet) {
304 return H_PARAMETER;
307 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
308 return H_PARAMETER;
311 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
312 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
313 ioba &= page_mask;
315 for (i = 0; i < npages; ++i, ioba += page_size) {
316 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
318 ret = put_tce_emu(tcet, ioba, tce);
319 if (ret) {
320 break;
324 /* Trace last successful or the first problematic entry */
325 i = i ? (i - 1) : 0;
326 if (SPAPR_IS_PCI_LIOBN(liobn)) {
327 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
328 } else {
329 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
331 return ret;
334 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
335 target_ulong opcode, target_ulong *args)
337 int i;
338 target_ulong liobn = args[0];
339 target_ulong ioba = args[1];
340 target_ulong tce_value = args[2];
341 target_ulong npages = args[3];
342 target_ulong ret = H_PARAMETER;
343 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
344 hwaddr page_mask, page_size;
346 if (!tcet) {
347 return H_PARAMETER;
350 if (npages > tcet->nb_table) {
351 return H_PARAMETER;
354 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
355 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
356 ioba &= page_mask;
358 for (i = 0; i < npages; ++i, ioba += page_size) {
359 ret = put_tce_emu(tcet, ioba, tce_value);
360 if (ret) {
361 break;
364 if (SPAPR_IS_PCI_LIOBN(liobn)) {
365 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
366 } else {
367 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
370 return ret;
373 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
374 target_ulong opcode, target_ulong *args)
376 target_ulong liobn = args[0];
377 target_ulong ioba = args[1];
378 target_ulong tce = args[2];
379 target_ulong ret = H_PARAMETER;
380 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
382 if (tcet) {
383 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
385 ioba &= page_mask;
387 ret = put_tce_emu(tcet, ioba, tce);
389 if (SPAPR_IS_PCI_LIOBN(liobn)) {
390 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
391 } else {
392 trace_spapr_iommu_put(liobn, ioba, tce, ret);
395 return ret;
398 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
399 target_ulong *tce)
401 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
403 if (index >= tcet->nb_table) {
404 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
405 TARGET_FMT_lx "\n", ioba);
406 return H_PARAMETER;
409 *tce = tcet->table[index];
411 return H_SUCCESS;
414 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
415 target_ulong opcode, target_ulong *args)
417 target_ulong liobn = args[0];
418 target_ulong ioba = args[1];
419 target_ulong tce = 0;
420 target_ulong ret = H_PARAMETER;
421 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
423 if (tcet) {
424 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
426 ioba &= page_mask;
428 ret = get_tce_emu(tcet, ioba, &tce);
429 if (!ret) {
430 args[0] = tce;
433 if (SPAPR_IS_PCI_LIOBN(liobn)) {
434 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
435 } else {
436 trace_spapr_iommu_get(liobn, ioba, ret, tce);
439 return ret;
442 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
443 uint32_t liobn, uint64_t window, uint32_t size)
445 uint32_t dma_prop[5];
446 int ret;
448 dma_prop[0] = cpu_to_be32(liobn);
449 dma_prop[1] = cpu_to_be32(window >> 32);
450 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
451 dma_prop[3] = 0; /* window size is 32 bits */
452 dma_prop[4] = cpu_to_be32(size);
454 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
455 if (ret < 0) {
456 return ret;
459 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
460 if (ret < 0) {
461 return ret;
464 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
465 if (ret < 0) {
466 return ret;
469 return 0;
472 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
473 sPAPRTCETable *tcet)
475 if (!tcet) {
476 return 0;
479 return spapr_dma_dt(fdt, node_off, propname,
480 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
483 static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
485 DeviceClass *dc = DEVICE_CLASS(klass);
486 dc->init = spapr_tce_table_realize;
487 dc->reset = spapr_tce_reset;
488 dc->unrealize = spapr_tce_table_unrealize;
490 QLIST_INIT(&spapr_tce_tables);
492 /* hcall-tce */
493 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
494 spapr_register_hypercall(H_GET_TCE, h_get_tce);
495 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
496 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
499 static TypeInfo spapr_tce_table_info = {
500 .name = TYPE_SPAPR_TCE_TABLE,
501 .parent = TYPE_DEVICE,
502 .instance_size = sizeof(sPAPRTCETable),
503 .class_init = spapr_tce_table_class_init,
506 static void register_types(void)
508 type_register_static(&spapr_tce_table_info);
511 type_init(register_types);