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Add API to get memory mapping
[qemu/ar7.git] / hw / fdc.c
blob30d34e3f1ddd6859ac2b3ce8932b88a80e9df2bf
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 typedef struct FDCtrl FDCtrl;
66
67 /* Floppy disk drive emulation */
68 typedef enum FDiskFlags {
69 FDISK_DBL_SIDES = 0x01,
70 } FDiskFlags;
71
72 typedef struct FDrive {
73 FDCtrl *fdctrl;
74 BlockDriverState *bs;
75 /* Drive status */
76 FDriveType drive;
77 uint8_t perpendicular; /* 2.88 MB access mode */
78 /* Position */
79 uint8_t head;
80 uint8_t track;
81 uint8_t sect;
82 /* Media */
83 FDiskFlags flags;
84 uint8_t last_sect; /* Nb sector per track */
85 uint8_t max_track; /* Nb of tracks */
86 uint16_t bps; /* Bytes per sector */
87 uint8_t ro; /* Is read-only */
88 uint8_t media_changed; /* Is media changed */
89 uint8_t media_rate; /* Data rate of medium */
90 } FDrive;
91
92 static void fd_init(FDrive *drv)
93 {
94 /* Drive */
95 drv->drive = FDRIVE_DRV_NONE;
96 drv->perpendicular = 0;
97 /* Disk */
98 drv->last_sect = 0;
99 drv->max_track = 0;
100 }
101
102 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
103
104 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
105 uint8_t last_sect, uint8_t num_sides)
106 {
107 return (((track * num_sides) + head) * last_sect) + sect - 1;
108 }
109
110 /* Returns current position, in sectors, for given drive */
111 static int fd_sector(FDrive *drv)
112 {
113 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
114 NUM_SIDES(drv));
115 }
116
117 /* Seek to a new position:
118 * returns 0 if already on right track
119 * returns 1 if track changed
120 * returns 2 if track is invalid
121 * returns 3 if sector is invalid
122 * returns 4 if seek is disabled
123 */
124 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
125 int enable_seek)
126 {
127 uint32_t sector;
128 int ret;
129
130 if (track > drv->max_track ||
131 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 2;
137 }
138 if (sect > drv->last_sect) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 3;
144 }
145 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
146 ret = 0;
147 if (sector != fd_sector(drv)) {
148 #if 0
149 if (!enable_seek) {
150 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
151 head, track, sect, 1, drv->max_track, drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track)
157 ret = 1;
158 drv->track = track;
159 drv->sect = sect;
160 }
161
162 return ret;
163 }
164
165 /* Set drive back to track 0 */
166 static void fd_recalibrate(FDrive *drv)
167 {
168 FLOPPY_DPRINTF("recalibrate\n");
169 drv->head = 0;
170 drv->track = 0;
171 drv->sect = 1;
172 }
173
174 /* Revalidate a disk drive after a disk change */
175 static void fd_revalidate(FDrive *drv)
176 {
177 int nb_heads, max_track, last_sect, ro;
178 FDriveType drive;
179 FDriveRate rate;
180
181 FLOPPY_DPRINTF("revalidate\n");
182 if (drv->bs != NULL) {
183 ro = bdrv_is_read_only(drv->bs);
184 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
185 &last_sect, drv->drive, &drive, &rate);
186 if (!bdrv_is_inserted(drv->bs)) {
187 FLOPPY_DPRINTF("No disk in drive\n");
188 } else if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
189 FLOPPY_DPRINTF("User defined disk (%d %d %d)\n",
190 nb_heads - 1, max_track, last_sect);
191 } else {
192 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
193 max_track, last_sect, ro ? "ro" : "rw");
194 }
195 if (nb_heads == 1) {
196 drv->flags &= ~FDISK_DBL_SIDES;
197 } else {
198 drv->flags |= FDISK_DBL_SIDES;
199 }
200 drv->max_track = max_track;
201 drv->last_sect = last_sect;
202 drv->ro = ro;
203 drv->drive = drive;
204 drv->media_rate = rate;
205 } else {
206 FLOPPY_DPRINTF("No drive connected\n");
207 drv->last_sect = 0;
208 drv->max_track = 0;
209 drv->flags &= ~FDISK_DBL_SIDES;
210 }
211 }
212
213 /********************************************************/
214 /* Intel 82078 floppy disk controller emulation */
215
216 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
217 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
218 static int fdctrl_transfer_handler (void *opaque, int nchan,
219 int dma_pos, int dma_len);
220 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
221 static FDrive *get_cur_drv(FDCtrl *fdctrl);
222
223 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
224 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
225 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
226 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
227 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
228 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
229 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
230 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
231 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
232 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
233 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
234 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
235
236 enum {
237 FD_DIR_WRITE = 0,
238 FD_DIR_READ = 1,
239 FD_DIR_SCANE = 2,
240 FD_DIR_SCANL = 3,
241 FD_DIR_SCANH = 4,
242 };
243
244 enum {
245 FD_STATE_MULTI = 0x01, /* multi track flag */
246 FD_STATE_FORMAT = 0x02, /* format flag */
247 FD_STATE_SEEK = 0x04, /* seek flag */
248 };
249
250 enum {
251 FD_REG_SRA = 0x00,
252 FD_REG_SRB = 0x01,
253 FD_REG_DOR = 0x02,
254 FD_REG_TDR = 0x03,
255 FD_REG_MSR = 0x04,
256 FD_REG_DSR = 0x04,
257 FD_REG_FIFO = 0x05,
258 FD_REG_DIR = 0x07,
259 FD_REG_CCR = 0x07,
260 };
261
262 enum {
263 FD_CMD_READ_TRACK = 0x02,
264 FD_CMD_SPECIFY = 0x03,
265 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
266 FD_CMD_WRITE = 0x05,
267 FD_CMD_READ = 0x06,
268 FD_CMD_RECALIBRATE = 0x07,
269 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
270 FD_CMD_WRITE_DELETED = 0x09,
271 FD_CMD_READ_ID = 0x0a,
272 FD_CMD_READ_DELETED = 0x0c,
273 FD_CMD_FORMAT_TRACK = 0x0d,
274 FD_CMD_DUMPREG = 0x0e,
275 FD_CMD_SEEK = 0x0f,
276 FD_CMD_VERSION = 0x10,
277 FD_CMD_SCAN_EQUAL = 0x11,
278 FD_CMD_PERPENDICULAR_MODE = 0x12,
279 FD_CMD_CONFIGURE = 0x13,
280 FD_CMD_LOCK = 0x14,
281 FD_CMD_VERIFY = 0x16,
282 FD_CMD_POWERDOWN_MODE = 0x17,
283 FD_CMD_PART_ID = 0x18,
284 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
285 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
286 FD_CMD_SAVE = 0x2e,
287 FD_CMD_OPTION = 0x33,
288 FD_CMD_RESTORE = 0x4e,
289 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
290 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
291 FD_CMD_FORMAT_AND_WRITE = 0xcd,
292 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
293 };
294
295 enum {
296 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
297 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
298 FD_CONFIG_POLL = 0x10, /* Poll enabled */
299 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
300 FD_CONFIG_EIS = 0x40, /* No implied seeks */
301 };
302
303 enum {
304 FD_SR0_EQPMT = 0x10,
305 FD_SR0_SEEK = 0x20,
306 FD_SR0_ABNTERM = 0x40,
307 FD_SR0_INVCMD = 0x80,
308 FD_SR0_RDYCHG = 0xc0,
309 };
310
311 enum {
312 FD_SR1_MA = 0x01, /* Missing address mark */
313 FD_SR1_NW = 0x02, /* Not writable */
314 FD_SR1_EC = 0x80, /* End of cylinder */
315 };
316
317 enum {
318 FD_SR2_SNS = 0x04, /* Scan not satisfied */
319 FD_SR2_SEH = 0x08, /* Scan equal hit */
320 };
321
322 enum {
323 FD_SRA_DIR = 0x01,
324 FD_SRA_nWP = 0x02,
325 FD_SRA_nINDX = 0x04,
326 FD_SRA_HDSEL = 0x08,
327 FD_SRA_nTRK0 = 0x10,
328 FD_SRA_STEP = 0x20,
329 FD_SRA_nDRV2 = 0x40,
330 FD_SRA_INTPEND = 0x80,
331 };
332
333 enum {
334 FD_SRB_MTR0 = 0x01,
335 FD_SRB_MTR1 = 0x02,
336 FD_SRB_WGATE = 0x04,
337 FD_SRB_RDATA = 0x08,
338 FD_SRB_WDATA = 0x10,
339 FD_SRB_DR0 = 0x20,
340 };
341
342 enum {
343 #if MAX_FD == 4
344 FD_DOR_SELMASK = 0x03,
345 #else
346 FD_DOR_SELMASK = 0x01,
347 #endif
348 FD_DOR_nRESET = 0x04,
349 FD_DOR_DMAEN = 0x08,
350 FD_DOR_MOTEN0 = 0x10,
351 FD_DOR_MOTEN1 = 0x20,
352 FD_DOR_MOTEN2 = 0x40,
353 FD_DOR_MOTEN3 = 0x80,
354 };
355
356 enum {
357 #if MAX_FD == 4
358 FD_TDR_BOOTSEL = 0x0c,
359 #else
360 FD_TDR_BOOTSEL = 0x04,
361 #endif
362 };
363
364 enum {
365 FD_DSR_DRATEMASK= 0x03,
366 FD_DSR_PWRDOWN = 0x40,
367 FD_DSR_SWRESET = 0x80,
368 };
369
370 enum {
371 FD_MSR_DRV0BUSY = 0x01,
372 FD_MSR_DRV1BUSY = 0x02,
373 FD_MSR_DRV2BUSY = 0x04,
374 FD_MSR_DRV3BUSY = 0x08,
375 FD_MSR_CMDBUSY = 0x10,
376 FD_MSR_NONDMA = 0x20,
377 FD_MSR_DIO = 0x40,
378 FD_MSR_RQM = 0x80,
379 };
380
381 enum {
382 FD_DIR_DSKCHG = 0x80,
383 };
384
385 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
386 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
387 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
388
389 struct FDCtrl {
390 MemoryRegion iomem;
391 qemu_irq irq;
392 /* Controller state */
393 QEMUTimer *result_timer;
394 int dma_chann;
395 /* Controller's identification */
396 uint8_t version;
397 /* HW */
398 uint8_t sra;
399 uint8_t srb;
400 uint8_t dor;
401 uint8_t dor_vmstate; /* only used as temp during vmstate */
402 uint8_t tdr;
403 uint8_t dsr;
404 uint8_t msr;
405 uint8_t cur_drv;
406 uint8_t status0;
407 uint8_t status1;
408 uint8_t status2;
409 /* Command FIFO */
410 uint8_t *fifo;
411 int32_t fifo_size;
412 uint32_t data_pos;
413 uint32_t data_len;
414 uint8_t data_state;
415 uint8_t data_dir;
416 uint8_t eot; /* last wanted sector */
417 /* States kept only to be returned back */
418 /* precompensation */
419 uint8_t precomp_trk;
420 uint8_t config;
421 uint8_t lock;
422 /* Power down config (also with status regB access mode */
423 uint8_t pwrd;
424 /* Floppy drives */
425 uint8_t num_floppies;
426 /* Sun4m quirks? */
427 int sun4m;
428 FDrive drives[MAX_FD];
429 int reset_sensei;
430 uint32_t check_media_rate;
431 /* Timers state */
432 uint8_t timer0;
433 uint8_t timer1;
434 };
435
436 typedef struct FDCtrlSysBus {
437 SysBusDevice busdev;
438 struct FDCtrl state;
439 } FDCtrlSysBus;
440
441 typedef struct FDCtrlISABus {
442 ISADevice busdev;
443 uint32_t iobase;
444 uint32_t irq;
445 uint32_t dma;
446 struct FDCtrl state;
447 int32_t bootindexA;
448 int32_t bootindexB;
449 } FDCtrlISABus;
450
451 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
452 {
453 FDCtrl *fdctrl = opaque;
454 uint32_t retval;
455
456 reg &= 7;
457 switch (reg) {
458 case FD_REG_SRA:
459 retval = fdctrl_read_statusA(fdctrl);
460 break;
461 case FD_REG_SRB:
462 retval = fdctrl_read_statusB(fdctrl);
463 break;
464 case FD_REG_DOR:
465 retval = fdctrl_read_dor(fdctrl);
466 break;
467 case FD_REG_TDR:
468 retval = fdctrl_read_tape(fdctrl);
469 break;
470 case FD_REG_MSR:
471 retval = fdctrl_read_main_status(fdctrl);
472 break;
473 case FD_REG_FIFO:
474 retval = fdctrl_read_data(fdctrl);
475 break;
476 case FD_REG_DIR:
477 retval = fdctrl_read_dir(fdctrl);
478 break;
479 default:
480 retval = (uint32_t)(-1);
481 break;
482 }
483 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
484
485 return retval;
486 }
487
488 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
489 {
490 FDCtrl *fdctrl = opaque;
491
492 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
493
494 reg &= 7;
495 switch (reg) {
496 case FD_REG_DOR:
497 fdctrl_write_dor(fdctrl, value);
498 break;
499 case FD_REG_TDR:
500 fdctrl_write_tape(fdctrl, value);
501 break;
502 case FD_REG_DSR:
503 fdctrl_write_rate(fdctrl, value);
504 break;
505 case FD_REG_FIFO:
506 fdctrl_write_data(fdctrl, value);
507 break;
508 case FD_REG_CCR:
509 fdctrl_write_ccr(fdctrl, value);
510 break;
511 default:
512 break;
513 }
514 }
515
516 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
517 unsigned ize)
518 {
519 return fdctrl_read(opaque, (uint32_t)reg);
520 }
521
522 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
523 uint64_t value, unsigned size)
524 {
525 fdctrl_write(opaque, (uint32_t)reg, value);
526 }
527
528 static const MemoryRegionOps fdctrl_mem_ops = {
529 .read = fdctrl_read_mem,
530 .write = fdctrl_write_mem,
531 .endianness = DEVICE_NATIVE_ENDIAN,
532 };
533
534 static const MemoryRegionOps fdctrl_mem_strict_ops = {
535 .read = fdctrl_read_mem,
536 .write = fdctrl_write_mem,
537 .endianness = DEVICE_NATIVE_ENDIAN,
538 .valid = {
539 .min_access_size = 1,
540 .max_access_size = 1,
541 },
542 };
543
544 static bool fdrive_media_changed_needed(void *opaque)
545 {
546 FDrive *drive = opaque;
547
548 return (drive->bs != NULL && drive->media_changed != 1);
549 }
550
551 static const VMStateDescription vmstate_fdrive_media_changed = {
552 .name = "fdrive/media_changed",
553 .version_id = 1,
554 .minimum_version_id = 1,
555 .minimum_version_id_old = 1,
556 .fields = (VMStateField[]) {
557 VMSTATE_UINT8(media_changed, FDrive),
558 VMSTATE_END_OF_LIST()
559 }
560 };
561
562 static bool fdrive_media_rate_needed(void *opaque)
563 {
564 FDrive *drive = opaque;
565
566 return drive->fdctrl->check_media_rate;
567 }
568
569 static const VMStateDescription vmstate_fdrive_media_rate = {
570 .name = "fdrive/media_rate",
571 .version_id = 1,
572 .minimum_version_id = 1,
573 .minimum_version_id_old = 1,
574 .fields = (VMStateField[]) {
575 VMSTATE_UINT8(media_rate, FDrive),
576 VMSTATE_END_OF_LIST()
577 }
578 };
579
580 static const VMStateDescription vmstate_fdrive = {
581 .name = "fdrive",
582 .version_id = 1,
583 .minimum_version_id = 1,
584 .minimum_version_id_old = 1,
585 .fields = (VMStateField[]) {
586 VMSTATE_UINT8(head, FDrive),
587 VMSTATE_UINT8(track, FDrive),
588 VMSTATE_UINT8(sect, FDrive),
589 VMSTATE_END_OF_LIST()
590 },
591 .subsections = (VMStateSubsection[]) {
592 {
593 .vmsd = &vmstate_fdrive_media_changed,
594 .needed = &fdrive_media_changed_needed,
595 } , {
596 .vmsd = &vmstate_fdrive_media_rate,
597 .needed = &fdrive_media_rate_needed,
598 } , {
599 /* empty */
600 }
601 }
602 };
603
604 static void fdc_pre_save(void *opaque)
605 {
606 FDCtrl *s = opaque;
607
608 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
609 }
610
611 static int fdc_post_load(void *opaque, int version_id)
612 {
613 FDCtrl *s = opaque;
614
615 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
616 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
617 return 0;
618 }
619
620 static const VMStateDescription vmstate_fdc = {
621 .name = "fdc",
622 .version_id = 2,
623 .minimum_version_id = 2,
624 .minimum_version_id_old = 2,
625 .pre_save = fdc_pre_save,
626 .post_load = fdc_post_load,
627 .fields = (VMStateField []) {
628 /* Controller State */
629 VMSTATE_UINT8(sra, FDCtrl),
630 VMSTATE_UINT8(srb, FDCtrl),
631 VMSTATE_UINT8(dor_vmstate, FDCtrl),
632 VMSTATE_UINT8(tdr, FDCtrl),
633 VMSTATE_UINT8(dsr, FDCtrl),
634 VMSTATE_UINT8(msr, FDCtrl),
635 VMSTATE_UINT8(status0, FDCtrl),
636 VMSTATE_UINT8(status1, FDCtrl),
637 VMSTATE_UINT8(status2, FDCtrl),
638 /* Command FIFO */
639 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
640 uint8_t),
641 VMSTATE_UINT32(data_pos, FDCtrl),
642 VMSTATE_UINT32(data_len, FDCtrl),
643 VMSTATE_UINT8(data_state, FDCtrl),
644 VMSTATE_UINT8(data_dir, FDCtrl),
645 VMSTATE_UINT8(eot, FDCtrl),
646 /* States kept only to be returned back */
647 VMSTATE_UINT8(timer0, FDCtrl),
648 VMSTATE_UINT8(timer1, FDCtrl),
649 VMSTATE_UINT8(precomp_trk, FDCtrl),
650 VMSTATE_UINT8(config, FDCtrl),
651 VMSTATE_UINT8(lock, FDCtrl),
652 VMSTATE_UINT8(pwrd, FDCtrl),
653 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
654 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
655 vmstate_fdrive, FDrive),
656 VMSTATE_END_OF_LIST()
657 }
658 };
659
660 static void fdctrl_external_reset_sysbus(DeviceState *d)
661 {
662 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
663 FDCtrl *s = &sys->state;
664
665 fdctrl_reset(s, 0);
666 }
667
668 static void fdctrl_external_reset_isa(DeviceState *d)
669 {
670 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
671 FDCtrl *s = &isa->state;
672
673 fdctrl_reset(s, 0);
674 }
675
676 static void fdctrl_handle_tc(void *opaque, int irq, int level)
677 {
678 //FDCtrl *s = opaque;
679
680 if (level) {
681 // XXX
682 FLOPPY_DPRINTF("TC pulsed\n");
683 }
684 }
685
686 /* Change IRQ state */
687 static void fdctrl_reset_irq(FDCtrl *fdctrl)
688 {
689 if (!(fdctrl->sra & FD_SRA_INTPEND))
690 return;
691 FLOPPY_DPRINTF("Reset interrupt\n");
692 qemu_set_irq(fdctrl->irq, 0);
693 fdctrl->sra &= ~FD_SRA_INTPEND;
694 }
695
696 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
697 {
698 /* Sparc mutation */
699 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
700 /* XXX: not sure */
701 fdctrl->msr &= ~FD_MSR_CMDBUSY;
702 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
703 fdctrl->status0 = status0;
704 return;
705 }
706 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
707 qemu_set_irq(fdctrl->irq, 1);
708 fdctrl->sra |= FD_SRA_INTPEND;
709 }
710 if (status0 & FD_SR0_SEEK) {
711 FDrive *cur_drv;
712 /* A seek clears the disk change line (if a disk is inserted) */
713 cur_drv = get_cur_drv(fdctrl);
714 if (cur_drv->bs != NULL && bdrv_is_inserted(cur_drv->bs)) {
715 cur_drv->media_changed = 0;
716 }
717 }
718
719 fdctrl->reset_sensei = 0;
720 fdctrl->status0 = status0;
721 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
722 }
723
724 /* Reset controller */
725 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
726 {
727 int i;
728
729 FLOPPY_DPRINTF("reset controller\n");
730 fdctrl_reset_irq(fdctrl);
731 /* Initialise controller */
732 fdctrl->sra = 0;
733 fdctrl->srb = 0xc0;
734 if (!fdctrl->drives[1].bs)
735 fdctrl->sra |= FD_SRA_nDRV2;
736 fdctrl->cur_drv = 0;
737 fdctrl->dor = FD_DOR_nRESET;
738 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
739 fdctrl->msr = FD_MSR_RQM;
740 /* FIFO state */
741 fdctrl->data_pos = 0;
742 fdctrl->data_len = 0;
743 fdctrl->data_state = 0;
744 fdctrl->data_dir = FD_DIR_WRITE;
745 for (i = 0; i < MAX_FD; i++)
746 fd_recalibrate(&fdctrl->drives[i]);
747 fdctrl_reset_fifo(fdctrl);
748 if (do_irq) {
749 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
750 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
751 }
752 }
753
754 static inline FDrive *drv0(FDCtrl *fdctrl)
755 {
756 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
757 }
758
759 static inline FDrive *drv1(FDCtrl *fdctrl)
760 {
761 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
762 return &fdctrl->drives[1];
763 else
764 return &fdctrl->drives[0];
765 }
766
767 #if MAX_FD == 4
768 static inline FDrive *drv2(FDCtrl *fdctrl)
769 {
770 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
771 return &fdctrl->drives[2];
772 else
773 return &fdctrl->drives[1];
774 }
775
776 static inline FDrive *drv3(FDCtrl *fdctrl)
777 {
778 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
779 return &fdctrl->drives[3];
780 else
781 return &fdctrl->drives[2];
782 }
783 #endif
784
785 static FDrive *get_cur_drv(FDCtrl *fdctrl)
786 {
787 switch (fdctrl->cur_drv) {
788 case 0: return drv0(fdctrl);
789 case 1: return drv1(fdctrl);
790 #if MAX_FD == 4
791 case 2: return drv2(fdctrl);
792 case 3: return drv3(fdctrl);
793 #endif
794 default: return NULL;
795 }
796 }
797
798 /* Status A register : 0x00 (read-only) */
799 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
800 {
801 uint32_t retval = fdctrl->sra;
802
803 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
804
805 return retval;
806 }
807
808 /* Status B register : 0x01 (read-only) */
809 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
810 {
811 uint32_t retval = fdctrl->srb;
812
813 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
814
815 return retval;
816 }
817
818 /* Digital output register : 0x02 */
819 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
820 {
821 uint32_t retval = fdctrl->dor;
822
823 /* Selected drive */
824 retval |= fdctrl->cur_drv;
825 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
826
827 return retval;
828 }
829
830 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
831 {
832 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
833
834 /* Motors */
835 if (value & FD_DOR_MOTEN0)
836 fdctrl->srb |= FD_SRB_MTR0;
837 else
838 fdctrl->srb &= ~FD_SRB_MTR0;
839 if (value & FD_DOR_MOTEN1)
840 fdctrl->srb |= FD_SRB_MTR1;
841 else
842 fdctrl->srb &= ~FD_SRB_MTR1;
843
844 /* Drive */
845 if (value & 1)
846 fdctrl->srb |= FD_SRB_DR0;
847 else
848 fdctrl->srb &= ~FD_SRB_DR0;
849
850 /* Reset */
851 if (!(value & FD_DOR_nRESET)) {
852 if (fdctrl->dor & FD_DOR_nRESET) {
853 FLOPPY_DPRINTF("controller enter RESET state\n");
854 }
855 } else {
856 if (!(fdctrl->dor & FD_DOR_nRESET)) {
857 FLOPPY_DPRINTF("controller out of RESET state\n");
858 fdctrl_reset(fdctrl, 1);
859 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
860 }
861 }
862 /* Selected drive */
863 fdctrl->cur_drv = value & FD_DOR_SELMASK;
864
865 fdctrl->dor = value;
866 }
867
868 /* Tape drive register : 0x03 */
869 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
870 {
871 uint32_t retval = fdctrl->tdr;
872
873 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
874
875 return retval;
876 }
877
878 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
879 {
880 /* Reset mode */
881 if (!(fdctrl->dor & FD_DOR_nRESET)) {
882 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
883 return;
884 }
885 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
886 /* Disk boot selection indicator */
887 fdctrl->tdr = value & FD_TDR_BOOTSEL;
888 /* Tape indicators: never allow */
889 }
890
891 /* Main status register : 0x04 (read) */
892 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
893 {
894 uint32_t retval = fdctrl->msr;
895
896 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
897 fdctrl->dor |= FD_DOR_nRESET;
898
899 /* Sparc mutation */
900 if (fdctrl->sun4m) {
901 retval |= FD_MSR_DIO;
902 fdctrl_reset_irq(fdctrl);
903 };
904
905 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
906
907 return retval;
908 }
909
910 /* Data select rate register : 0x04 (write) */
911 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
912 {
913 /* Reset mode */
914 if (!(fdctrl->dor & FD_DOR_nRESET)) {
915 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
916 return;
917 }
918 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
919 /* Reset: autoclear */
920 if (value & FD_DSR_SWRESET) {
921 fdctrl->dor &= ~FD_DOR_nRESET;
922 fdctrl_reset(fdctrl, 1);
923 fdctrl->dor |= FD_DOR_nRESET;
924 }
925 if (value & FD_DSR_PWRDOWN) {
926 fdctrl_reset(fdctrl, 1);
927 }
928 fdctrl->dsr = value;
929 }
930
931 /* Configuration control register: 0x07 (write) */
932 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
933 {
934 /* Reset mode */
935 if (!(fdctrl->dor & FD_DOR_nRESET)) {
936 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
937 return;
938 }
939 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
940
941 /* Only the rate selection bits used in AT mode, and we
942 * store those in the DSR.
943 */
944 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
945 (value & FD_DSR_DRATEMASK);
946 }
947
948 static int fdctrl_media_changed(FDrive *drv)
949 {
950 return drv->media_changed;
951 }
952
953 /* Digital input register : 0x07 (read-only) */
954 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
955 {
956 uint32_t retval = 0;
957
958 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
959 retval |= FD_DIR_DSKCHG;
960 }
961 if (retval != 0) {
962 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
963 }
964
965 return retval;
966 }
967
968 /* FIFO state control */
969 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
970 {
971 fdctrl->data_dir = FD_DIR_WRITE;
972 fdctrl->data_pos = 0;
973 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
974 }
975
976 /* Set FIFO status for the host to read */
977 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
978 {
979 fdctrl->data_dir = FD_DIR_READ;
980 fdctrl->data_len = fifo_len;
981 fdctrl->data_pos = 0;
982 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
983 if (do_irq)
984 fdctrl_raise_irq(fdctrl, 0x00);
985 }
986
987 /* Set an error: unimplemented/unknown command */
988 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
989 {
990 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
991 fdctrl->fifo[0] = FD_SR0_INVCMD;
992 fdctrl_set_fifo(fdctrl, 1, 0);
993 }
994
995 /* Seek to next sector */
996 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
997 {
998 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
999 cur_drv->head, cur_drv->track, cur_drv->sect,
1000 fd_sector(cur_drv));
1001 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1002 error in fact */
1003 if (cur_drv->sect >= cur_drv->last_sect ||
1004 cur_drv->sect == fdctrl->eot) {
1005 cur_drv->sect = 1;
1006 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1007 if (cur_drv->head == 0 &&
1008 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1009 cur_drv->head = 1;
1010 } else {
1011 cur_drv->head = 0;
1012 cur_drv->track++;
1013 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1014 return 0;
1015 }
1016 } else {
1017 cur_drv->track++;
1018 return 0;
1019 }
1020 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1021 cur_drv->head, cur_drv->track,
1022 cur_drv->sect, fd_sector(cur_drv));
1023 } else {
1024 cur_drv->sect++;
1025 }
1026 return 1;
1027 }
1028
1029 /* Callback for transfer end (stop or abort) */
1030 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1031 uint8_t status1, uint8_t status2)
1032 {
1033 FDrive *cur_drv;
1034
1035 cur_drv = get_cur_drv(fdctrl);
1036 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1037 status0, status1, status2,
1038 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1039 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1040 fdctrl->fifo[1] = status1;
1041 fdctrl->fifo[2] = status2;
1042 fdctrl->fifo[3] = cur_drv->track;
1043 fdctrl->fifo[4] = cur_drv->head;
1044 fdctrl->fifo[5] = cur_drv->sect;
1045 fdctrl->fifo[6] = FD_SECTOR_SC;
1046 fdctrl->data_dir = FD_DIR_READ;
1047 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1048 DMA_release_DREQ(fdctrl->dma_chann);
1049 }
1050 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1051 fdctrl->msr &= ~FD_MSR_NONDMA;
1052 fdctrl_set_fifo(fdctrl, 7, 1);
1053 }
1054
1055 /* Prepare a data transfer (either DMA or FIFO) */
1056 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1057 {
1058 FDrive *cur_drv;
1059 uint8_t kh, kt, ks;
1060 int did_seek = 0;
1061
1062 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1063 cur_drv = get_cur_drv(fdctrl);
1064 kt = fdctrl->fifo[2];
1065 kh = fdctrl->fifo[3];
1066 ks = fdctrl->fifo[4];
1067 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1068 GET_CUR_DRV(fdctrl), kh, kt, ks,
1069 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1070 NUM_SIDES(cur_drv)));
1071 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1072 case 2:
1073 /* sect too big */
1074 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1075 fdctrl->fifo[3] = kt;
1076 fdctrl->fifo[4] = kh;
1077 fdctrl->fifo[5] = ks;
1078 return;
1079 case 3:
1080 /* track too big */
1081 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1082 fdctrl->fifo[3] = kt;
1083 fdctrl->fifo[4] = kh;
1084 fdctrl->fifo[5] = ks;
1085 return;
1086 case 4:
1087 /* No seek enabled */
1088 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1089 fdctrl->fifo[3] = kt;
1090 fdctrl->fifo[4] = kh;
1091 fdctrl->fifo[5] = ks;
1092 return;
1093 case 1:
1094 did_seek = 1;
1095 break;
1096 default:
1097 break;
1098 }
1099
1100 /* Check the data rate. If the programmed data rate does not match
1101 * the currently inserted medium, the operation has to fail. */
1102 if (fdctrl->check_media_rate &&
1103 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1104 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1105 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1106 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1107 fdctrl->fifo[3] = kt;
1108 fdctrl->fifo[4] = kh;
1109 fdctrl->fifo[5] = ks;
1110 return;
1111 }
1112
1113 /* Set the FIFO state */
1114 fdctrl->data_dir = direction;
1115 fdctrl->data_pos = 0;
1116 fdctrl->msr |= FD_MSR_CMDBUSY;
1117 if (fdctrl->fifo[0] & 0x80)
1118 fdctrl->data_state |= FD_STATE_MULTI;
1119 else
1120 fdctrl->data_state &= ~FD_STATE_MULTI;
1121 if (did_seek)
1122 fdctrl->data_state |= FD_STATE_SEEK;
1123 else
1124 fdctrl->data_state &= ~FD_STATE_SEEK;
1125 if (fdctrl->fifo[5] == 00) {
1126 fdctrl->data_len = fdctrl->fifo[8];
1127 } else {
1128 int tmp;
1129 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1130 tmp = (fdctrl->fifo[6] - ks + 1);
1131 if (fdctrl->fifo[0] & 0x80)
1132 tmp += fdctrl->fifo[6];
1133 fdctrl->data_len *= tmp;
1134 }
1135 fdctrl->eot = fdctrl->fifo[6];
1136 if (fdctrl->dor & FD_DOR_DMAEN) {
1137 int dma_mode;
1138 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1139 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1140 dma_mode = (dma_mode >> 2) & 3;
1141 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1142 dma_mode, direction,
1143 (128 << fdctrl->fifo[5]) *
1144 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1145 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1146 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1147 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1148 (direction == FD_DIR_READ && dma_mode == 1)) {
1149 /* No access is allowed until DMA transfer has completed */
1150 fdctrl->msr &= ~FD_MSR_RQM;
1151 /* Now, we just have to wait for the DMA controller to
1152 * recall us...
1153 */
1154 DMA_hold_DREQ(fdctrl->dma_chann);
1155 DMA_schedule(fdctrl->dma_chann);
1156 return;
1157 } else {
1158 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1159 }
1160 }
1161 FLOPPY_DPRINTF("start non-DMA transfer\n");
1162 fdctrl->msr |= FD_MSR_NONDMA;
1163 if (direction != FD_DIR_WRITE)
1164 fdctrl->msr |= FD_MSR_DIO;
1165 /* IO based transfer: calculate len */
1166 fdctrl_raise_irq(fdctrl, 0x00);
1167
1168 return;
1169 }
1170
1171 /* Prepare a transfer of deleted data */
1172 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1173 {
1174 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1175
1176 /* We don't handle deleted data,
1177 * so we don't return *ANYTHING*
1178 */
1179 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1180 }
1181
1182 /* handlers for DMA transfers */
1183 static int fdctrl_transfer_handler (void *opaque, int nchan,
1184 int dma_pos, int dma_len)
1185 {
1186 FDCtrl *fdctrl;
1187 FDrive *cur_drv;
1188 int len, start_pos, rel_pos;
1189 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1190
1191 fdctrl = opaque;
1192 if (fdctrl->msr & FD_MSR_RQM) {
1193 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1194 return 0;
1195 }
1196 cur_drv = get_cur_drv(fdctrl);
1197 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1198 fdctrl->data_dir == FD_DIR_SCANH)
1199 status2 = FD_SR2_SNS;
1200 if (dma_len > fdctrl->data_len)
1201 dma_len = fdctrl->data_len;
1202 if (cur_drv->bs == NULL) {
1203 if (fdctrl->data_dir == FD_DIR_WRITE)
1204 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1205 else
1206 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1207 len = 0;
1208 goto transfer_error;
1209 }
1210 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1211 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1212 len = dma_len - fdctrl->data_pos;
1213 if (len + rel_pos > FD_SECTOR_LEN)
1214 len = FD_SECTOR_LEN - rel_pos;
1215 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1216 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1217 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1218 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1219 fd_sector(cur_drv) * FD_SECTOR_LEN);
1220 if (fdctrl->data_dir != FD_DIR_WRITE ||
1221 len < FD_SECTOR_LEN || rel_pos != 0) {
1222 /* READ & SCAN commands and realign to a sector for WRITE */
1223 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1224 fdctrl->fifo, 1) < 0) {
1225 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1226 fd_sector(cur_drv));
1227 /* Sure, image size is too small... */
1228 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1229 }
1230 }
1231 switch (fdctrl->data_dir) {
1232 case FD_DIR_READ:
1233 /* READ commands */
1234 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1235 fdctrl->data_pos, len);
1236 break;
1237 case FD_DIR_WRITE:
1238 /* WRITE commands */
1239 if (cur_drv->ro) {
1240 /* Handle readonly medium early, no need to do DMA, touch the
1241 * LED or attempt any writes. A real floppy doesn't attempt
1242 * to write to readonly media either. */
1243 fdctrl_stop_transfer(fdctrl,
1244 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1245 0x00);
1246 goto transfer_error;
1247 }
1248
1249 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1250 fdctrl->data_pos, len);
1251 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1252 fdctrl->fifo, 1) < 0) {
1253 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1254 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1255 goto transfer_error;
1256 }
1257 break;
1258 default:
1259 /* SCAN commands */
1260 {
1261 uint8_t tmpbuf[FD_SECTOR_LEN];
1262 int ret;
1263 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1264 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1265 if (ret == 0) {
1266 status2 = FD_SR2_SEH;
1267 goto end_transfer;
1268 }
1269 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1270 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1271 status2 = 0x00;
1272 goto end_transfer;
1273 }
1274 }
1275 break;
1276 }
1277 fdctrl->data_pos += len;
1278 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1279 if (rel_pos == 0) {
1280 /* Seek to next sector */
1281 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1282 break;
1283 }
1284 }
1285 end_transfer:
1286 len = fdctrl->data_pos - start_pos;
1287 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1288 fdctrl->data_pos, len, fdctrl->data_len);
1289 if (fdctrl->data_dir == FD_DIR_SCANE ||
1290 fdctrl->data_dir == FD_DIR_SCANL ||
1291 fdctrl->data_dir == FD_DIR_SCANH)
1292 status2 = FD_SR2_SEH;
1293 if (FD_DID_SEEK(fdctrl->data_state))
1294 status0 |= FD_SR0_SEEK;
1295 fdctrl->data_len -= len;
1296 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1297 transfer_error:
1298
1299 return len;
1300 }
1301
1302 /* Data register : 0x05 */
1303 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1304 {
1305 FDrive *cur_drv;
1306 uint32_t retval = 0;
1307 int pos;
1308
1309 cur_drv = get_cur_drv(fdctrl);
1310 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1311 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1312 FLOPPY_ERROR("controller not ready for reading\n");
1313 return 0;
1314 }
1315 pos = fdctrl->data_pos;
1316 if (fdctrl->msr & FD_MSR_NONDMA) {
1317 pos %= FD_SECTOR_LEN;
1318 if (pos == 0) {
1319 if (fdctrl->data_pos != 0)
1320 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1321 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1322 fd_sector(cur_drv));
1323 return 0;
1324 }
1325 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1326 FLOPPY_DPRINTF("error getting sector %d\n",
1327 fd_sector(cur_drv));
1328 /* Sure, image size is too small... */
1329 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1330 }
1331 }
1332 }
1333 retval = fdctrl->fifo[pos];
1334 if (++fdctrl->data_pos == fdctrl->data_len) {
1335 fdctrl->data_pos = 0;
1336 /* Switch from transfer mode to status mode
1337 * then from status mode to command mode
1338 */
1339 if (fdctrl->msr & FD_MSR_NONDMA) {
1340 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1341 } else {
1342 fdctrl_reset_fifo(fdctrl);
1343 fdctrl_reset_irq(fdctrl);
1344 }
1345 }
1346 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1347
1348 return retval;
1349 }
1350
1351 static void fdctrl_format_sector(FDCtrl *fdctrl)
1352 {
1353 FDrive *cur_drv;
1354 uint8_t kh, kt, ks;
1355
1356 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1357 cur_drv = get_cur_drv(fdctrl);
1358 kt = fdctrl->fifo[6];
1359 kh = fdctrl->fifo[7];
1360 ks = fdctrl->fifo[8];
1361 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1362 GET_CUR_DRV(fdctrl), kh, kt, ks,
1363 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1364 NUM_SIDES(cur_drv)));
1365 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1366 case 2:
1367 /* sect too big */
1368 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1369 fdctrl->fifo[3] = kt;
1370 fdctrl->fifo[4] = kh;
1371 fdctrl->fifo[5] = ks;
1372 return;
1373 case 3:
1374 /* track too big */
1375 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1376 fdctrl->fifo[3] = kt;
1377 fdctrl->fifo[4] = kh;
1378 fdctrl->fifo[5] = ks;
1379 return;
1380 case 4:
1381 /* No seek enabled */
1382 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1383 fdctrl->fifo[3] = kt;
1384 fdctrl->fifo[4] = kh;
1385 fdctrl->fifo[5] = ks;
1386 return;
1387 case 1:
1388 fdctrl->data_state |= FD_STATE_SEEK;
1389 break;
1390 default:
1391 break;
1392 }
1393 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1394 if (cur_drv->bs == NULL ||
1395 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1396 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1397 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1398 } else {
1399 if (cur_drv->sect == cur_drv->last_sect) {
1400 fdctrl->data_state &= ~FD_STATE_FORMAT;
1401 /* Last sector done */
1402 if (FD_DID_SEEK(fdctrl->data_state))
1403 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1404 else
1405 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1406 } else {
1407 /* More to do */
1408 fdctrl->data_pos = 0;
1409 fdctrl->data_len = 4;
1410 }
1411 }
1412 }
1413
1414 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1415 {
1416 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1417 fdctrl->fifo[0] = fdctrl->lock << 4;
1418 fdctrl_set_fifo(fdctrl, 1, 0);
1419 }
1420
1421 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1422 {
1423 FDrive *cur_drv = get_cur_drv(fdctrl);
1424
1425 /* Drives position */
1426 fdctrl->fifo[0] = drv0(fdctrl)->track;
1427 fdctrl->fifo[1] = drv1(fdctrl)->track;
1428 #if MAX_FD == 4
1429 fdctrl->fifo[2] = drv2(fdctrl)->track;
1430 fdctrl->fifo[3] = drv3(fdctrl)->track;
1431 #else
1432 fdctrl->fifo[2] = 0;
1433 fdctrl->fifo[3] = 0;
1434 #endif
1435 /* timers */
1436 fdctrl->fifo[4] = fdctrl->timer0;
1437 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1438 fdctrl->fifo[6] = cur_drv->last_sect;
1439 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1440 (cur_drv->perpendicular << 2);
1441 fdctrl->fifo[8] = fdctrl->config;
1442 fdctrl->fifo[9] = fdctrl->precomp_trk;
1443 fdctrl_set_fifo(fdctrl, 10, 0);
1444 }
1445
1446 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1447 {
1448 /* Controller's version */
1449 fdctrl->fifo[0] = fdctrl->version;
1450 fdctrl_set_fifo(fdctrl, 1, 0);
1451 }
1452
1453 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1454 {
1455 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1456 fdctrl_set_fifo(fdctrl, 1, 0);
1457 }
1458
1459 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1460 {
1461 FDrive *cur_drv = get_cur_drv(fdctrl);
1462
1463 /* Drives position */
1464 drv0(fdctrl)->track = fdctrl->fifo[3];
1465 drv1(fdctrl)->track = fdctrl->fifo[4];
1466 #if MAX_FD == 4
1467 drv2(fdctrl)->track = fdctrl->fifo[5];
1468 drv3(fdctrl)->track = fdctrl->fifo[6];
1469 #endif
1470 /* timers */
1471 fdctrl->timer0 = fdctrl->fifo[7];
1472 fdctrl->timer1 = fdctrl->fifo[8];
1473 cur_drv->last_sect = fdctrl->fifo[9];
1474 fdctrl->lock = fdctrl->fifo[10] >> 7;
1475 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1476 fdctrl->config = fdctrl->fifo[11];
1477 fdctrl->precomp_trk = fdctrl->fifo[12];
1478 fdctrl->pwrd = fdctrl->fifo[13];
1479 fdctrl_reset_fifo(fdctrl);
1480 }
1481
1482 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1483 {
1484 FDrive *cur_drv = get_cur_drv(fdctrl);
1485
1486 fdctrl->fifo[0] = 0;
1487 fdctrl->fifo[1] = 0;
1488 /* Drives position */
1489 fdctrl->fifo[2] = drv0(fdctrl)->track;
1490 fdctrl->fifo[3] = drv1(fdctrl)->track;
1491 #if MAX_FD == 4
1492 fdctrl->fifo[4] = drv2(fdctrl)->track;
1493 fdctrl->fifo[5] = drv3(fdctrl)->track;
1494 #else
1495 fdctrl->fifo[4] = 0;
1496 fdctrl->fifo[5] = 0;
1497 #endif
1498 /* timers */
1499 fdctrl->fifo[6] = fdctrl->timer0;
1500 fdctrl->fifo[7] = fdctrl->timer1;
1501 fdctrl->fifo[8] = cur_drv->last_sect;
1502 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1503 (cur_drv->perpendicular << 2);
1504 fdctrl->fifo[10] = fdctrl->config;
1505 fdctrl->fifo[11] = fdctrl->precomp_trk;
1506 fdctrl->fifo[12] = fdctrl->pwrd;
1507 fdctrl->fifo[13] = 0;
1508 fdctrl->fifo[14] = 0;
1509 fdctrl_set_fifo(fdctrl, 15, 0);
1510 }
1511
1512 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1513 {
1514 FDrive *cur_drv = get_cur_drv(fdctrl);
1515
1516 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1517 qemu_mod_timer(fdctrl->result_timer,
1518 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1519 }
1520
1521 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1522 {
1523 FDrive *cur_drv;
1524
1525 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1526 cur_drv = get_cur_drv(fdctrl);
1527 fdctrl->data_state |= FD_STATE_FORMAT;
1528 if (fdctrl->fifo[0] & 0x80)
1529 fdctrl->data_state |= FD_STATE_MULTI;
1530 else
1531 fdctrl->data_state &= ~FD_STATE_MULTI;
1532 fdctrl->data_state &= ~FD_STATE_SEEK;
1533 cur_drv->bps =
1534 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1535 #if 0
1536 cur_drv->last_sect =
1537 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1538 fdctrl->fifo[3] / 2;
1539 #else
1540 cur_drv->last_sect = fdctrl->fifo[3];
1541 #endif
1542 /* TODO: implement format using DMA expected by the Bochs BIOS
1543 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1544 * the sector with the specified fill byte
1545 */
1546 fdctrl->data_state &= ~FD_STATE_FORMAT;
1547 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1548 }
1549
1550 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1551 {
1552 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1553 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1554 if (fdctrl->fifo[2] & 1)
1555 fdctrl->dor &= ~FD_DOR_DMAEN;
1556 else
1557 fdctrl->dor |= FD_DOR_DMAEN;
1558 /* No result back */
1559 fdctrl_reset_fifo(fdctrl);
1560 }
1561
1562 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1563 {
1564 FDrive *cur_drv;
1565
1566 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1567 cur_drv = get_cur_drv(fdctrl);
1568 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1569 /* 1 Byte status back */
1570 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1571 (cur_drv->track == 0 ? 0x10 : 0x00) |
1572 (cur_drv->head << 2) |
1573 GET_CUR_DRV(fdctrl) |
1574 0x28;
1575 fdctrl_set_fifo(fdctrl, 1, 0);
1576 }
1577
1578 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1579 {
1580 FDrive *cur_drv;
1581
1582 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1583 cur_drv = get_cur_drv(fdctrl);
1584 fd_recalibrate(cur_drv);
1585 fdctrl_reset_fifo(fdctrl);
1586 /* Raise Interrupt */
1587 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1588 }
1589
1590 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1591 {
1592 FDrive *cur_drv = get_cur_drv(fdctrl);
1593
1594 if(fdctrl->reset_sensei > 0) {
1595 fdctrl->fifo[0] =
1596 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1597 fdctrl->reset_sensei--;
1598 } else {
1599 /* XXX: status0 handling is broken for read/write
1600 commands, so we do this hack. It should be suppressed
1601 ASAP */
1602 fdctrl->fifo[0] =
1603 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1604 }
1605
1606 fdctrl->fifo[1] = cur_drv->track;
1607 fdctrl_set_fifo(fdctrl, 2, 0);
1608 fdctrl_reset_irq(fdctrl);
1609 fdctrl->status0 = FD_SR0_RDYCHG;
1610 }
1611
1612 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1613 {
1614 FDrive *cur_drv;
1615
1616 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1617 cur_drv = get_cur_drv(fdctrl);
1618 fdctrl_reset_fifo(fdctrl);
1619 /* The seek command just sends step pulses to the drive and doesn't care if
1620 * there is a medium inserted of if it's banging the head against the drive.
1621 */
1622 if (fdctrl->fifo[2] > cur_drv->max_track) {
1623 cur_drv->track = cur_drv->max_track;
1624 } else {
1625 cur_drv->track = fdctrl->fifo[2];
1626 }
1627 /* Raise Interrupt */
1628 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1629 }
1630
1631 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1632 {
1633 FDrive *cur_drv = get_cur_drv(fdctrl);
1634
1635 if (fdctrl->fifo[1] & 0x80)
1636 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1637 /* No result back */
1638 fdctrl_reset_fifo(fdctrl);
1639 }
1640
1641 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1642 {
1643 fdctrl->config = fdctrl->fifo[2];
1644 fdctrl->precomp_trk = fdctrl->fifo[3];
1645 /* No result back */
1646 fdctrl_reset_fifo(fdctrl);
1647 }
1648
1649 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1650 {
1651 fdctrl->pwrd = fdctrl->fifo[1];
1652 fdctrl->fifo[0] = fdctrl->fifo[1];
1653 fdctrl_set_fifo(fdctrl, 1, 0);
1654 }
1655
1656 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1657 {
1658 /* No result back */
1659 fdctrl_reset_fifo(fdctrl);
1660 }
1661
1662 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1663 {
1664 FDrive *cur_drv = get_cur_drv(fdctrl);
1665
1666 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1667 /* Command parameters done */
1668 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1669 fdctrl->fifo[0] = fdctrl->fifo[1];
1670 fdctrl->fifo[2] = 0;
1671 fdctrl->fifo[3] = 0;
1672 fdctrl_set_fifo(fdctrl, 4, 0);
1673 } else {
1674 fdctrl_reset_fifo(fdctrl);
1675 }
1676 } else if (fdctrl->data_len > 7) {
1677 /* ERROR */
1678 fdctrl->fifo[0] = 0x80 |
1679 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1680 fdctrl_set_fifo(fdctrl, 1, 0);
1681 }
1682 }
1683
1684 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1685 {
1686 FDrive *cur_drv;
1687
1688 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1689 cur_drv = get_cur_drv(fdctrl);
1690 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1691 cur_drv->track = cur_drv->max_track - 1;
1692 } else {
1693 cur_drv->track += fdctrl->fifo[2];
1694 }
1695 fdctrl_reset_fifo(fdctrl);
1696 /* Raise Interrupt */
1697 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1698 }
1699
1700 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1701 {
1702 FDrive *cur_drv;
1703
1704 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1705 cur_drv = get_cur_drv(fdctrl);
1706 if (fdctrl->fifo[2] > cur_drv->track) {
1707 cur_drv->track = 0;
1708 } else {
1709 cur_drv->track -= fdctrl->fifo[2];
1710 }
1711 fdctrl_reset_fifo(fdctrl);
1712 /* Raise Interrupt */
1713 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1714 }
1715
1716 static const struct {
1717 uint8_t value;
1718 uint8_t mask;
1719 const char* name;
1720 int parameters;
1721 void (*handler)(FDCtrl *fdctrl, int direction);
1722 int direction;
1723 } handlers[] = {
1724 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1725 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1726 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1727 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1728 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1729 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1730 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1731 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1732 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1733 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1734 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1735 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1736 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1737 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1738 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1739 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1740 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1741 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1742 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1743 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1744 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1745 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1746 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1747 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1748 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1749 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1750 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1751 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1752 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1753 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1754 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1755 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1756 };
1757 /* Associate command to an index in the 'handlers' array */
1758 static uint8_t command_to_handler[256];
1759
1760 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1761 {
1762 FDrive *cur_drv;
1763 int pos;
1764
1765 /* Reset mode */
1766 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1767 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1768 return;
1769 }
1770 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1771 FLOPPY_ERROR("controller not ready for writing\n");
1772 return;
1773 }
1774 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1775 /* Is it write command time ? */
1776 if (fdctrl->msr & FD_MSR_NONDMA) {
1777 /* FIFO data write */
1778 pos = fdctrl->data_pos++;
1779 pos %= FD_SECTOR_LEN;
1780 fdctrl->fifo[pos] = value;
1781 if (pos == FD_SECTOR_LEN - 1 ||
1782 fdctrl->data_pos == fdctrl->data_len) {
1783 cur_drv = get_cur_drv(fdctrl);
1784 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1785 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1786 return;
1787 }
1788 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1789 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1790 fd_sector(cur_drv));
1791 return;
1792 }
1793 }
1794 /* Switch from transfer mode to status mode
1795 * then from status mode to command mode
1796 */
1797 if (fdctrl->data_pos == fdctrl->data_len)
1798 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1799 return;
1800 }
1801 if (fdctrl->data_pos == 0) {
1802 /* Command */
1803 pos = command_to_handler[value & 0xff];
1804 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1805 fdctrl->data_len = handlers[pos].parameters + 1;
1806 fdctrl->msr |= FD_MSR_CMDBUSY;
1807 }
1808
1809 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1810 fdctrl->fifo[fdctrl->data_pos++] = value;
1811 if (fdctrl->data_pos == fdctrl->data_len) {
1812 /* We now have all parameters
1813 * and will be able to treat the command
1814 */
1815 if (fdctrl->data_state & FD_STATE_FORMAT) {
1816 fdctrl_format_sector(fdctrl);
1817 return;
1818 }
1819
1820 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1821 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1822 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1823 }
1824 }
1825
1826 static void fdctrl_result_timer(void *opaque)
1827 {
1828 FDCtrl *fdctrl = opaque;
1829 FDrive *cur_drv = get_cur_drv(fdctrl);
1830
1831 /* Pretend we are spinning.
1832 * This is needed for Coherent, which uses READ ID to check for
1833 * sector interleaving.
1834 */
1835 if (cur_drv->last_sect != 0) {
1836 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1837 }
1838 /* READ_ID can't automatically succeed! */
1839 if (fdctrl->check_media_rate &&
1840 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1841 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1842 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1843 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1844 } else {
1845 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1846 }
1847 }
1848
1849 static void fdctrl_change_cb(void *opaque, bool load)
1850 {
1851 FDrive *drive = opaque;
1852
1853 drive->media_changed = 1;
1854 fd_revalidate(drive);
1855 }
1856
1857 static const BlockDevOps fdctrl_block_ops = {
1858 .change_media_cb = fdctrl_change_cb,
1859 };
1860
1861 /* Init functions */
1862 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1863 {
1864 unsigned int i;
1865 FDrive *drive;
1866
1867 for (i = 0; i < MAX_FD; i++) {
1868 drive = &fdctrl->drives[i];
1869 drive->fdctrl = fdctrl;
1870
1871 if (drive->bs) {
1872 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1873 error_report("fdc doesn't support drive option werror");
1874 return -1;
1875 }
1876 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1877 error_report("fdc doesn't support drive option rerror");
1878 return -1;
1879 }
1880 }
1881
1882 fd_init(drive);
1883 fdctrl_change_cb(drive, 0);
1884 if (drive->bs) {
1885 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1886 }
1887 }
1888 return 0;
1889 }
1890
1891 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1892 target_phys_addr_t mmio_base, DriveInfo **fds)
1893 {
1894 FDCtrl *fdctrl;
1895 DeviceState *dev;
1896 FDCtrlSysBus *sys;
1897
1898 dev = qdev_create(NULL, "sysbus-fdc");
1899 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1900 fdctrl = &sys->state;
1901 fdctrl->dma_chann = dma_chann; /* FIXME */
1902 if (fds[0]) {
1903 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1904 }
1905 if (fds[1]) {
1906 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1907 }
1908 qdev_init_nofail(dev);
1909 sysbus_connect_irq(&sys->busdev, 0, irq);
1910 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1911 }
1912
1913 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1914 DriveInfo **fds, qemu_irq *fdc_tc)
1915 {
1916 DeviceState *dev;
1917 FDCtrlSysBus *sys;
1918
1919 dev = qdev_create(NULL, "SUNW,fdtwo");
1920 if (fds[0]) {
1921 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1922 }
1923 qdev_init_nofail(dev);
1924 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1925 sysbus_connect_irq(&sys->busdev, 0, irq);
1926 sysbus_mmio_map(&sys->busdev, 0, io_base);
1927 *fdc_tc = qdev_get_gpio_in(dev, 0);
1928 }
1929
1930 static int fdctrl_init_common(FDCtrl *fdctrl)
1931 {
1932 int i, j;
1933 static int command_tables_inited = 0;
1934
1935 /* Fill 'command_to_handler' lookup table */
1936 if (!command_tables_inited) {
1937 command_tables_inited = 1;
1938 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1939 for (j = 0; j < sizeof(command_to_handler); j++) {
1940 if ((j & handlers[i].mask) == handlers[i].value) {
1941 command_to_handler[j] = i;
1942 }
1943 }
1944 }
1945 }
1946
1947 FLOPPY_DPRINTF("init controller\n");
1948 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1949 fdctrl->fifo_size = 512;
1950 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1951 fdctrl_result_timer, fdctrl);
1952
1953 fdctrl->version = 0x90; /* Intel 82078 controller */
1954 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1955 fdctrl->num_floppies = MAX_FD;
1956
1957 if (fdctrl->dma_chann != -1)
1958 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1959 return fdctrl_connect_drives(fdctrl);
1960 }
1961
1962 static const MemoryRegionPortio fdc_portio_list[] = {
1963 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1964 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1965 PORTIO_END_OF_LIST(),
1966 };
1967
1968 static int isabus_fdc_init1(ISADevice *dev)
1969 {
1970 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1971 FDCtrl *fdctrl = &isa->state;
1972 int ret;
1973
1974 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
1975
1976 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
1977 fdctrl->dma_chann = isa->dma;
1978
1979 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
1980 ret = fdctrl_init_common(fdctrl);
1981
1982 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1983 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1984
1985 return ret;
1986 }
1987
1988 static int sysbus_fdc_init1(SysBusDevice *dev)
1989 {
1990 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1991 FDCtrl *fdctrl = &sys->state;
1992 int ret;
1993
1994 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
1995 sysbus_init_mmio(dev, &fdctrl->iomem);
1996 sysbus_init_irq(dev, &fdctrl->irq);
1997 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1998 fdctrl->dma_chann = -1;
1999
2000 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2001 ret = fdctrl_init_common(fdctrl);
2002
2003 return ret;
2004 }
2005
2006 static int sun4m_fdc_init1(SysBusDevice *dev)
2007 {
2008 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2009
2010 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2011 "fdctrl", 0x08);
2012 sysbus_init_mmio(dev, &fdctrl->iomem);
2013 sysbus_init_irq(dev, &fdctrl->irq);
2014 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2015
2016 fdctrl->sun4m = 1;
2017 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2018 return fdctrl_init_common(fdctrl);
2019 }
2020
2021 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2022 {
2023 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2024 FDCtrl *fdctrl = &isa->state;
2025 int i;
2026
2027 for (i = 0; i < MAX_FD; i++) {
2028 bs[i] = fdctrl->drives[i].bs;
2029 }
2030 }
2031
2032
2033 static const VMStateDescription vmstate_isa_fdc ={
2034 .name = "fdc",
2035 .version_id = 2,
2036 .minimum_version_id = 2,
2037 .fields = (VMStateField []) {
2038 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2039 VMSTATE_END_OF_LIST()
2040 }
2041 };
2042
2043 static Property isa_fdc_properties[] = {
2044 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2045 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2046 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2047 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2048 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2049 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2050 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2051 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2052 0, true),
2053 DEFINE_PROP_END_OF_LIST(),
2054 };
2055
2056 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2057 {
2058 DeviceClass *dc = DEVICE_CLASS(klass);
2059 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2060 ic->init = isabus_fdc_init1;
2061 dc->fw_name = "fdc";
2062 dc->no_user = 1;
2063 dc->reset = fdctrl_external_reset_isa;
2064 dc->vmsd = &vmstate_isa_fdc;
2065 dc->props = isa_fdc_properties;
2066 }
2067
2068 static TypeInfo isa_fdc_info = {
2069 .name = "isa-fdc",
2070 .parent = TYPE_ISA_DEVICE,
2071 .instance_size = sizeof(FDCtrlISABus),
2072 .class_init = isabus_fdc_class_init1,
2073 };
2074
2075 static const VMStateDescription vmstate_sysbus_fdc ={
2076 .name = "fdc",
2077 .version_id = 2,
2078 .minimum_version_id = 2,
2079 .fields = (VMStateField []) {
2080 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2081 VMSTATE_END_OF_LIST()
2082 }
2083 };
2084
2085 static Property sysbus_fdc_properties[] = {
2086 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2087 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2088 DEFINE_PROP_END_OF_LIST(),
2089 };
2090
2091 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2092 {
2093 DeviceClass *dc = DEVICE_CLASS(klass);
2094 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2095
2096 k->init = sysbus_fdc_init1;
2097 dc->reset = fdctrl_external_reset_sysbus;
2098 dc->vmsd = &vmstate_sysbus_fdc;
2099 dc->props = sysbus_fdc_properties;
2100 }
2101
2102 static TypeInfo sysbus_fdc_info = {
2103 .name = "sysbus-fdc",
2104 .parent = TYPE_SYS_BUS_DEVICE,
2105 .instance_size = sizeof(FDCtrlSysBus),
2106 .class_init = sysbus_fdc_class_init,
2107 };
2108
2109 static Property sun4m_fdc_properties[] = {
2110 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2111 DEFINE_PROP_END_OF_LIST(),
2112 };
2113
2114 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2115 {
2116 DeviceClass *dc = DEVICE_CLASS(klass);
2117 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2118
2119 k->init = sun4m_fdc_init1;
2120 dc->reset = fdctrl_external_reset_sysbus;
2121 dc->vmsd = &vmstate_sysbus_fdc;
2122 dc->props = sun4m_fdc_properties;
2123 }
2124
2125 static TypeInfo sun4m_fdc_info = {
2126 .name = "SUNW,fdtwo",
2127 .parent = TYPE_SYS_BUS_DEVICE,
2128 .instance_size = sizeof(FDCtrlSysBus),
2129 .class_init = sun4m_fdc_class_init,
2130 };
2131
2132 static void fdc_register_types(void)
2133 {
2134 type_register_static(&isa_fdc_info);
2135 type_register_static(&sysbus_fdc_info);
2136 type_register_static(&sun4m_fdc_info);
2137 }
2138
2139 type_init(fdc_register_types)
AR7 emulation for QEMU