6 #define CPUArchState struct CPUMIPSState
8 #include "qemu-common.h"
10 #include "mips-defs.h"
11 #include "exec/cpu-defs.h"
12 #include "fpu/softfloat.h"
16 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
19 #define MSA_WRLEN (128)
21 typedef union wr_t wr_t
;
23 int8_t b
[MSA_WRLEN
/8];
24 int16_t h
[MSA_WRLEN
/16];
25 int32_t w
[MSA_WRLEN
/32];
26 int64_t d
[MSA_WRLEN
/64];
29 typedef union fpr_t fpr_t
;
31 float64 fd
; /* ieee double precision */
32 float32 fs
[2];/* ieee single precision */
33 uint64_t d
; /* binary double fixed-point */
34 uint32_t w
[2]; /* binary single fixed-point */
35 /* FPU/MSA register mapping is not tested on big-endian hosts. */
36 wr_t wr
; /* vector data */
38 /* define FP_ENDIAN_IDX to access the same location
39 * in the fpr_t union regardless of the host endianness
41 #if defined(HOST_WORDS_BIGENDIAN)
42 # define FP_ENDIAN_IDX 1
44 # define FP_ENDIAN_IDX 0
47 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
48 struct CPUMIPSFPUContext
{
49 /* Floating point registers */
51 float_status fp_status
;
52 /* fpu implementation/revision register (fir) */
56 #define FCR0_HAS2008 23
67 uint32_t fcr31_rw_bitmask
;
70 #define FCR31_ABS2008 19
71 #define FCR31_NAN2008 18
72 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
73 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
74 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
75 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
76 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
77 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
78 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
79 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
80 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
81 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
83 #define FP_UNDERFLOW 2
87 #define FP_UNIMPLEMENTED 32
90 #define NB_MMU_MODES 4
91 #define TARGET_INSN_START_EXTRA_WORDS 2
93 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
94 struct CPUMIPSMVPContext
{
95 int32_t CP0_MVPControl
;
96 #define CP0MVPCo_CPA 3
97 #define CP0MVPCo_STLB 2
98 #define CP0MVPCo_VPC 1
99 #define CP0MVPCo_EVP 0
100 int32_t CP0_MVPConf0
;
101 #define CP0MVPC0_M 31
102 #define CP0MVPC0_TLBS 29
103 #define CP0MVPC0_GS 28
104 #define CP0MVPC0_PCP 27
105 #define CP0MVPC0_PTLBE 16
106 #define CP0MVPC0_TCA 15
107 #define CP0MVPC0_PVPE 10
108 #define CP0MVPC0_PTC 0
109 int32_t CP0_MVPConf1
;
110 #define CP0MVPC1_CIM 31
111 #define CP0MVPC1_CIF 30
112 #define CP0MVPC1_PCX 20
113 #define CP0MVPC1_PCP2 10
114 #define CP0MVPC1_PCP1 0
117 typedef struct mips_def_t mips_def_t
;
119 #define MIPS_SHADOW_SET_MAX 16
120 #define MIPS_TC_MAX 5
121 #define MIPS_FPU_MAX 1
122 #define MIPS_DSP_ACC 4
123 #define MIPS_KSCRATCH_NUM 6
124 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
126 typedef struct TCState TCState
;
128 target_ulong gpr
[32];
130 target_ulong HI
[MIPS_DSP_ACC
];
131 target_ulong LO
[MIPS_DSP_ACC
];
132 target_ulong ACX
[MIPS_DSP_ACC
];
133 target_ulong DSPControl
;
134 int32_t CP0_TCStatus
;
135 #define CP0TCSt_TCU3 31
136 #define CP0TCSt_TCU2 30
137 #define CP0TCSt_TCU1 29
138 #define CP0TCSt_TCU0 28
139 #define CP0TCSt_TMX 27
140 #define CP0TCSt_RNST 23
141 #define CP0TCSt_TDS 21
142 #define CP0TCSt_DT 20
143 #define CP0TCSt_DA 15
145 #define CP0TCSt_TKSU 11
146 #define CP0TCSt_IXMT 10
147 #define CP0TCSt_TASID 0
149 #define CP0TCBd_CurTC 21
150 #define CP0TCBd_TBE 17
151 #define CP0TCBd_CurVPE 0
152 target_ulong CP0_TCHalt
;
153 target_ulong CP0_TCContext
;
154 target_ulong CP0_TCSchedule
;
155 target_ulong CP0_TCScheFBack
;
156 int32_t CP0_Debug_tcstatus
;
157 target_ulong CP0_UserLocal
;
162 #define MSACSR_FS_MASK (1 << MSACSR_FS)
164 #define MSACSR_NX_MASK (1 << MSACSR_NX)
166 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
168 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
169 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
172 float_status msa_fp_status
;
175 typedef struct CPUMIPSState CPUMIPSState
;
176 struct CPUMIPSState
{
178 CPUMIPSFPUContext active_fpu
;
181 uint32_t current_fpu
;
185 #if defined(TARGET_MIPS64)
186 # define PABITS_BASE 36
188 # define PABITS_BASE 32
190 target_ulong SEGMask
;
192 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
195 #define MSAIR_ProcID 8
199 * Summary of CP0 registers
200 * ========================
203 * Register 0 Register 1 Register 2 Register 3
204 * ---------- ---------- ---------- ----------
206 * 0 Index Random EntryLo0 EntryLo1
207 * 1 MVPControl VPEControl TCStatus GlobalNumber
208 * 2 MVPConf0 VPEConf0 TCBind
209 * 3 MVPConf1 VPEConf1 TCRestart
210 * 4 VPControl YQMask TCHalt
211 * 5 VPESchedule TCContext
212 * 6 VPEScheFBack TCSchedule
213 * 7 VPEOpt TCScheFBack TCOpt
216 * Register 4 Register 5 Register 6 Register 7
217 * ---------- ---------- ---------- ----------
219 * 0 Context PageMask Wired HWREna
220 * 1 ContextConfig PageGrain SRSConf0
221 * 2 UserLocal SegCtl0 SRSConf1
222 * 3 XContextConfig SegCtl1 SRSConf2
223 * 4 DebugContextID SegCtl2 SRSConf3
224 * 5 MemoryMapID PWBase SRSConf4
229 * Register 8 Register 9 Register 10 Register 11
230 * ---------- ---------- ----------- -----------
232 * 0 BadVAddr Count EntryHi Compare
236 * 4 GuestCtl1 GuestCtl0Ext
242 * Register 12 Register 13 Register 14 Register 15
243 * ----------- ----------- ----------- -----------
245 * 0 Status Cause EPC PRId
247 * 2 SRSCtl NestedEPC CDMMBase
249 * 4 View_IPL View_RIPL BEVVA
250 * 5 SRSMap2 NestedExc
255 * Register 16 Register 17 Register 18 Register 19
256 * ----------- ----------- ----------- -----------
258 * 0 Config LLAddr WatchLo WatchHi
259 * 1 Config1 MAAR WatchLo WatchHi
260 * 2 Config2 MAARI WatchLo WatchHi
261 * 3 Config3 WatchLo WatchHi
262 * 4 Config4 WatchLo WatchHi
263 * 5 Config5 WatchLo WatchHi
268 * Register 20 Register 21 Register 22 Register 23
269 * ----------- ----------- ----------- -----------
281 * Register 24 Register 25 Register 26 Register 27
282 * ----------- ----------- ----------- -----------
284 * 0 DEPC PerfCnt ErrCtl CacheErr
286 * 2 TraceControl3 PerfCnt
287 * 3 UserTraceData2 PerfCnt
294 * Register 28 Register 29 Register 30 Register 31
295 * ----------- ----------- ----------- -----------
297 * 0 DataLo DataHi ErrorEPC DESAVE
299 * 2 DataLo DataHi KScratch<n>
300 * 3 TagLo TagHi KScratch<n>
301 * 4 DataLo DataHi KScratch<n>
302 * 5 TagLo TagHi KScratch<n>
303 * 6 DataLo DataHi KScratch<n>
304 * 7 TagLo TagHi KScratch<n>
311 /* CP0_MVP* are per MVP registers. */
312 int32_t CP0_VPControl
;
313 #define CP0VPCtl_DIS 0
318 int32_t CP0_VPEControl
;
319 #define CP0VPECo_YSI 21
320 #define CP0VPECo_GSI 20
321 #define CP0VPECo_EXCPT 16
322 #define CP0VPECo_TE 15
323 #define CP0VPECo_TargTC 0
324 int32_t CP0_VPEConf0
;
325 #define CP0VPEC0_M 31
326 #define CP0VPEC0_XTC 21
327 #define CP0VPEC0_TCS 19
328 #define CP0VPEC0_SCS 18
329 #define CP0VPEC0_DSC 17
330 #define CP0VPEC0_ICS 16
331 #define CP0VPEC0_MVP 1
332 #define CP0VPEC0_VPA 0
333 int32_t CP0_VPEConf1
;
334 #define CP0VPEC1_NCX 20
335 #define CP0VPEC1_NCP2 10
336 #define CP0VPEC1_NCP1 0
337 target_ulong CP0_YQMask
;
338 target_ulong CP0_VPESchedule
;
339 target_ulong CP0_VPEScheFBack
;
341 #define CP0VPEOpt_IWX7 15
342 #define CP0VPEOpt_IWX6 14
343 #define CP0VPEOpt_IWX5 13
344 #define CP0VPEOpt_IWX4 12
345 #define CP0VPEOpt_IWX3 11
346 #define CP0VPEOpt_IWX2 10
347 #define CP0VPEOpt_IWX1 9
348 #define CP0VPEOpt_IWX0 8
349 #define CP0VPEOpt_DWX7 7
350 #define CP0VPEOpt_DWX6 6
351 #define CP0VPEOpt_DWX5 5
352 #define CP0VPEOpt_DWX4 4
353 #define CP0VPEOpt_DWX3 3
354 #define CP0VPEOpt_DWX2 2
355 #define CP0VPEOpt_DWX1 1
356 #define CP0VPEOpt_DWX0 0
360 uint64_t CP0_EntryLo0
;
364 uint64_t CP0_EntryLo1
;
365 #if defined(TARGET_MIPS64)
366 # define CP0EnLo_RI 63
367 # define CP0EnLo_XI 62
369 # define CP0EnLo_RI 31
370 # define CP0EnLo_XI 30
372 int32_t CP0_GlobalNumber
;
377 target_ulong CP0_Context
;
378 target_ulong CP0_KScratch
[MIPS_KSCRATCH_NUM
];
382 int32_t CP0_PageMask
;
383 int32_t CP0_PageGrain_rw_bitmask
;
384 int32_t CP0_PageGrain
;
387 #define CP0PG_ELPA 29
389 target_ulong CP0_SegCtl0
;
390 target_ulong CP0_SegCtl1
;
391 target_ulong CP0_SegCtl2
;
393 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
394 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
396 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
397 #define CP0SC_AM_UK 0ULL
398 #define CP0SC_AM_MK 1ULL
399 #define CP0SC_AM_MSK 2ULL
400 #define CP0SC_AM_MUSK 3ULL
401 #define CP0SC_AM_MUSUK 4ULL
402 #define CP0SC_AM_USK 5ULL
403 #define CP0SC_AM_UUSK 7ULL
405 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
407 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
408 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
410 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
412 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
413 #define CP0SC1_XAM 59
414 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
415 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
417 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
418 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
419 target_ulong CP0_PWBase
;
420 target_ulong CP0_PWField
;
421 #if defined(TARGET_MIPS64)
422 #define CP0PF_BDI 32 /* 37..32 */
423 #define CP0PF_GDI 24 /* 29..24 */
424 #define CP0PF_UDI 18 /* 23..18 */
425 #define CP0PF_MDI 12 /* 17..12 */
426 #define CP0PF_PTI 6 /* 11..6 */
427 #define CP0PF_PTEI 0 /* 5..0 */
429 #define CP0PF_GDW 24 /* 29..24 */
430 #define CP0PF_UDW 18 /* 23..18 */
431 #define CP0PF_MDW 12 /* 17..12 */
432 #define CP0PF_PTW 6 /* 11..6 */
433 #define CP0PF_PTEW 0 /* 5..0 */
435 target_ulong CP0_PWSize
;
436 #if defined(TARGET_MIPS64)
437 #define CP0PS_BDW 32 /* 37..32 */
440 #define CP0PS_GDW 24 /* 29..24 */
441 #define CP0PS_UDW 18 /* 23..18 */
442 #define CP0PS_MDW 12 /* 17..12 */
443 #define CP0PS_PTW 6 /* 11..6 */
444 #define CP0PS_PTEW 0 /* 5..0 */
450 #define CP0PC_PWEN 31
451 #if defined(TARGET_MIPS64)
452 #define CP0PC_PWDIREXT 30
458 #define CP0PC_HUGEPG 6
459 #define CP0PC_PSN 0 /* 5..0 */
460 int32_t CP0_SRSConf0_rw_bitmask
;
461 int32_t CP0_SRSConf0
;
462 #define CP0SRSC0_M 31
463 #define CP0SRSC0_SRS3 20
464 #define CP0SRSC0_SRS2 10
465 #define CP0SRSC0_SRS1 0
466 int32_t CP0_SRSConf1_rw_bitmask
;
467 int32_t CP0_SRSConf1
;
468 #define CP0SRSC1_M 31
469 #define CP0SRSC1_SRS6 20
470 #define CP0SRSC1_SRS5 10
471 #define CP0SRSC1_SRS4 0
472 int32_t CP0_SRSConf2_rw_bitmask
;
473 int32_t CP0_SRSConf2
;
474 #define CP0SRSC2_M 31
475 #define CP0SRSC2_SRS9 20
476 #define CP0SRSC2_SRS8 10
477 #define CP0SRSC2_SRS7 0
478 int32_t CP0_SRSConf3_rw_bitmask
;
479 int32_t CP0_SRSConf3
;
480 #define CP0SRSC3_M 31
481 #define CP0SRSC3_SRS12 20
482 #define CP0SRSC3_SRS11 10
483 #define CP0SRSC3_SRS10 0
484 int32_t CP0_SRSConf4_rw_bitmask
;
485 int32_t CP0_SRSConf4
;
486 #define CP0SRSC4_SRS15 20
487 #define CP0SRSC4_SRS14 10
488 #define CP0SRSC4_SRS13 0
496 target_ulong CP0_BadVAddr
;
497 uint32_t CP0_BadInstr
;
498 uint32_t CP0_BadInstrP
;
499 uint32_t CP0_BadInstrX
;
507 target_ulong CP0_EntryHi
;
508 #define CP0EnHi_EHINV 10
509 target_ulong CP0_EntryHi_ASID_mask
;
540 #define CP0IntCtl_IPTI 29
541 #define CP0IntCtl_IPPCI 26
542 #define CP0IntCtl_VS 5
544 #define CP0SRSCtl_HSS 26
545 #define CP0SRSCtl_EICSS 18
546 #define CP0SRSCtl_ESS 12
547 #define CP0SRSCtl_PSS 6
548 #define CP0SRSCtl_CSS 0
550 #define CP0SRSMap_SSV7 28
551 #define CP0SRSMap_SSV6 24
552 #define CP0SRSMap_SSV5 20
553 #define CP0SRSMap_SSV4 16
554 #define CP0SRSMap_SSV3 12
555 #define CP0SRSMap_SSV2 8
556 #define CP0SRSMap_SSV1 4
557 #define CP0SRSMap_SSV0 0
570 #define CP0Ca_IP_mask 0x0000FF00
575 target_ulong CP0_EPC
;
580 target_ulong CP0_EBase
;
581 target_ulong CP0_EBaseWG_rw_bitmask
;
582 #define CP0EBase_WG 11
583 target_ulong CP0_CMGCRBase
;
589 #define CP0C0_K23 28 /* 30..28 */
590 #define CP0C0_KU 25 /* 27..25 */
594 #define CP0C0_Impl 16 /* 24..16 */
596 #define CP0C0_AT 13 /* 14..13 */
597 #define CP0C0_AR 10 /* 12..10 */
598 #define CP0C0_MT 7 /* 9..7 */
600 #define CP0C0_K0 0 /* 2..0 */
603 #define CP0C1_MMU 25 /* 30..25 */
604 #define CP0C1_IS 22 /* 24..22 */
605 #define CP0C1_IL 19 /* 21..19 */
606 #define CP0C1_IA 16 /* 18..16 */
607 #define CP0C1_DS 13 /* 15..13 */
608 #define CP0C1_DL 10 /* 12..10 */
609 #define CP0C1_DA 7 /* 9..7 */
619 #define CP0C2_TU 28 /* 30..28 */
620 #define CP0C2_TS 24 /* 27..24 */
621 #define CP0C2_TL 20 /* 23..20 */
622 #define CP0C2_TA 16 /* 19..16 */
623 #define CP0C2_SU 12 /* 15..12 */
624 #define CP0C2_SS 8 /* 11..8 */
625 #define CP0C2_SL 4 /* 7..4 */
626 #define CP0C2_SA 0 /* 3..0 */
630 #define CP0C3_CMGCR 29
631 #define CP0C3_MSAP 28
637 #define CP0C3_IPLV 21 /* 22..21 */
638 #define CP0C3_MMAR 18 /* 20..18 */
640 #define CP0C3_ISA_ON_EXC 16
641 #define CP0C3_ISA 14 /* 15..14 */
642 #define CP0C3_ULRI 13
644 #define CP0C3_DSP2P 11
645 #define CP0C3_DSPP 10
646 #define CP0C3_CTXTC 9
657 int32_t CP0_Config4_rw_bitmask
;
659 #define CP0C4_IE 29 /* 30..29 */
661 #define CP0C4_VTLBSizeExt 24 /* 27..24 */
662 #define CP0C4_KScrExist 16
663 #define CP0C4_MMUExtDef 14
664 #define CP0C4_FTLBPageSize 8 /* 12..8 */
665 /* bit layout if MMUExtDef=1 */
666 #define CP0C4_MMUSizeExt 0 /* 7..0 */
667 /* bit layout if MMUExtDef=2 */
668 #define CP0C4_FTLBWays 4 /* 7..4 */
669 #define CP0C4_FTLBSets 0 /* 3..0 */
671 int32_t CP0_Config5_rw_bitmask
;
676 #define CP0C5_MSAEn 27
677 #define CP0C5_PMJ 23 /* 25..23 */
682 #define CP0C5_CRCP 18
684 #define CP0C5_GI 15 /* 16..15 */
697 #define CP0C5_NFExists 0
700 uint64_t CP0_MAAR
[MIPS_MAAR_MAX
];
702 /* XXX: Maybe make LLAddr per-TC? */
708 target_ulong llnewval
;
710 uint32_t llnewval_wp
;
712 uint64_t CP0_LLAddr_rw_bitmask
;
713 int CP0_LLAddr_shift
;
717 target_ulong CP0_WatchLo
[8];
721 int32_t CP0_WatchHi
[8];
722 #define CP0WH_ASID 16
726 target_ulong CP0_XContext
;
727 int32_t CP0_Framemask
;
734 #define CP0DB_LSNM 28
735 #define CP0DB_Doze 27
736 #define CP0DB_Halt 26
738 #define CP0DB_IBEP 24
739 #define CP0DB_DBEP 21
740 #define CP0DB_IEXI 20
753 target_ulong CP0_DEPC
;
757 int32_t CP0_Performance0
;
778 target_ulong CP0_ErrorEPC
;
784 /* We waste some space so we can handle shadow registers like TCs. */
785 TCState tcs
[MIPS_SHADOW_SET_MAX
];
786 CPUMIPSFPUContext fpus
[MIPS_FPU_MAX
];
789 #define EXCP_TLB_NOMATCH 0x1
790 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
791 uint32_t hflags
; /* CPU State */
792 /* TMASK defines different execution modes */
793 #define MIPS_HFLAG_TMASK 0x1F5807FF
794 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
795 /* The KSU flags must be the lowest bits in hflags. The flag order
796 must be the same as defined for CP0 Status. This allows to use
797 the bits as the value of mmu_idx. */
798 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
799 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
800 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
801 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
802 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
803 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
804 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
805 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
806 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
807 /* True if the MIPS IV COP1X instructions can be used. This also
808 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
810 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
811 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
812 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
813 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
814 #define MIPS_HFLAG_M16_SHIFT 10
815 /* If translation is interrupted between the branch instruction and
816 * the delay slot, record what type of branch it is so that we can
817 * resume translation properly. It might be possible to reduce
818 * this from three bits to two. */
819 #define MIPS_HFLAG_BMASK_BASE 0x803800
820 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
821 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
822 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
823 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
824 /* Extra flags about the current pending branch. */
825 #define MIPS_HFLAG_BMASK_EXT 0x7C000
826 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
827 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
828 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
829 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
830 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
831 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
832 /* MIPS DSP resources access. */
833 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
834 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
835 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
836 /* Extra flag about HWREna register. */
837 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
838 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
839 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
840 #define MIPS_HFLAG_MSA 0x1000000
841 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
842 #define MIPS_HFLAG_ELPA 0x4000000
843 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
844 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
845 target_ulong btarget
; /* Jump / branch target */
846 target_ulong bcond
; /* Branch condition (if needed) */
848 int SYNCI_Step
; /* Address step size for SYNCI */
849 int CCRes
; /* Cycle count resolution/divisor */
850 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
851 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
852 uint64_t insn_flags
; /* Supported instruction set */
854 /* Fields up to this point are cleared by a CPU reset */
855 struct {} end_reset_fields
;
859 /* Fields from here on are preserved across CPU reset. */
860 CPUMIPSMVPContext
*mvp
;
861 #if !defined(CONFIG_USER_ONLY)
862 CPUMIPSTLBContext
*tlb
;
865 const mips_def_t
*cpu_model
;
867 QEMUTimer
*timer
; /* Internal timer */
868 MemoryRegion
*itc_tag
; /* ITC Configuration Tags */
869 target_ulong exception_base
; /* ExceptionBase input to the core */
874 * @env: #CPUMIPSState
886 static inline MIPSCPU
*mips_env_get_cpu(CPUMIPSState
*env
)
888 return container_of(env
, MIPSCPU
, env
);
891 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
893 #define ENV_OFFSET offsetof(MIPSCPU, env)
895 void mips_cpu_list (FILE *f
, fprintf_function cpu_fprintf
);
897 #define cpu_signal_handler cpu_mips_signal_handler
898 #define cpu_list mips_cpu_list
900 extern void cpu_wrdsp(uint32_t rs
, uint32_t mask_num
, CPUMIPSState
*env
);
901 extern uint32_t cpu_rddsp(uint32_t mask_num
, CPUMIPSState
*env
);
903 /* MMU modes definitions. We carefully match the indices with our
905 #define MMU_MODE0_SUFFIX _kernel
906 #define MMU_MODE1_SUFFIX _super
907 #define MMU_MODE2_SUFFIX _user
908 #define MMU_MODE3_SUFFIX _error
909 #define MMU_USER_IDX 2
911 static inline int hflags_mmu_index(uint32_t hflags
)
913 if (hflags
& MIPS_HFLAG_ERL
) {
916 return hflags
& MIPS_HFLAG_KSU
;
920 static inline int cpu_mmu_index (CPUMIPSState
*env
, bool ifetch
)
922 return hflags_mmu_index(env
->hflags
);
925 #include "exec/cpu-all.h"
927 /* Memory access type :
928 * may be needed for precise access rights control and precise exceptions.
931 /* 1 bit to define user level / supervisor access */
934 /* 1 bit to indicate direction */
936 /* Type of instruction that generated the access */
937 ACCESS_CODE
= 0x10, /* Code fetch access */
938 ACCESS_INT
= 0x20, /* Integer load/store access */
939 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
953 EXCP_EXT_INTERRUPT
, /* 8 */
969 EXCP_DWATCH
, /* 24 */
984 EXCP_LAST
= EXCP_TLBRI
,
986 /* Dummy exception for conditional stores. */
987 #define EXCP_SC 0x100
990 * This is an internally generated WAKE request line.
991 * It is driven by the CPU itself. Raised when the MT
992 * block wants to wake a VPE from an inactive state and
993 * cleared when VPE goes from active to inactive.
995 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
997 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
999 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1000 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1001 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1003 bool cpu_supports_cps_smp(const char *cpu_type
);
1004 bool cpu_supports_isa(const char *cpu_type
, unsigned int isa
);
1005 void cpu_set_exception_base(int vp_index
, target_ulong address
);
1008 void cpu_mips_soft_irq(CPUMIPSState
*env
, int irq
, int level
);
1011 target_ulong
exception_resume_pc (CPUMIPSState
*env
);
1013 static inline void restore_snan_bit_mode(CPUMIPSState
*env
)
1015 set_snan_bit_is_one((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) == 0,
1016 &env
->active_fpu
.fp_status
);
1019 static inline void cpu_get_tb_cpu_state(CPUMIPSState
*env
, target_ulong
*pc
,
1020 target_ulong
*cs_base
, uint32_t *flags
)
1022 *pc
= env
->active_tc
.PC
;
1024 *flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
|
1025 MIPS_HFLAG_HWRENA_ULR
);
1028 #endif /* MIPS_CPU_H */