hw/ppc/ppce500_spin.c

   1 /*
   2  * QEMU PowerPC e500v2 ePAPR spinning code
   3  *
   4  * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Alexander Graf, <agraf@suse.de>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  *
  21  * This code is not really a device, but models an interface that usually
  22  * firmware takes care of. It's used when QEMU plays the role of firmware.
  23  *
  24  * Specification:
  25  *
  26  * https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf
  27  *
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "qemu/module.h"
  32 #include "qemu/units.h"
  33 #include "hw/hw.h"
  34 #include "hw/sysbus.h"
  35 #include "sysemu/hw_accel.h"
  36 #include "e500.h"
  37 #include "qom/object.h"
  38
  39 #define MAX_CPUS 32
  40
  41 typedef struct spin_info {
  42     uint64_t addr;
  43     uint64_t r3;
  44     uint32_t resv;
  45     uint32_t pir;
  46     uint64_t reserved;
  47 } QEMU_PACKED SpinInfo;
  48
  49 #define TYPE_E500_SPIN "e500-spin"
  50 typedef struct SpinState SpinState;
  51 DECLARE_INSTANCE_CHECKER(SpinState, E500_SPIN,
  52                          TYPE_E500_SPIN)
  53
  54 struct SpinState {
  55     SysBusDevice parent_obj;
  56
  57     MemoryRegion iomem;
  58     SpinInfo spin[MAX_CPUS];
  59 };
  60
  61 static void spin_reset(DeviceState *dev)
  62 {
  63     SpinState *s = E500_SPIN(dev);
  64     int i;
  65
  66     for (i = 0; i < MAX_CPUS; i++) {
  67         SpinInfo *info = &s->spin[i];
  68
  69         stl_p(&info->pir, i);
  70         stq_p(&info->r3, i);
  71         stq_p(&info->addr, 1);
  72     }
  73 }
  74
  75 static void mmubooke_create_initial_mapping(CPUPPCState *env,
  76                                      target_ulong va,
  77                                      hwaddr pa,
  78                                      hwaddr len)
  79 {
  80     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
  81     hwaddr size;
  82
  83     size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
  84     tlb->mas1 = MAS1_VALID | size;
  85     tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
  86     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
  87     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
  88     env->tlb_dirty = true;
  89 }
  90
  91 static void spin_kick(CPUState *cs, run_on_cpu_data data)
  92 {
  93     PowerPCCPU *cpu = POWERPC_CPU(cs);
  94     CPUPPCState *env = &cpu->env;
  95     SpinInfo *curspin = data.host_ptr;
  96     hwaddr map_size = 64 * MiB;
  97     hwaddr map_start;
  98
  99     cpu_synchronize_state(cs);
 100     stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]);
 101     env->nip = ldq_p(&curspin->addr) & (map_size - 1);
 102     env->gpr[3] = ldq_p(&curspin->r3);
 103     env->gpr[4] = 0;
 104     env->gpr[5] = 0;
 105     env->gpr[6] = 0;
 106     env->gpr[7] = map_size;
 107     env->gpr[8] = 0;
 108     env->gpr[9] = 0;
 109
 110     map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
 111     mmubooke_create_initial_mapping(env, 0, map_start, map_size);
 112
 113     cs->halted = 0;
 114     cs->exception_index = -1;
 115     cs->stopped = false;
 116     qemu_cpu_kick(cs);
 117 }
 118
 119 static void spin_write(void *opaque, hwaddr addr, uint64_t value,
 120                        unsigned len)
 121 {
 122     SpinState *s = opaque;
 123     int env_idx = addr / sizeof(SpinInfo);
 124     CPUState *cpu;
 125     SpinInfo *curspin = &s->spin[env_idx];
 126     uint8_t *curspin_p = (uint8_t*)curspin;
 127
 128     cpu = qemu_get_cpu(env_idx);
 129     if (cpu == NULL) {
 130         /* Unknown CPU */
 131         return;
 132     }
 133
 134     if (cpu->cpu_index == 0) {
 135         /* primary CPU doesn't spin */
 136         return;
 137     }
 138
 139     curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
 140     switch (len) {
 141     case 1:
 142         stb_p(curspin_p, value);
 143         break;
 144     case 2:
 145         stw_p(curspin_p, value);
 146         break;
 147     case 4:
 148         stl_p(curspin_p, value);
 149         break;
 150     }
 151
 152     if (!(ldq_p(&curspin->addr) & 1)) {
 153         /* run CPU */
 154         run_on_cpu(cpu, spin_kick, RUN_ON_CPU_HOST_PTR(curspin));
 155     }
 156 }
 157
 158 static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)
 159 {
 160     SpinState *s = opaque;
 161     uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
 162
 163     switch (len) {
 164     case 1:
 165         return ldub_p(spin_p);
 166     case 2:
 167         return lduw_p(spin_p);
 168     case 4:
 169         return ldl_p(spin_p);
 170     default:
 171         hw_error("ppce500: unexpected %s with len = %u", __func__, len);
 172     }
 173 }
 174
 175 static const MemoryRegionOps spin_rw_ops = {
 176     .read = spin_read,
 177     .write = spin_write,
 178     .endianness = DEVICE_BIG_ENDIAN,
 179 };
 180
 181 static void ppce500_spin_initfn(Object *obj)
 182 {
 183     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 184     SpinState *s = E500_SPIN(dev);
 185
 186     memory_region_init_io(&s->iomem, obj, &spin_rw_ops, s,
 187                           "e500 spin pv device", sizeof(SpinInfo) * MAX_CPUS);
 188     sysbus_init_mmio(dev, &s->iomem);
 189 }
 190
 191 static void ppce500_spin_class_init(ObjectClass *klass, void *data)
 192 {
 193     DeviceClass *dc = DEVICE_CLASS(klass);
 194
 195     dc->reset = spin_reset;
 196 }
 197
 198 static const TypeInfo ppce500_spin_info = {
 199     .name          = TYPE_E500_SPIN,
 200     .parent        = TYPE_SYS_BUS_DEVICE,
 201     .instance_size = sizeof(SpinState),
 202     .instance_init = ppce500_spin_initfn,
 203     .class_init    = ppce500_spin_class_init,
 204 };
 205
 206 static void ppce500_spin_register_types(void)
 207 {
 208     type_register_static(&ppce500_spin_info);
 209 }
 210
 211 type_init(ppce500_spin_register_types)