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util: introduce qemu_open and qemu_create with error reporting
[qemu/ar7.git] / hw / net / rtl8139.c
blob9246388f58d9272a84a9f3bf2210ce2e08f59f00
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52
53 #include "qemu/osdep.h"
54 #include <zlib.h>
55
56 #include "hw/pci/pci.h"
57 #include "hw/qdev-properties.h"
58 #include "migration/vmstate.h"
59 #include "sysemu/dma.h"
60 #include "qemu/module.h"
61 #include "qemu/timer.h"
62 #include "net/net.h"
63 #include "net/eth.h"
64 #include "sysemu/sysemu.h"
65 #include "qom/object.h"
66
67 /* debug RTL8139 card */
68 //#define DEBUG_RTL8139 1
69
70 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
71
72 #define SET_MASKED(input, mask, curr) \
73 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
74
75 /* arg % size for size which is a power of 2 */
76 #define MOD2(input, size) \
77 ( ( input ) & ( size - 1 ) )
78
79 #define ETHER_TYPE_LEN 2
80 #define ETH_MTU 1500
81
82 #define VLAN_TCI_LEN 2
83 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
85 #if defined (DEBUG_RTL8139)
86 # define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
88 #else
89 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
90 {
91 return 0;
92 }
93 #endif
94
95 #define TYPE_RTL8139 "rtl8139"
96
97 typedef struct RTL8139State RTL8139State;
98 DECLARE_INSTANCE_CHECKER(RTL8139State, RTL8139,
99 TYPE_RTL8139)
100
101 /* Symbolic offsets to registers. */
102 enum RTL8139_registers {
103 MAC0 = 0, /* Ethernet hardware address. */
104 MAR0 = 8, /* Multicast filter. */
105 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
106 /* Dump Tally Conter control register(64bit). C+ mode only */
107 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
108 RxBuf = 0x30,
109 ChipCmd = 0x37,
110 RxBufPtr = 0x38,
111 RxBufAddr = 0x3A,
112 IntrMask = 0x3C,
113 IntrStatus = 0x3E,
114 TxConfig = 0x40,
115 RxConfig = 0x44,
116 Timer = 0x48, /* A general-purpose counter. */
117 RxMissed = 0x4C, /* 24 bits valid, write clears. */
118 Cfg9346 = 0x50,
119 Config0 = 0x51,
120 Config1 = 0x52,
121 FlashReg = 0x54,
122 MediaStatus = 0x58,
123 Config3 = 0x59,
124 Config4 = 0x5A, /* absent on RTL-8139A */
125 HltClk = 0x5B,
126 MultiIntr = 0x5C,
127 PCIRevisionID = 0x5E,
128 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
129 BasicModeCtrl = 0x62,
130 BasicModeStatus = 0x64,
131 NWayAdvert = 0x66,
132 NWayLPAR = 0x68,
133 NWayExpansion = 0x6A,
134 /* Undocumented registers, but required for proper operation. */
135 FIFOTMS = 0x70, /* FIFO Control and test. */
136 CSCR = 0x74, /* Chip Status and Configuration Register. */
137 PARA78 = 0x78,
138 PARA7c = 0x7c, /* Magic transceiver parameter register. */
139 Config5 = 0xD8, /* absent on RTL-8139A */
140 /* C+ mode */
141 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
142 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
143 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
144 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
145 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
146 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
147 TxThresh = 0xEC, /* Early Tx threshold */
148 };
149
150 enum ClearBitMasks {
151 MultiIntrClear = 0xF000,
152 ChipCmdClear = 0xE2,
153 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
154 };
155
156 enum ChipCmdBits {
157 CmdReset = 0x10,
158 CmdRxEnb = 0x08,
159 CmdTxEnb = 0x04,
160 RxBufEmpty = 0x01,
161 };
162
163 /* C+ mode */
164 enum CplusCmdBits {
165 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
166 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
167 CPlusRxEnb = 0x0002,
168 CPlusTxEnb = 0x0001,
169 };
170
171 /* Interrupt register bits, using my own meaningful names. */
172 enum IntrStatusBits {
173 PCIErr = 0x8000,
174 PCSTimeout = 0x4000,
175 RxFIFOOver = 0x40,
176 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
177 RxOverflow = 0x10,
178 TxErr = 0x08,
179 TxOK = 0x04,
180 RxErr = 0x02,
181 RxOK = 0x01,
182
183 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
184 };
185
186 enum TxStatusBits {
187 TxHostOwns = 0x2000,
188 TxUnderrun = 0x4000,
189 TxStatOK = 0x8000,
190 TxOutOfWindow = 0x20000000,
191 TxAborted = 0x40000000,
192 TxCarrierLost = 0x80000000,
193 };
194 enum RxStatusBits {
195 RxMulticast = 0x8000,
196 RxPhysical = 0x4000,
197 RxBroadcast = 0x2000,
198 RxBadSymbol = 0x0020,
199 RxRunt = 0x0010,
200 RxTooLong = 0x0008,
201 RxCRCErr = 0x0004,
202 RxBadAlign = 0x0002,
203 RxStatusOK = 0x0001,
204 };
205
206 /* Bits in RxConfig. */
207 enum rx_mode_bits {
208 AcceptErr = 0x20,
209 AcceptRunt = 0x10,
210 AcceptBroadcast = 0x08,
211 AcceptMulticast = 0x04,
212 AcceptMyPhys = 0x02,
213 AcceptAllPhys = 0x01,
214 };
215
216 /* Bits in TxConfig. */
217 enum tx_config_bits {
218
219 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
220 TxIFGShift = 24,
221 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
222 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
223 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
224 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
225
226 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
227 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
228 TxClearAbt = (1 << 0), /* Clear abort (WO) */
229 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
230 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
231
232 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
233 };
234
235
236 /* Transmit Status of All Descriptors (TSAD) Register */
237 enum TSAD_bits {
238 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
239 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
240 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
241 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
242 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
243 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
244 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
245 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
246 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
247 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
248 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
249 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
250 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
251 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
252 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
253 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
254 };
255
256
257 /* Bits in Config1 */
258 enum Config1Bits {
259 Cfg1_PM_Enable = 0x01,
260 Cfg1_VPD_Enable = 0x02,
261 Cfg1_PIO = 0x04,
262 Cfg1_MMIO = 0x08,
263 LWAKE = 0x10, /* not on 8139, 8139A */
264 Cfg1_Driver_Load = 0x20,
265 Cfg1_LED0 = 0x40,
266 Cfg1_LED1 = 0x80,
267 SLEEP = (1 << 1), /* only on 8139, 8139A */
268 PWRDN = (1 << 0), /* only on 8139, 8139A */
269 };
270
271 /* Bits in Config3 */
272 enum Config3Bits {
273 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
274 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
275 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
276 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
277 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
278 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
279 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
280 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
281 };
282
283 /* Bits in Config4 */
284 enum Config4Bits {
285 LWPTN = (1 << 2), /* not on 8139, 8139A */
286 };
287
288 /* Bits in Config5 */
289 enum Config5Bits {
290 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
291 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
292 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
293 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
294 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
295 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
296 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
297 };
298
299 enum RxConfigBits {
300 /* rx fifo threshold */
301 RxCfgFIFOShift = 13,
302 RxCfgFIFONone = (7 << RxCfgFIFOShift),
303
304 /* Max DMA burst */
305 RxCfgDMAShift = 8,
306 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
307
308 /* rx ring buffer length */
309 RxCfgRcv8K = 0,
310 RxCfgRcv16K = (1 << 11),
311 RxCfgRcv32K = (1 << 12),
312 RxCfgRcv64K = (1 << 11) | (1 << 12),
313
314 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
315 RxNoWrap = (1 << 7),
316 };
317
318 /* Twister tuning parameters from RealTek.
319 Completely undocumented, but required to tune bad links on some boards. */
320 /*
321 enum CSCRBits {
322 CSCR_LinkOKBit = 0x0400,
323 CSCR_LinkChangeBit = 0x0800,
324 CSCR_LinkStatusBits = 0x0f000,
325 CSCR_LinkDownOffCmd = 0x003c0,
326 CSCR_LinkDownCmd = 0x0f3c0,
327 */
328 enum CSCRBits {
329 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
330 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
331 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
332 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
333 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
334 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
335 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
336 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
337 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
338 };
339
340 enum Cfg9346Bits {
341 Cfg9346_Normal = 0x00,
342 Cfg9346_Autoload = 0x40,
343 Cfg9346_Programming = 0x80,
344 Cfg9346_ConfigWrite = 0xC0,
345 };
346
347 typedef enum {
348 CH_8139 = 0,
349 CH_8139_K,
350 CH_8139A,
351 CH_8139A_G,
352 CH_8139B,
353 CH_8130,
354 CH_8139C,
355 CH_8100,
356 CH_8100B_8139D,
357 CH_8101,
358 } chip_t;
359
360 enum chip_flags {
361 HasHltClk = (1 << 0),
362 HasLWake = (1 << 1),
363 };
364
365 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
366 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
367 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
368
369 #define RTL8139_PCI_REVID_8139 0x10
370 #define RTL8139_PCI_REVID_8139CPLUS 0x20
371
372 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
373
374 /* Size is 64 * 16bit words */
375 #define EEPROM_9346_ADDR_BITS 6
376 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
377 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
378
379 enum Chip9346Operation
380 {
381 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
382 Chip9346_op_read = 0x80, /* 10 AAAAAA */
383 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
384 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
385 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
386 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
387 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
388 };
389
390 enum Chip9346Mode
391 {
392 Chip9346_none = 0,
393 Chip9346_enter_command_mode,
394 Chip9346_read_command,
395 Chip9346_data_read, /* from output register */
396 Chip9346_data_write, /* to input register, then to contents at specified address */
397 Chip9346_data_write_all, /* to input register, then filling contents */
398 };
399
400 typedef struct EEprom9346
401 {
402 uint16_t contents[EEPROM_9346_SIZE];
403 int mode;
404 uint32_t tick;
405 uint8_t address;
406 uint16_t input;
407 uint16_t output;
408
409 uint8_t eecs;
410 uint8_t eesk;
411 uint8_t eedi;
412 uint8_t eedo;
413 } EEprom9346;
414
415 typedef struct RTL8139TallyCounters
416 {
417 /* Tally counters */
418 uint64_t TxOk;
419 uint64_t RxOk;
420 uint64_t TxERR;
421 uint32_t RxERR;
422 uint16_t MissPkt;
423 uint16_t FAE;
424 uint32_t Tx1Col;
425 uint32_t TxMCol;
426 uint64_t RxOkPhy;
427 uint64_t RxOkBrd;
428 uint32_t RxOkMul;
429 uint16_t TxAbt;
430 uint16_t TxUndrn;
431 } RTL8139TallyCounters;
432
433 /* Clears all tally counters */
434 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
435
436 struct RTL8139State {
437 /*< private >*/
438 PCIDevice parent_obj;
439 /*< public >*/
440
441 uint8_t phys[8]; /* mac address */
442 uint8_t mult[8]; /* multicast mask array */
443
444 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
445 uint32_t TxAddr[4]; /* TxAddr0 */
446 uint32_t RxBuf; /* Receive buffer */
447 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
448 uint32_t RxBufPtr;
449 uint32_t RxBufAddr;
450
451 uint16_t IntrStatus;
452 uint16_t IntrMask;
453
454 uint32_t TxConfig;
455 uint32_t RxConfig;
456 uint32_t RxMissed;
457
458 uint16_t CSCR;
459
460 uint8_t Cfg9346;
461 uint8_t Config0;
462 uint8_t Config1;
463 uint8_t Config3;
464 uint8_t Config4;
465 uint8_t Config5;
466
467 uint8_t clock_enabled;
468 uint8_t bChipCmdState;
469
470 uint16_t MultiIntr;
471
472 uint16_t BasicModeCtrl;
473 uint16_t BasicModeStatus;
474 uint16_t NWayAdvert;
475 uint16_t NWayLPAR;
476 uint16_t NWayExpansion;
477
478 uint16_t CpCmd;
479 uint8_t TxThresh;
480
481 NICState *nic;
482 NICConf conf;
483
484 /* C ring mode */
485 uint32_t currTxDesc;
486
487 /* C+ mode */
488 uint32_t cplus_enabled;
489
490 uint32_t currCPlusRxDesc;
491 uint32_t currCPlusTxDesc;
492
493 uint32_t RxRingAddrLO;
494 uint32_t RxRingAddrHI;
495
496 EEprom9346 eeprom;
497
498 uint32_t TCTR;
499 uint32_t TimerInt;
500 int64_t TCTR_base;
501
502 /* Tally counters */
503 RTL8139TallyCounters tally_counters;
504
505 /* Non-persistent data */
506 uint8_t *cplus_txbuffer;
507 int cplus_txbuffer_len;
508 int cplus_txbuffer_offset;
509
510 /* PCI interrupt timer */
511 QEMUTimer *timer;
512
513 MemoryRegion bar_io;
514 MemoryRegion bar_mem;
515
516 /* Support migration to/from old versions */
517 int rtl8139_mmio_io_addr_dummy;
518 };
519
520 /* Writes tally counters to memory via DMA */
521 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
522
523 static void rtl8139_set_next_tctr_time(RTL8139State *s);
524
525 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
526 {
527 DPRINTF("eeprom command 0x%02x\n", command);
528
529 switch (command & Chip9346_op_mask)
530 {
531 case Chip9346_op_read:
532 {
533 eeprom->address = command & EEPROM_9346_ADDR_MASK;
534 eeprom->output = eeprom->contents[eeprom->address];
535 eeprom->eedo = 0;
536 eeprom->tick = 0;
537 eeprom->mode = Chip9346_data_read;
538 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
539 eeprom->address, eeprom->output);
540 }
541 break;
542
543 case Chip9346_op_write:
544 {
545 eeprom->address = command & EEPROM_9346_ADDR_MASK;
546 eeprom->input = 0;
547 eeprom->tick = 0;
548 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
549 DPRINTF("eeprom begin write to address 0x%02x\n",
550 eeprom->address);
551 }
552 break;
553 default:
554 eeprom->mode = Chip9346_none;
555 switch (command & Chip9346_op_ext_mask)
556 {
557 case Chip9346_op_write_enable:
558 DPRINTF("eeprom write enabled\n");
559 break;
560 case Chip9346_op_write_all:
561 DPRINTF("eeprom begin write all\n");
562 break;
563 case Chip9346_op_write_disable:
564 DPRINTF("eeprom write disabled\n");
565 break;
566 }
567 break;
568 }
569 }
570
571 static void prom9346_shift_clock(EEprom9346 *eeprom)
572 {
573 int bit = eeprom->eedi?1:0;
574
575 ++ eeprom->tick;
576
577 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
578 eeprom->eedo);
579
580 switch (eeprom->mode)
581 {
582 case Chip9346_enter_command_mode:
583 if (bit)
584 {
585 eeprom->mode = Chip9346_read_command;
586 eeprom->tick = 0;
587 eeprom->input = 0;
588 DPRINTF("eeprom: +++ synchronized, begin command read\n");
589 }
590 break;
591
592 case Chip9346_read_command:
593 eeprom->input = (eeprom->input << 1) | (bit & 1);
594 if (eeprom->tick == 8)
595 {
596 prom9346_decode_command(eeprom, eeprom->input & 0xff);
597 }
598 break;
599
600 case Chip9346_data_read:
601 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
602 eeprom->output <<= 1;
603 if (eeprom->tick == 16)
604 {
605 #if 1
606 // the FreeBSD drivers (rl and re) don't explicitly toggle
607 // CS between reads (or does setting Cfg9346 to 0 count too?),
608 // so we need to enter wait-for-command state here
609 eeprom->mode = Chip9346_enter_command_mode;
610 eeprom->input = 0;
611 eeprom->tick = 0;
612
613 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
614 #else
615 // original behaviour
616 ++eeprom->address;
617 eeprom->address &= EEPROM_9346_ADDR_MASK;
618 eeprom->output = eeprom->contents[eeprom->address];
619 eeprom->tick = 0;
620
621 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->output);
623 #endif
624 }
625 break;
626
627 case Chip9346_data_write:
628 eeprom->input = (eeprom->input << 1) | (bit & 1);
629 if (eeprom->tick == 16)
630 {
631 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
632 eeprom->address, eeprom->input);
633
634 eeprom->contents[eeprom->address] = eeprom->input;
635 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
636 eeprom->tick = 0;
637 eeprom->input = 0;
638 }
639 break;
640
641 case Chip9346_data_write_all:
642 eeprom->input = (eeprom->input << 1) | (bit & 1);
643 if (eeprom->tick == 16)
644 {
645 int i;
646 for (i = 0; i < EEPROM_9346_SIZE; i++)
647 {
648 eeprom->contents[i] = eeprom->input;
649 }
650 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
651
652 eeprom->mode = Chip9346_enter_command_mode;
653 eeprom->tick = 0;
654 eeprom->input = 0;
655 }
656 break;
657
658 default:
659 break;
660 }
661 }
662
663 static int prom9346_get_wire(RTL8139State *s)
664 {
665 EEprom9346 *eeprom = &s->eeprom;
666 if (!eeprom->eecs)
667 return 0;
668
669 return eeprom->eedo;
670 }
671
672 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
673 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
674 {
675 EEprom9346 *eeprom = &s->eeprom;
676 uint8_t old_eecs = eeprom->eecs;
677 uint8_t old_eesk = eeprom->eesk;
678
679 eeprom->eecs = eecs;
680 eeprom->eesk = eesk;
681 eeprom->eedi = eedi;
682
683 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
684 eeprom->eesk, eeprom->eedi, eeprom->eedo);
685
686 if (!old_eecs && eecs)
687 {
688 /* Synchronize start */
689 eeprom->tick = 0;
690 eeprom->input = 0;
691 eeprom->output = 0;
692 eeprom->mode = Chip9346_enter_command_mode;
693
694 DPRINTF("=== eeprom: begin access, enter command mode\n");
695 }
696
697 if (!eecs)
698 {
699 DPRINTF("=== eeprom: end access\n");
700 return;
701 }
702
703 if (!old_eesk && eesk)
704 {
705 /* SK front rules */
706 prom9346_shift_clock(eeprom);
707 }
708 }
709
710 static void rtl8139_update_irq(RTL8139State *s)
711 {
712 PCIDevice *d = PCI_DEVICE(s);
713 int isr;
714 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
715
716 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
717 s->IntrMask);
718
719 pci_set_irq(d, (isr != 0));
720 }
721
722 static int rtl8139_RxWrap(RTL8139State *s)
723 {
724 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725 return (s->RxConfig & (1 << 7));
726 }
727
728 static int rtl8139_receiver_enabled(RTL8139State *s)
729 {
730 return s->bChipCmdState & CmdRxEnb;
731 }
732
733 static int rtl8139_transmitter_enabled(RTL8139State *s)
734 {
735 return s->bChipCmdState & CmdTxEnb;
736 }
737
738 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739 {
740 return s->CpCmd & CPlusRxEnb;
741 }
742
743 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744 {
745 return s->CpCmd & CPlusTxEnb;
746 }
747
748 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749 {
750 PCIDevice *d = PCI_DEVICE(s);
751
752 if (s->RxBufAddr + size > s->RxBufferSize)
753 {
754 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
755
756 /* write packet data */
757 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
758 {
759 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
760
761 if (size > wrapped)
762 {
763 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
764 buf, size-wrapped);
765 }
766
767 /* reset buffer pointer */
768 s->RxBufAddr = 0;
769
770 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
771 buf + (size-wrapped), wrapped);
772
773 s->RxBufAddr = wrapped;
774
775 return;
776 }
777 }
778
779 /* non-wrapping path or overwrapping enabled */
780 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
781
782 s->RxBufAddr += size;
783 }
784
785 #define MIN_BUF_SIZE 60
786 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
787 {
788 return low | ((uint64_t)high << 32);
789 }
790
791 /* Workaround for buggy guest driver such as linux who allocates rx
792 * rings after the receiver were enabled. */
793 static bool rtl8139_cp_rx_valid(RTL8139State *s)
794 {
795 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
796 }
797
798 static bool rtl8139_can_receive(NetClientState *nc)
799 {
800 RTL8139State *s = qemu_get_nic_opaque(nc);
801 int avail;
802
803 /* Receive (drop) packets if card is disabled. */
804 if (!s->clock_enabled) {
805 return true;
806 }
807 if (!rtl8139_receiver_enabled(s)) {
808 return true;
809 }
810
811 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
812 /* ??? Flow control not implemented in c+ mode.
813 This is a hack to work around slirp deficiencies anyway. */
814 return true;
815 }
816
817 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
818 s->RxBufferSize);
819 return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow);
820 }
821
822 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
823 {
824 RTL8139State *s = qemu_get_nic_opaque(nc);
825 PCIDevice *d = PCI_DEVICE(s);
826 /* size is the length of the buffer passed to the driver */
827 size_t size = size_;
828 const uint8_t *dot1q_buf = NULL;
829
830 uint32_t packet_header = 0;
831
832 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
833 static const uint8_t broadcast_macaddr[6] =
834 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
835
836 DPRINTF(">>> received len=%zu\n", size);
837
838 /* test if board clock is stopped */
839 if (!s->clock_enabled)
840 {
841 DPRINTF("stopped ==========================\n");
842 return -1;
843 }
844
845 /* first check if receiver is enabled */
846
847 if (!rtl8139_receiver_enabled(s))
848 {
849 DPRINTF("receiver disabled ================\n");
850 return -1;
851 }
852
853 /* XXX: check this */
854 if (s->RxConfig & AcceptAllPhys) {
855 /* promiscuous: receive all */
856 DPRINTF(">>> packet received in promiscuous mode\n");
857
858 } else {
859 if (!memcmp(buf, broadcast_macaddr, 6)) {
860 /* broadcast address */
861 if (!(s->RxConfig & AcceptBroadcast))
862 {
863 DPRINTF(">>> broadcast packet rejected\n");
864
865 /* update tally counter */
866 ++s->tally_counters.RxERR;
867
868 return size;
869 }
870
871 packet_header |= RxBroadcast;
872
873 DPRINTF(">>> broadcast packet received\n");
874
875 /* update tally counter */
876 ++s->tally_counters.RxOkBrd;
877
878 } else if (buf[0] & 0x01) {
879 /* multicast */
880 if (!(s->RxConfig & AcceptMulticast))
881 {
882 DPRINTF(">>> multicast packet rejected\n");
883
884 /* update tally counter */
885 ++s->tally_counters.RxERR;
886
887 return size;
888 }
889
890 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
891
892 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
893 {
894 DPRINTF(">>> multicast address mismatch\n");
895
896 /* update tally counter */
897 ++s->tally_counters.RxERR;
898
899 return size;
900 }
901
902 packet_header |= RxMulticast;
903
904 DPRINTF(">>> multicast packet received\n");
905
906 /* update tally counter */
907 ++s->tally_counters.RxOkMul;
908
909 } else if (s->phys[0] == buf[0] &&
910 s->phys[1] == buf[1] &&
911 s->phys[2] == buf[2] &&
912 s->phys[3] == buf[3] &&
913 s->phys[4] == buf[4] &&
914 s->phys[5] == buf[5]) {
915 /* match */
916 if (!(s->RxConfig & AcceptMyPhys))
917 {
918 DPRINTF(">>> rejecting physical address matching packet\n");
919
920 /* update tally counter */
921 ++s->tally_counters.RxERR;
922
923 return size;
924 }
925
926 packet_header |= RxPhysical;
927
928 DPRINTF(">>> physical address matching packet received\n");
929
930 /* update tally counter */
931 ++s->tally_counters.RxOkPhy;
932
933 } else {
934
935 DPRINTF(">>> unknown packet\n");
936
937 /* update tally counter */
938 ++s->tally_counters.RxERR;
939
940 return size;
941 }
942 }
943
944 /* if too small buffer, then expand it
945 * Include some tailroom in case a vlan tag is later removed. */
946 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
947 memcpy(buf1, buf, size);
948 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
949 buf = buf1;
950 if (size < MIN_BUF_SIZE) {
951 size = MIN_BUF_SIZE;
952 }
953 }
954
955 if (rtl8139_cp_receiver_enabled(s))
956 {
957 if (!rtl8139_cp_rx_valid(s)) {
958 return size;
959 }
960
961 DPRINTF("in C+ Rx mode ================\n");
962
963 /* begin C+ receiver mode */
964
965 /* w0 ownership flag */
966 #define CP_RX_OWN (1<<31)
967 /* w0 end of ring flag */
968 #define CP_RX_EOR (1<<30)
969 /* w0 bits 0...12 : buffer size */
970 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
971 /* w1 tag available flag */
972 #define CP_RX_TAVA (1<<16)
973 /* w1 bits 0...15 : VLAN tag */
974 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
975 /* w2 low 32bit of Rx buffer ptr */
976 /* w3 high 32bit of Rx buffer ptr */
977
978 int descriptor = s->currCPlusRxDesc;
979 dma_addr_t cplus_rx_ring_desc;
980
981 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
982 cplus_rx_ring_desc += 16 * descriptor;
983
984 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
985 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
986 s->RxRingAddrLO, cplus_rx_ring_desc);
987
988 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
989
990 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
991 rxdw0 = le32_to_cpu(val);
992 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
993 rxdw1 = le32_to_cpu(val);
994 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
995 rxbufLO = le32_to_cpu(val);
996 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
997 rxbufHI = le32_to_cpu(val);
998
999 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1000 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
1001
1002 if (!(rxdw0 & CP_RX_OWN))
1003 {
1004 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1005 descriptor);
1006
1007 s->IntrStatus |= RxOverflow;
1008 ++s->RxMissed;
1009
1010 /* update tally counter */
1011 ++s->tally_counters.RxERR;
1012 ++s->tally_counters.MissPkt;
1013
1014 rtl8139_update_irq(s);
1015 return size_;
1016 }
1017
1018 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1019
1020 /* write VLAN info to descriptor variables. */
1021 if (s->CpCmd & CPlusRxVLAN &&
1022 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) {
1023 dot1q_buf = &buf[ETH_ALEN * 2];
1024 size -= VLAN_HLEN;
1025 /* if too small buffer, use the tailroom added duing expansion */
1026 if (size < MIN_BUF_SIZE) {
1027 size = MIN_BUF_SIZE;
1028 }
1029
1030 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1031 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1032 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]);
1033
1034 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1035 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN]));
1036 } else {
1037 /* reset VLAN tag flag */
1038 rxdw1 &= ~CP_RX_TAVA;
1039 }
1040
1041 /* TODO: scatter the packet over available receive ring descriptors space */
1042
1043 if (size+4 > rx_space)
1044 {
1045 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n",
1046 descriptor, rx_space, size);
1047
1048 s->IntrStatus |= RxOverflow;
1049 ++s->RxMissed;
1050
1051 /* update tally counter */
1052 ++s->tally_counters.RxERR;
1053 ++s->tally_counters.MissPkt;
1054
1055 rtl8139_update_irq(s);
1056 return size_;
1057 }
1058
1059 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1060
1061 /* receive/copy to target memory */
1062 if (dot1q_buf) {
1063 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN);
1064 pci_dma_write(d, rx_addr + 2 * ETH_ALEN,
1065 buf + 2 * ETH_ALEN + VLAN_HLEN,
1066 size - 2 * ETH_ALEN);
1067 } else {
1068 pci_dma_write(d, rx_addr, buf, size);
1069 }
1070
1071 if (s->CpCmd & CPlusRxChkSum)
1072 {
1073 /* do some packet checksumming */
1074 }
1075
1076 /* write checksum */
1077 val = cpu_to_le32(crc32(0, buf, size_));
1078 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
1079
1080 /* first segment of received packet flag */
1081 #define CP_RX_STATUS_FS (1<<29)
1082 /* last segment of received packet flag */
1083 #define CP_RX_STATUS_LS (1<<28)
1084 /* multicast packet flag */
1085 #define CP_RX_STATUS_MAR (1<<26)
1086 /* physical-matching packet flag */
1087 #define CP_RX_STATUS_PAM (1<<25)
1088 /* broadcast packet flag */
1089 #define CP_RX_STATUS_BAR (1<<24)
1090 /* runt packet flag */
1091 #define CP_RX_STATUS_RUNT (1<<19)
1092 /* crc error flag */
1093 #define CP_RX_STATUS_CRC (1<<18)
1094 /* IP checksum error flag */
1095 #define CP_RX_STATUS_IPF (1<<15)
1096 /* UDP checksum error flag */
1097 #define CP_RX_STATUS_UDPF (1<<14)
1098 /* TCP checksum error flag */
1099 #define CP_RX_STATUS_TCPF (1<<13)
1100
1101 /* transfer ownership to target */
1102 rxdw0 &= ~CP_RX_OWN;
1103
1104 /* set first segment bit */
1105 rxdw0 |= CP_RX_STATUS_FS;
1106
1107 /* set last segment bit */
1108 rxdw0 |= CP_RX_STATUS_LS;
1109
1110 /* set received packet type flags */
1111 if (packet_header & RxBroadcast)
1112 rxdw0 |= CP_RX_STATUS_BAR;
1113 if (packet_header & RxMulticast)
1114 rxdw0 |= CP_RX_STATUS_MAR;
1115 if (packet_header & RxPhysical)
1116 rxdw0 |= CP_RX_STATUS_PAM;
1117
1118 /* set received size */
1119 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1120 rxdw0 |= (size+4);
1121
1122 /* update ring data */
1123 val = cpu_to_le32(rxdw0);
1124 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1125 val = cpu_to_le32(rxdw1);
1126 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1127
1128 /* update tally counter */
1129 ++s->tally_counters.RxOk;
1130
1131 /* seek to next Rx descriptor */
1132 if (rxdw0 & CP_RX_EOR)
1133 {
1134 s->currCPlusRxDesc = 0;
1135 }
1136 else
1137 {
1138 ++s->currCPlusRxDesc;
1139 }
1140
1141 DPRINTF("done C+ Rx mode ----------------\n");
1142
1143 }
1144 else
1145 {
1146 DPRINTF("in ring Rx mode ================\n");
1147
1148 /* begin ring receiver mode */
1149 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1150
1151 /* if receiver buffer is empty then avail == 0 */
1152
1153 #define RX_ALIGN(x) (((x) + 3) & ~0x3)
1154
1155 if (avail != 0 && RX_ALIGN(size + 8) >= avail)
1156 {
1157 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1158 "read 0x%04x === available 0x%04x need 0x%04zx\n",
1159 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1160
1161 s->IntrStatus |= RxOverflow;
1162 ++s->RxMissed;
1163 rtl8139_update_irq(s);
1164 return 0;
1165 }
1166
1167 packet_header |= RxStatusOK;
1168
1169 packet_header |= (((size+4) << 16) & 0xffff0000);
1170
1171 /* write header */
1172 uint32_t val = cpu_to_le32(packet_header);
1173
1174 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1175
1176 rtl8139_write_buffer(s, buf, size);
1177
1178 /* write checksum */
1179 val = cpu_to_le32(crc32(0, buf, size));
1180 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1181
1182 /* correct buffer write pointer */
1183 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
1184
1185 /* now we can signal we have received something */
1186
1187 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1188 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1189 }
1190
1191 s->IntrStatus |= RxOK;
1192
1193 if (do_interrupt)
1194 {
1195 rtl8139_update_irq(s);
1196 }
1197
1198 return size_;
1199 }
1200
1201 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1202 {
1203 return rtl8139_do_receive(nc, buf, size, 1);
1204 }
1205
1206 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1207 {
1208 s->RxBufferSize = bufferSize;
1209 s->RxBufPtr = 0;
1210 s->RxBufAddr = 0;
1211 }
1212
1213 static void rtl8139_reset_phy(RTL8139State *s)
1214 {
1215 s->BasicModeStatus = 0x7809;
1216 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1217 /* preserve link state */
1218 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1219
1220 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1221 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1222 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1223
1224 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1225 }
1226
1227 static void rtl8139_reset(DeviceState *d)
1228 {
1229 RTL8139State *s = RTL8139(d);
1230 int i;
1231
1232 /* restore MAC address */
1233 memcpy(s->phys, s->conf.macaddr.a, 6);
1234 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
1235
1236 /* reset interrupt mask */
1237 s->IntrStatus = 0;
1238 s->IntrMask = 0;
1239
1240 rtl8139_update_irq(s);
1241
1242 /* mark all status registers as owned by host */
1243 for (i = 0; i < 4; ++i)
1244 {
1245 s->TxStatus[i] = TxHostOwns;
1246 }
1247
1248 s->currTxDesc = 0;
1249 s->currCPlusRxDesc = 0;
1250 s->currCPlusTxDesc = 0;
1251
1252 s->RxRingAddrLO = 0;
1253 s->RxRingAddrHI = 0;
1254
1255 s->RxBuf = 0;
1256
1257 rtl8139_reset_rxring(s, 8192);
1258
1259 /* ACK the reset */
1260 s->TxConfig = 0;
1261
1262 #if 0
1263 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1264 s->clock_enabled = 0;
1265 #else
1266 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1267 s->clock_enabled = 1;
1268 #endif
1269
1270 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1271
1272 /* set initial state data */
1273 s->Config0 = 0x0; /* No boot ROM */
1274 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1275 s->Config3 = 0x1; /* fast back-to-back compatible */
1276 s->Config5 = 0x0;
1277
1278 s->CpCmd = 0x0; /* reset C+ mode */
1279 s->cplus_enabled = 0;
1280
1281 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1282 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1283 s->BasicModeCtrl = 0x1000; // autonegotiation
1284
1285 rtl8139_reset_phy(s);
1286
1287 /* also reset timer and disable timer interrupt */
1288 s->TCTR = 0;
1289 s->TimerInt = 0;
1290 s->TCTR_base = 0;
1291 rtl8139_set_next_tctr_time(s);
1292
1293 /* reset tally counters */
1294 RTL8139TallyCounters_clear(&s->tally_counters);
1295 }
1296
1297 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1298 {
1299 counters->TxOk = 0;
1300 counters->RxOk = 0;
1301 counters->TxERR = 0;
1302 counters->RxERR = 0;
1303 counters->MissPkt = 0;
1304 counters->FAE = 0;
1305 counters->Tx1Col = 0;
1306 counters->TxMCol = 0;
1307 counters->RxOkPhy = 0;
1308 counters->RxOkBrd = 0;
1309 counters->RxOkMul = 0;
1310 counters->TxAbt = 0;
1311 counters->TxUndrn = 0;
1312 }
1313
1314 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1315 {
1316 PCIDevice *d = PCI_DEVICE(s);
1317 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1318 uint16_t val16;
1319 uint32_t val32;
1320 uint64_t val64;
1321
1322 val64 = cpu_to_le64(tally_counters->TxOk);
1323 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1324
1325 val64 = cpu_to_le64(tally_counters->RxOk);
1326 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1327
1328 val64 = cpu_to_le64(tally_counters->TxERR);
1329 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1330
1331 val32 = cpu_to_le32(tally_counters->RxERR);
1332 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1333
1334 val16 = cpu_to_le16(tally_counters->MissPkt);
1335 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1336
1337 val16 = cpu_to_le16(tally_counters->FAE);
1338 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1339
1340 val32 = cpu_to_le32(tally_counters->Tx1Col);
1341 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1342
1343 val32 = cpu_to_le32(tally_counters->TxMCol);
1344 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1345
1346 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1347 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1348
1349 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1350 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1351
1352 val32 = cpu_to_le32(tally_counters->RxOkMul);
1353 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1354
1355 val16 = cpu_to_le16(tally_counters->TxAbt);
1356 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1357
1358 val16 = cpu_to_le16(tally_counters->TxUndrn);
1359 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1360 }
1361
1362 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1363 {
1364 DeviceState *d = DEVICE(s);
1365
1366 val &= 0xff;
1367
1368 DPRINTF("ChipCmd write val=0x%08x\n", val);
1369
1370 if (val & CmdReset)
1371 {
1372 DPRINTF("ChipCmd reset\n");
1373 rtl8139_reset(d);
1374 }
1375 if (val & CmdRxEnb)
1376 {
1377 DPRINTF("ChipCmd enable receiver\n");
1378
1379 s->currCPlusRxDesc = 0;
1380 }
1381 if (val & CmdTxEnb)
1382 {
1383 DPRINTF("ChipCmd enable transmitter\n");
1384
1385 s->currCPlusTxDesc = 0;
1386 }
1387
1388 /* mask unwritable bits */
1389 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1390
1391 /* Deassert reset pin before next read */
1392 val &= ~CmdReset;
1393
1394 s->bChipCmdState = val;
1395 }
1396
1397 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1398 {
1399 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1400
1401 if (unread != 0)
1402 {
1403 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1404 return 0;
1405 }
1406
1407 DPRINTF("receiver buffer is empty\n");
1408
1409 return 1;
1410 }
1411
1412 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1413 {
1414 uint32_t ret = s->bChipCmdState;
1415
1416 if (rtl8139_RxBufferEmpty(s))
1417 ret |= RxBufEmpty;
1418
1419 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1420
1421 return ret;
1422 }
1423
1424 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1425 {
1426 val &= 0xffff;
1427
1428 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1429
1430 s->cplus_enabled = 1;
1431
1432 /* mask unwritable bits */
1433 val = SET_MASKED(val, 0xff84, s->CpCmd);
1434
1435 s->CpCmd = val;
1436 }
1437
1438 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1439 {
1440 uint32_t ret = s->CpCmd;
1441
1442 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1443
1444 return ret;
1445 }
1446
1447 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1448 {
1449 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1450 }
1451
1452 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1453 {
1454 uint32_t ret = 0;
1455
1456 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1457
1458 return ret;
1459 }
1460
1461 static int rtl8139_config_writable(RTL8139State *s)
1462 {
1463 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1464 {
1465 return 1;
1466 }
1467
1468 DPRINTF("Configuration registers are write-protected\n");
1469
1470 return 0;
1471 }
1472
1473 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1474 {
1475 val &= 0xffff;
1476
1477 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1478
1479 /* mask unwritable bits */
1480 uint32_t mask = 0xccff;
1481
1482 if (1 || !rtl8139_config_writable(s))
1483 {
1484 /* Speed setting and autonegotiation enable bits are read-only */
1485 mask |= 0x3000;
1486 /* Duplex mode setting is read-only */
1487 mask |= 0x0100;
1488 }
1489
1490 if (val & 0x8000) {
1491 /* Reset PHY */
1492 rtl8139_reset_phy(s);
1493 }
1494
1495 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1496
1497 s->BasicModeCtrl = val;
1498 }
1499
1500 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1501 {
1502 uint32_t ret = s->BasicModeCtrl;
1503
1504 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1505
1506 return ret;
1507 }
1508
1509 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1510 {
1511 val &= 0xffff;
1512
1513 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1514
1515 /* mask unwritable bits */
1516 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1517
1518 s->BasicModeStatus = val;
1519 }
1520
1521 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1522 {
1523 uint32_t ret = s->BasicModeStatus;
1524
1525 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1526
1527 return ret;
1528 }
1529
1530 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1531 {
1532 DeviceState *d = DEVICE(s);
1533
1534 val &= 0xff;
1535
1536 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1537
1538 /* mask unwritable bits */
1539 val = SET_MASKED(val, 0x31, s->Cfg9346);
1540
1541 uint32_t opmode = val & 0xc0;
1542 uint32_t eeprom_val = val & 0xf;
1543
1544 if (opmode == 0x80) {
1545 /* eeprom access */
1546 int eecs = (eeprom_val & 0x08)?1:0;
1547 int eesk = (eeprom_val & 0x04)?1:0;
1548 int eedi = (eeprom_val & 0x02)?1:0;
1549 prom9346_set_wire(s, eecs, eesk, eedi);
1550 } else if (opmode == 0x40) {
1551 /* Reset. */
1552 val = 0;
1553 rtl8139_reset(d);
1554 }
1555
1556 s->Cfg9346 = val;
1557 }
1558
1559 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1560 {
1561 uint32_t ret = s->Cfg9346;
1562
1563 uint32_t opmode = ret & 0xc0;
1564
1565 if (opmode == 0x80)
1566 {
1567 /* eeprom access */
1568 int eedo = prom9346_get_wire(s);
1569 if (eedo)
1570 {
1571 ret |= 0x01;
1572 }
1573 else
1574 {
1575 ret &= ~0x01;
1576 }
1577 }
1578
1579 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1580
1581 return ret;
1582 }
1583
1584 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1585 {
1586 val &= 0xff;
1587
1588 DPRINTF("Config0 write val=0x%02x\n", val);
1589
1590 if (!rtl8139_config_writable(s)) {
1591 return;
1592 }
1593
1594 /* mask unwritable bits */
1595 val = SET_MASKED(val, 0xf8, s->Config0);
1596
1597 s->Config0 = val;
1598 }
1599
1600 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1601 {
1602 uint32_t ret = s->Config0;
1603
1604 DPRINTF("Config0 read val=0x%02x\n", ret);
1605
1606 return ret;
1607 }
1608
1609 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1610 {
1611 val &= 0xff;
1612
1613 DPRINTF("Config1 write val=0x%02x\n", val);
1614
1615 if (!rtl8139_config_writable(s)) {
1616 return;
1617 }
1618
1619 /* mask unwritable bits */
1620 val = SET_MASKED(val, 0xC, s->Config1);
1621
1622 s->Config1 = val;
1623 }
1624
1625 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1626 {
1627 uint32_t ret = s->Config1;
1628
1629 DPRINTF("Config1 read val=0x%02x\n", ret);
1630
1631 return ret;
1632 }
1633
1634 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1635 {
1636 val &= 0xff;
1637
1638 DPRINTF("Config3 write val=0x%02x\n", val);
1639
1640 if (!rtl8139_config_writable(s)) {
1641 return;
1642 }
1643
1644 /* mask unwritable bits */
1645 val = SET_MASKED(val, 0x8F, s->Config3);
1646
1647 s->Config3 = val;
1648 }
1649
1650 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1651 {
1652 uint32_t ret = s->Config3;
1653
1654 DPRINTF("Config3 read val=0x%02x\n", ret);
1655
1656 return ret;
1657 }
1658
1659 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1660 {
1661 val &= 0xff;
1662
1663 DPRINTF("Config4 write val=0x%02x\n", val);
1664
1665 if (!rtl8139_config_writable(s)) {
1666 return;
1667 }
1668
1669 /* mask unwritable bits */
1670 val = SET_MASKED(val, 0x0a, s->Config4);
1671
1672 s->Config4 = val;
1673 }
1674
1675 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1676 {
1677 uint32_t ret = s->Config4;
1678
1679 DPRINTF("Config4 read val=0x%02x\n", ret);
1680
1681 return ret;
1682 }
1683
1684 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1685 {
1686 val &= 0xff;
1687
1688 DPRINTF("Config5 write val=0x%02x\n", val);
1689
1690 /* mask unwritable bits */
1691 val = SET_MASKED(val, 0x80, s->Config5);
1692
1693 s->Config5 = val;
1694 }
1695
1696 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1697 {
1698 uint32_t ret = s->Config5;
1699
1700 DPRINTF("Config5 read val=0x%02x\n", ret);
1701
1702 return ret;
1703 }
1704
1705 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1706 {
1707 if (!rtl8139_transmitter_enabled(s))
1708 {
1709 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1710 return;
1711 }
1712
1713 DPRINTF("TxConfig write val=0x%08x\n", val);
1714
1715 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1716
1717 s->TxConfig = val;
1718 }
1719
1720 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1721 {
1722 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1723
1724 uint32_t tc = s->TxConfig;
1725 tc &= 0xFFFFFF00;
1726 tc |= (val & 0x000000FF);
1727 rtl8139_TxConfig_write(s, tc);
1728 }
1729
1730 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1731 {
1732 uint32_t ret = s->TxConfig;
1733
1734 DPRINTF("TxConfig read val=0x%04x\n", ret);
1735
1736 return ret;
1737 }
1738
1739 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1740 {
1741 DPRINTF("RxConfig write val=0x%08x\n", val);
1742
1743 /* mask unwritable bits */
1744 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1745
1746 s->RxConfig = val;
1747
1748 /* reset buffer size and read/write pointers */
1749 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1750
1751 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1752 }
1753
1754 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1755 {
1756 uint32_t ret = s->RxConfig;
1757
1758 DPRINTF("RxConfig read val=0x%08x\n", ret);
1759
1760 return ret;
1761 }
1762
1763 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1764 int do_interrupt, const uint8_t *dot1q_buf)
1765 {
1766 struct iovec *iov = NULL;
1767 struct iovec vlan_iov[3];
1768
1769 if (!size)
1770 {
1771 DPRINTF("+++ empty ethernet frame\n");
1772 return;
1773 }
1774
1775 if (dot1q_buf && size >= ETH_ALEN * 2) {
1776 iov = (struct iovec[3]) {
1777 { .iov_base = buf, .iov_len = ETH_ALEN * 2 },
1778 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1779 { .iov_base = buf + ETH_ALEN * 2,
1780 .iov_len = size - ETH_ALEN * 2 },
1781 };
1782
1783 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1784 iov = vlan_iov;
1785 }
1786
1787 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1788 {
1789 size_t buf2_size;
1790 uint8_t *buf2;
1791
1792 if (iov) {
1793 buf2_size = iov_size(iov, 3);
1794 buf2 = g_malloc(buf2_size);
1795 iov_to_buf(iov, 3, 0, buf2, buf2_size);
1796 buf = buf2;
1797 }
1798
1799 DPRINTF("+++ transmit loopback mode\n");
1800 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
1801
1802 if (iov) {
1803 g_free(buf2);
1804 }
1805 }
1806 else
1807 {
1808 if (iov) {
1809 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
1810 } else {
1811 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
1812 }
1813 }
1814 }
1815
1816 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1817 {
1818 if (!rtl8139_transmitter_enabled(s))
1819 {
1820 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1821 "disabled\n", descriptor);
1822 return 0;
1823 }
1824
1825 if (s->TxStatus[descriptor] & TxHostOwns)
1826 {
1827 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1828 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1829 return 0;
1830 }
1831
1832 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1833
1834 PCIDevice *d = PCI_DEVICE(s);
1835 int txsize = s->TxStatus[descriptor] & 0x1fff;
1836 uint8_t txbuffer[0x2000];
1837
1838 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1839 txsize, s->TxAddr[descriptor]);
1840
1841 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1842
1843 /* Mark descriptor as transferred */
1844 s->TxStatus[descriptor] |= TxHostOwns;
1845 s->TxStatus[descriptor] |= TxStatOK;
1846
1847 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1848
1849 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1850 descriptor);
1851
1852 /* update interrupt */
1853 s->IntrStatus |= TxOK;
1854 rtl8139_update_irq(s);
1855
1856 return 1;
1857 }
1858
1859 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1860
1861 /* produces ones' complement sum of data */
1862 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1863 {
1864 uint32_t result = 0;
1865
1866 for (; len > 1; data+=2, len-=2)
1867 {
1868 result += *(uint16_t*)data;
1869 }
1870
1871 /* add the remainder byte */
1872 if (len)
1873 {
1874 uint8_t odd[2] = {*data, 0};
1875 result += *(uint16_t*)odd;
1876 }
1877
1878 while (result>>16)
1879 result = (result & 0xffff) + (result >> 16);
1880
1881 return result;
1882 }
1883
1884 static uint16_t ip_checksum(void *data, size_t len)
1885 {
1886 return ~ones_complement_sum((uint8_t*)data, len);
1887 }
1888
1889 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1890 {
1891 if (!rtl8139_transmitter_enabled(s))
1892 {
1893 DPRINTF("+++ C+ mode: transmitter disabled\n");
1894 return 0;
1895 }
1896
1897 if (!rtl8139_cp_transmitter_enabled(s))
1898 {
1899 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1900 return 0 ;
1901 }
1902
1903 PCIDevice *d = PCI_DEVICE(s);
1904 int descriptor = s->currCPlusTxDesc;
1905
1906 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1907
1908 /* Normal priority ring */
1909 cplus_tx_ring_desc += 16 * descriptor;
1910
1911 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1912 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1913 s->TxAddr[0], cplus_tx_ring_desc);
1914
1915 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1916
1917 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1918 txdw0 = le32_to_cpu(val);
1919 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1920 txdw1 = le32_to_cpu(val);
1921 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1922 txbufLO = le32_to_cpu(val);
1923 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1924 txbufHI = le32_to_cpu(val);
1925
1926 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1927 txdw0, txdw1, txbufLO, txbufHI);
1928
1929 /* w0 ownership flag */
1930 #define CP_TX_OWN (1<<31)
1931 /* w0 end of ring flag */
1932 #define CP_TX_EOR (1<<30)
1933 /* first segment of received packet flag */
1934 #define CP_TX_FS (1<<29)
1935 /* last segment of received packet flag */
1936 #define CP_TX_LS (1<<28)
1937 /* large send packet flag */
1938 #define CP_TX_LGSEN (1<<27)
1939 /* large send MSS mask, bits 16...25 */
1940 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1941
1942 /* IP checksum offload flag */
1943 #define CP_TX_IPCS (1<<18)
1944 /* UDP checksum offload flag */
1945 #define CP_TX_UDPCS (1<<17)
1946 /* TCP checksum offload flag */
1947 #define CP_TX_TCPCS (1<<16)
1948
1949 /* w0 bits 0...15 : buffer size */
1950 #define CP_TX_BUFFER_SIZE (1<<16)
1951 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1952 /* w1 add tag flag */
1953 #define CP_TX_TAGC (1<<17)
1954 /* w1 bits 0...15 : VLAN tag (big endian) */
1955 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1956 /* w2 low 32bit of Rx buffer ptr */
1957 /* w3 high 32bit of Rx buffer ptr */
1958
1959 /* set after transmission */
1960 /* FIFO underrun flag */
1961 #define CP_TX_STATUS_UNF (1<<25)
1962 /* transmit error summary flag, valid if set any of three below */
1963 #define CP_TX_STATUS_TES (1<<23)
1964 /* out-of-window collision flag */
1965 #define CP_TX_STATUS_OWC (1<<22)
1966 /* link failure flag */
1967 #define CP_TX_STATUS_LNKF (1<<21)
1968 /* excessive collisions flag */
1969 #define CP_TX_STATUS_EXC (1<<20)
1970
1971 if (!(txdw0 & CP_TX_OWN))
1972 {
1973 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
1974 return 0 ;
1975 }
1976
1977 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
1978
1979 if (txdw0 & CP_TX_FS)
1980 {
1981 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1982 "descriptor\n", descriptor);
1983
1984 /* reset internal buffer offset */
1985 s->cplus_txbuffer_offset = 0;
1986 }
1987
1988 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1989 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1990
1991 /* make sure we have enough space to assemble the packet */
1992 if (!s->cplus_txbuffer)
1993 {
1994 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1995 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
1996 s->cplus_txbuffer_offset = 0;
1997
1998 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
1999 s->cplus_txbuffer_len);
2000 }
2001
2002 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2003 {
2004 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2005 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2006 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2007 "length to %d\n", txsize);
2008 }
2009
2010 /* append more data to the packet */
2011
2012 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2013 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2014 s->cplus_txbuffer_offset);
2015
2016 pci_dma_read(d, tx_addr,
2017 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2018 s->cplus_txbuffer_offset += txsize;
2019
2020 /* seek to next Rx descriptor */
2021 if (txdw0 & CP_TX_EOR)
2022 {
2023 s->currCPlusTxDesc = 0;
2024 }
2025 else
2026 {
2027 ++s->currCPlusTxDesc;
2028 if (s->currCPlusTxDesc >= 64)
2029 s->currCPlusTxDesc = 0;
2030 }
2031
2032 /* transfer ownership to target */
2033 txdw0 &= ~CP_TX_OWN;
2034
2035 /* reset error indicator bits */
2036 txdw0 &= ~CP_TX_STATUS_UNF;
2037 txdw0 &= ~CP_TX_STATUS_TES;
2038 txdw0 &= ~CP_TX_STATUS_OWC;
2039 txdw0 &= ~CP_TX_STATUS_LNKF;
2040 txdw0 &= ~CP_TX_STATUS_EXC;
2041
2042 /* update ring data */
2043 val = cpu_to_le32(txdw0);
2044 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2045
2046 /* Now decide if descriptor being processed is holding the last segment of packet */
2047 if (txdw0 & CP_TX_LS)
2048 {
2049 uint8_t dot1q_buffer_space[VLAN_HLEN];
2050 uint16_t *dot1q_buffer;
2051
2052 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2053 descriptor);
2054
2055 /* can transfer fully assembled packet */
2056
2057 uint8_t *saved_buffer = s->cplus_txbuffer;
2058 int saved_size = s->cplus_txbuffer_offset;
2059 int saved_buffer_len = s->cplus_txbuffer_len;
2060
2061 /* create vlan tag */
2062 if (txdw1 & CP_TX_TAGC) {
2063 /* the vlan tag is in BE byte order in the descriptor
2064 * BE + le_to_cpu() + ~swap()~ = cpu */
2065 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2066 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2067
2068 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2069 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN);
2070 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2071 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2072 } else {
2073 dot1q_buffer = NULL;
2074 }
2075
2076 /* reset the card space to protect from recursive call */
2077 s->cplus_txbuffer = NULL;
2078 s->cplus_txbuffer_offset = 0;
2079 s->cplus_txbuffer_len = 0;
2080
2081 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2082 {
2083 DPRINTF("+++ C+ mode offloaded task checksum\n");
2084
2085 /* Large enough for Ethernet and IP headers? */
2086 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
2087 goto skip_offload;
2088 }
2089
2090 /* ip packet header */
2091 struct ip_header *ip = NULL;
2092 int hlen = 0;
2093 uint8_t ip_protocol = 0;
2094 uint16_t ip_data_len = 0;
2095
2096 uint8_t *eth_payload_data = NULL;
2097 size_t eth_payload_len = 0;
2098
2099 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2100 if (proto != ETH_P_IP)
2101 {
2102 goto skip_offload;
2103 }
2104
2105 DPRINTF("+++ C+ mode has IP packet\n");
2106
2107 /* Note on memory alignment: eth_payload_data is 16-bit aligned
2108 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is
2109 * even. 32-bit accesses must use ldl/stl wrappers to avoid
2110 * unaligned accesses.
2111 */
2112 eth_payload_data = saved_buffer + ETH_HLEN;
2113 eth_payload_len = saved_size - ETH_HLEN;
2114
2115 ip = (struct ip_header*)eth_payload_data;
2116
2117 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2118 DPRINTF("+++ C+ mode packet has bad IP version %d "
2119 "expected %d\n", IP_HEADER_VERSION(ip),
2120 IP_HEADER_VERSION_4);
2121 goto skip_offload;
2122 }
2123
2124 hlen = IP_HDR_GET_LEN(ip);
2125 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) {
2126 goto skip_offload;
2127 }
2128
2129 ip_protocol = ip->ip_p;
2130
2131 ip_data_len = be16_to_cpu(ip->ip_len);
2132 if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2133 goto skip_offload;
2134 }
2135 ip_data_len -= hlen;
2136
2137 if (txdw0 & CP_TX_IPCS)
2138 {
2139 DPRINTF("+++ C+ mode need IP checksum\n");
2140
2141 ip->ip_sum = 0;
2142 ip->ip_sum = ip_checksum(ip, hlen);
2143 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2144 hlen, ip->ip_sum);
2145 }
2146
2147 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2148 {
2149 /* Large enough for the TCP header? */
2150 if (ip_data_len < sizeof(tcp_header)) {
2151 goto skip_offload;
2152 }
2153
2154 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2155
2156 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2157 "frame data %d specified MSS=%d\n", ETH_MTU,
2158 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2159
2160 int tcp_send_offset = 0;
2161 int send_count = 0;
2162
2163 /* maximum IP header length is 60 bytes */
2164 uint8_t saved_ip_header[60];
2165
2166 /* save IP header template; data area is used in tcp checksum calculation */
2167 memcpy(saved_ip_header, eth_payload_data, hlen);
2168
2169 /* a placeholder for checksum calculation routine in tcp case */
2170 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2171 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2172
2173 /* pointer to TCP header */
2174 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2175
2176 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2177
2178 /* Invalid TCP data offset? */
2179 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2180 goto skip_offload;
2181 }
2182
2183 /* ETH_MTU = ip header len + tcp header len + payload */
2184 int tcp_data_len = ip_data_len - tcp_hlen;
2185 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2186
2187 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2188 "data len %d TCP chunk size %d\n", ip_data_len,
2189 tcp_hlen, tcp_data_len, tcp_chunk_size);
2190
2191 /* note the cycle below overwrites IP header data,
2192 but restores it from saved_ip_header before sending packet */
2193
2194 int is_last_frame = 0;
2195
2196 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2197 {
2198 uint16_t chunk_size = tcp_chunk_size;
2199
2200 /* check if this is the last frame */
2201 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2202 {
2203 is_last_frame = 1;
2204 chunk_size = tcp_data_len - tcp_send_offset;
2205 }
2206
2207 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2208 ldl_be_p(&p_tcp_hdr->th_seq));
2209
2210 /* add 4 TCP pseudoheader fields */
2211 /* copy IP source and destination fields */
2212 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2213
2214 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2215 "packet with %d bytes data\n", tcp_hlen +
2216 chunk_size);
2217
2218 if (tcp_send_offset)
2219 {
2220 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2221 }
2222
2223 /* keep PUSH and FIN flags only for the last frame */
2224 if (!is_last_frame)
2225 {
2226 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN);
2227 }
2228
2229 /* recalculate TCP checksum */
2230 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2231 p_tcpip_hdr->zeros = 0;
2232 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2233 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2234
2235 p_tcp_hdr->th_sum = 0;
2236
2237 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2238 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2239 tcp_checksum);
2240
2241 p_tcp_hdr->th_sum = tcp_checksum;
2242
2243 /* restore IP header */
2244 memcpy(eth_payload_data, saved_ip_header, hlen);
2245
2246 /* set IP data length and recalculate IP checksum */
2247 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2248
2249 /* increment IP id for subsequent frames */
2250 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2251
2252 ip->ip_sum = 0;
2253 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2254 DPRINTF("+++ C+ mode TSO IP header len=%d "
2255 "checksum=%04x\n", hlen, ip->ip_sum);
2256
2257 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2258 DPRINTF("+++ C+ mode TSO transferring packet size "
2259 "%d\n", tso_send_size);
2260 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2261 0, (uint8_t *) dot1q_buffer);
2262
2263 /* add transferred count to TCP sequence number */
2264 stl_be_p(&p_tcp_hdr->th_seq,
2265 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
2266 ++send_count;
2267 }
2268
2269 /* Stop sending this frame */
2270 saved_size = 0;
2271 }
2272 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2273 {
2274 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2275
2276 /* maximum IP header length is 60 bytes */
2277 uint8_t saved_ip_header[60];
2278 memcpy(saved_ip_header, eth_payload_data, hlen);
2279
2280 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2281 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2282
2283 /* add 4 TCP pseudoheader fields */
2284 /* copy IP source and destination fields */
2285 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2286
2287 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2288 {
2289 DPRINTF("+++ C+ mode calculating TCP checksum for "
2290 "packet with %d bytes data\n", ip_data_len);
2291
2292 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2293 p_tcpip_hdr->zeros = 0;
2294 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2295 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2296
2297 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2298
2299 p_tcp_hdr->th_sum = 0;
2300
2301 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2302 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2303 tcp_checksum);
2304
2305 p_tcp_hdr->th_sum = tcp_checksum;
2306 }
2307 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2308 {
2309 DPRINTF("+++ C+ mode calculating UDP checksum for "
2310 "packet with %d bytes data\n", ip_data_len);
2311
2312 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2313 p_udpip_hdr->zeros = 0;
2314 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2315 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2316
2317 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2318
2319 p_udp_hdr->uh_sum = 0;
2320
2321 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2322 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2323 udp_checksum);
2324
2325 p_udp_hdr->uh_sum = udp_checksum;
2326 }
2327
2328 /* restore IP header */
2329 memcpy(eth_payload_data, saved_ip_header, hlen);
2330 }
2331 }
2332
2333 skip_offload:
2334 /* update tally counter */
2335 ++s->tally_counters.TxOk;
2336
2337 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2338
2339 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2340 (uint8_t *) dot1q_buffer);
2341
2342 /* restore card space if there was no recursion and reset offset */
2343 if (!s->cplus_txbuffer)
2344 {
2345 s->cplus_txbuffer = saved_buffer;
2346 s->cplus_txbuffer_len = saved_buffer_len;
2347 s->cplus_txbuffer_offset = 0;
2348 }
2349 else
2350 {
2351 g_free(saved_buffer);
2352 }
2353 }
2354 else
2355 {
2356 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2357 }
2358
2359 return 1;
2360 }
2361
2362 static void rtl8139_cplus_transmit(RTL8139State *s)
2363 {
2364 int txcount = 0;
2365
2366 while (txcount < 64 && rtl8139_cplus_transmit_one(s))
2367 {
2368 ++txcount;
2369 }
2370
2371 /* Mark transfer completed */
2372 if (!txcount)
2373 {
2374 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2375 s->currCPlusTxDesc);
2376 }
2377 else
2378 {
2379 /* update interrupt status */
2380 s->IntrStatus |= TxOK;
2381 rtl8139_update_irq(s);
2382 }
2383 }
2384
2385 static void rtl8139_transmit(RTL8139State *s)
2386 {
2387 int descriptor = s->currTxDesc, txcount = 0;
2388
2389 /*while*/
2390 if (rtl8139_transmit_one(s, descriptor))
2391 {
2392 ++s->currTxDesc;
2393 s->currTxDesc %= 4;
2394 ++txcount;
2395 }
2396
2397 /* Mark transfer completed */
2398 if (!txcount)
2399 {
2400 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2401 s->currTxDesc);
2402 }
2403 }
2404
2405 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2406 {
2407
2408 int descriptor = txRegOffset/4;
2409
2410 /* handle C+ transmit mode register configuration */
2411
2412 if (s->cplus_enabled)
2413 {
2414 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2415 "descriptor=%d\n", txRegOffset, val, descriptor);
2416
2417 /* handle Dump Tally Counters command */
2418 s->TxStatus[descriptor] = val;
2419
2420 if (descriptor == 0 && (val & 0x8))
2421 {
2422 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2423
2424 /* dump tally counters to specified memory location */
2425 RTL8139TallyCounters_dma_write(s, tc_addr);
2426
2427 /* mark dump completed */
2428 s->TxStatus[0] &= ~0x8;
2429 }
2430
2431 return;
2432 }
2433
2434 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2435 txRegOffset, val, descriptor);
2436
2437 /* mask only reserved bits */
2438 val &= ~0xff00c000; /* these bits are reset on write */
2439 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2440
2441 s->TxStatus[descriptor] = val;
2442
2443 /* attempt to start transmission */
2444 rtl8139_transmit(s);
2445 }
2446
2447 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2448 uint32_t base, uint8_t addr,
2449 int size)
2450 {
2451 uint32_t reg = (addr - base) / 4;
2452 uint32_t offset = addr & 0x3;
2453 uint32_t ret = 0;
2454
2455 if (addr & (size - 1)) {
2456 DPRINTF("not implemented read for TxStatus/TxAddr "
2457 "addr=0x%x size=0x%x\n", addr, size);
2458 return ret;
2459 }
2460
2461 switch (size) {
2462 case 1: /* fall through */
2463 case 2: /* fall through */
2464 case 4:
2465 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2466 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2467 reg, addr, size, ret);
2468 break;
2469 default:
2470 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2471 break;
2472 }
2473
2474 return ret;
2475 }
2476
2477 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2478 {
2479 uint16_t ret = 0;
2480
2481 /* Simulate TSAD, it is read only anyway */
2482
2483 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2484 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2485 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2486 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2487
2488 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2489 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2490 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2491 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2492
2493 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2494 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2495 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2496 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2497
2498 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2499 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2500 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2501 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2502
2503
2504 DPRINTF("TSAD read val=0x%04x\n", ret);
2505
2506 return ret;
2507 }
2508
2509 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2510 {
2511 uint16_t ret = s->CSCR;
2512
2513 DPRINTF("CSCR read val=0x%04x\n", ret);
2514
2515 return ret;
2516 }
2517
2518 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2519 {
2520 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2521
2522 s->TxAddr[txAddrOffset/4] = val;
2523 }
2524
2525 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2526 {
2527 uint32_t ret = s->TxAddr[txAddrOffset/4];
2528
2529 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2530
2531 return ret;
2532 }
2533
2534 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2535 {
2536 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2537
2538 /* this value is off by 16 */
2539 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2540
2541 /* more buffer space may be available so try to receive */
2542 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2543
2544 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2545 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2546 }
2547
2548 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2549 {
2550 /* this value is off by 16 */
2551 uint32_t ret = s->RxBufPtr - 0x10;
2552
2553 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2554
2555 return ret;
2556 }
2557
2558 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2559 {
2560 /* this value is NOT off by 16 */
2561 uint32_t ret = s->RxBufAddr;
2562
2563 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2564
2565 return ret;
2566 }
2567
2568 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2569 {
2570 DPRINTF("RxBuf write val=0x%08x\n", val);
2571
2572 s->RxBuf = val;
2573
2574 /* may need to reset rxring here */
2575 }
2576
2577 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2578 {
2579 uint32_t ret = s->RxBuf;
2580
2581 DPRINTF("RxBuf read val=0x%08x\n", ret);
2582
2583 return ret;
2584 }
2585
2586 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2587 {
2588 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2589
2590 /* mask unwritable bits */
2591 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2592
2593 s->IntrMask = val;
2594
2595 rtl8139_update_irq(s);
2596
2597 }
2598
2599 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2600 {
2601 uint32_t ret = s->IntrMask;
2602
2603 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2604
2605 return ret;
2606 }
2607
2608 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2609 {
2610 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2611
2612 #if 0
2613
2614 /* writing to ISR has no effect */
2615
2616 return;
2617
2618 #else
2619 uint16_t newStatus = s->IntrStatus & ~val;
2620
2621 /* mask unwritable bits */
2622 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2623
2624 /* writing 1 to interrupt status register bit clears it */
2625 s->IntrStatus = 0;
2626 rtl8139_update_irq(s);
2627
2628 s->IntrStatus = newStatus;
2629 rtl8139_set_next_tctr_time(s);
2630 rtl8139_update_irq(s);
2631
2632 #endif
2633 }
2634
2635 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2636 {
2637 uint32_t ret = s->IntrStatus;
2638
2639 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2640
2641 #if 0
2642
2643 /* reading ISR clears all interrupts */
2644 s->IntrStatus = 0;
2645
2646 rtl8139_update_irq(s);
2647
2648 #endif
2649
2650 return ret;
2651 }
2652
2653 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2654 {
2655 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2656
2657 /* mask unwritable bits */
2658 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2659
2660 s->MultiIntr = val;
2661 }
2662
2663 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2664 {
2665 uint32_t ret = s->MultiIntr;
2666
2667 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2668
2669 return ret;
2670 }
2671
2672 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2673 {
2674 RTL8139State *s = opaque;
2675
2676 switch (addr)
2677 {
2678 case MAC0 ... MAC0+4:
2679 s->phys[addr - MAC0] = val;
2680 break;
2681 case MAC0+5:
2682 s->phys[addr - MAC0] = val;
2683 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2684 break;
2685 case MAC0+6 ... MAC0+7:
2686 /* reserved */
2687 break;
2688 case MAR0 ... MAR0+7:
2689 s->mult[addr - MAR0] = val;
2690 break;
2691 case ChipCmd:
2692 rtl8139_ChipCmd_write(s, val);
2693 break;
2694 case Cfg9346:
2695 rtl8139_Cfg9346_write(s, val);
2696 break;
2697 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2698 rtl8139_TxConfig_writeb(s, val);
2699 break;
2700 case Config0:
2701 rtl8139_Config0_write(s, val);
2702 break;
2703 case Config1:
2704 rtl8139_Config1_write(s, val);
2705 break;
2706 case Config3:
2707 rtl8139_Config3_write(s, val);
2708 break;
2709 case Config4:
2710 rtl8139_Config4_write(s, val);
2711 break;
2712 case Config5:
2713 rtl8139_Config5_write(s, val);
2714 break;
2715 case MediaStatus:
2716 /* ignore */
2717 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2718 val);
2719 break;
2720
2721 case HltClk:
2722 DPRINTF("HltClk write val=0x%08x\n", val);
2723 if (val == 'R')
2724 {
2725 s->clock_enabled = 1;
2726 }
2727 else if (val == 'H')
2728 {
2729 s->clock_enabled = 0;
2730 }
2731 break;
2732
2733 case TxThresh:
2734 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2735 s->TxThresh = val;
2736 break;
2737
2738 case TxPoll:
2739 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2740 if (val & (1 << 7))
2741 {
2742 DPRINTF("C+ TxPoll high priority transmission (not "
2743 "implemented)\n");
2744 //rtl8139_cplus_transmit(s);
2745 }
2746 if (val & (1 << 6))
2747 {
2748 DPRINTF("C+ TxPoll normal priority transmission\n");
2749 rtl8139_cplus_transmit(s);
2750 }
2751
2752 break;
2753
2754 default:
2755 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2756 val);
2757 break;
2758 }
2759 }
2760
2761 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2762 {
2763 RTL8139State *s = opaque;
2764
2765 switch (addr)
2766 {
2767 case IntrMask:
2768 rtl8139_IntrMask_write(s, val);
2769 break;
2770
2771 case IntrStatus:
2772 rtl8139_IntrStatus_write(s, val);
2773 break;
2774
2775 case MultiIntr:
2776 rtl8139_MultiIntr_write(s, val);
2777 break;
2778
2779 case RxBufPtr:
2780 rtl8139_RxBufPtr_write(s, val);
2781 break;
2782
2783 case BasicModeCtrl:
2784 rtl8139_BasicModeCtrl_write(s, val);
2785 break;
2786 case BasicModeStatus:
2787 rtl8139_BasicModeStatus_write(s, val);
2788 break;
2789 case NWayAdvert:
2790 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2791 s->NWayAdvert = val;
2792 break;
2793 case NWayLPAR:
2794 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2795 break;
2796 case NWayExpansion:
2797 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2798 s->NWayExpansion = val;
2799 break;
2800
2801 case CpCmd:
2802 rtl8139_CpCmd_write(s, val);
2803 break;
2804
2805 case IntrMitigate:
2806 rtl8139_IntrMitigate_write(s, val);
2807 break;
2808
2809 default:
2810 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2811 addr, val);
2812
2813 rtl8139_io_writeb(opaque, addr, val & 0xff);
2814 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2815 break;
2816 }
2817 }
2818
2819 static void rtl8139_set_next_tctr_time(RTL8139State *s)
2820 {
2821 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32;
2822
2823 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2824
2825 /* This function is called at least once per period, so it is a good
2826 * place to update the timer base.
2827 *
2828 * After one iteration of this loop the value in the Timer register does
2829 * not change, but the device model is counting up by 2^32 ticks (approx.
2830 * 130 seconds).
2831 */
2832 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2833 s->TCTR_base += ns_per_period;
2834 }
2835
2836 if (!s->TimerInt) {
2837 timer_del(s->timer);
2838 } else {
2839 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD;
2840 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2841 delta += ns_per_period;
2842 }
2843 timer_mod(s->timer, s->TCTR_base + delta);
2844 }
2845 }
2846
2847 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2848 {
2849 RTL8139State *s = opaque;
2850
2851 switch (addr)
2852 {
2853 case RxMissed:
2854 DPRINTF("RxMissed clearing on write\n");
2855 s->RxMissed = 0;
2856 break;
2857
2858 case TxConfig:
2859 rtl8139_TxConfig_write(s, val);
2860 break;
2861
2862 case RxConfig:
2863 rtl8139_RxConfig_write(s, val);
2864 break;
2865
2866 case TxStatus0 ... TxStatus0+4*4-1:
2867 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2868 break;
2869
2870 case TxAddr0 ... TxAddr0+4*4-1:
2871 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2872 break;
2873
2874 case RxBuf:
2875 rtl8139_RxBuf_write(s, val);
2876 break;
2877
2878 case RxRingAddrLO:
2879 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2880 s->RxRingAddrLO = val;
2881 break;
2882
2883 case RxRingAddrHI:
2884 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2885 s->RxRingAddrHI = val;
2886 break;
2887
2888 case Timer:
2889 DPRINTF("TCTR Timer reset on write\n");
2890 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2891 rtl8139_set_next_tctr_time(s);
2892 break;
2893
2894 case FlashReg:
2895 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2896 if (s->TimerInt != val) {
2897 s->TimerInt = val;
2898 rtl8139_set_next_tctr_time(s);
2899 }
2900 break;
2901
2902 default:
2903 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2904 addr, val);
2905 rtl8139_io_writeb(opaque, addr, val & 0xff);
2906 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2907 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2908 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2909 break;
2910 }
2911 }
2912
2913 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2914 {
2915 RTL8139State *s = opaque;
2916 int ret;
2917
2918 switch (addr)
2919 {
2920 case MAC0 ... MAC0+5:
2921 ret = s->phys[addr - MAC0];
2922 break;
2923 case MAC0+6 ... MAC0+7:
2924 ret = 0;
2925 break;
2926 case MAR0 ... MAR0+7:
2927 ret = s->mult[addr - MAR0];
2928 break;
2929 case TxStatus0 ... TxStatus0+4*4-1:
2930 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2931 addr, 1);
2932 break;
2933 case ChipCmd:
2934 ret = rtl8139_ChipCmd_read(s);
2935 break;
2936 case Cfg9346:
2937 ret = rtl8139_Cfg9346_read(s);
2938 break;
2939 case Config0:
2940 ret = rtl8139_Config0_read(s);
2941 break;
2942 case Config1:
2943 ret = rtl8139_Config1_read(s);
2944 break;
2945 case Config3:
2946 ret = rtl8139_Config3_read(s);
2947 break;
2948 case Config4:
2949 ret = rtl8139_Config4_read(s);
2950 break;
2951 case Config5:
2952 ret = rtl8139_Config5_read(s);
2953 break;
2954
2955 case MediaStatus:
2956 /* The LinkDown bit of MediaStatus is inverse with link status */
2957 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
2958 DPRINTF("MediaStatus read 0x%x\n", ret);
2959 break;
2960
2961 case HltClk:
2962 ret = s->clock_enabled;
2963 DPRINTF("HltClk read 0x%x\n", ret);
2964 break;
2965
2966 case PCIRevisionID:
2967 ret = RTL8139_PCI_REVID;
2968 DPRINTF("PCI Revision ID read 0x%x\n", ret);
2969 break;
2970
2971 case TxThresh:
2972 ret = s->TxThresh;
2973 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
2974 break;
2975
2976 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2977 ret = s->TxConfig >> 24;
2978 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
2979 break;
2980
2981 default:
2982 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
2983 ret = 0;
2984 break;
2985 }
2986
2987 return ret;
2988 }
2989
2990 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2991 {
2992 RTL8139State *s = opaque;
2993 uint32_t ret;
2994
2995 switch (addr)
2996 {
2997 case TxAddr0 ... TxAddr0+4*4-1:
2998 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
2999 break;
3000 case IntrMask:
3001 ret = rtl8139_IntrMask_read(s);
3002 break;
3003
3004 case IntrStatus:
3005 ret = rtl8139_IntrStatus_read(s);
3006 break;
3007
3008 case MultiIntr:
3009 ret = rtl8139_MultiIntr_read(s);
3010 break;
3011
3012 case RxBufPtr:
3013 ret = rtl8139_RxBufPtr_read(s);
3014 break;
3015
3016 case RxBufAddr:
3017 ret = rtl8139_RxBufAddr_read(s);
3018 break;
3019
3020 case BasicModeCtrl:
3021 ret = rtl8139_BasicModeCtrl_read(s);
3022 break;
3023 case BasicModeStatus:
3024 ret = rtl8139_BasicModeStatus_read(s);
3025 break;
3026 case NWayAdvert:
3027 ret = s->NWayAdvert;
3028 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3029 break;
3030 case NWayLPAR:
3031 ret = s->NWayLPAR;
3032 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3033 break;
3034 case NWayExpansion:
3035 ret = s->NWayExpansion;
3036 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3037 break;
3038
3039 case CpCmd:
3040 ret = rtl8139_CpCmd_read(s);
3041 break;
3042
3043 case IntrMitigate:
3044 ret = rtl8139_IntrMitigate_read(s);
3045 break;
3046
3047 case TxSummary:
3048 ret = rtl8139_TSAD_read(s);
3049 break;
3050
3051 case CSCR:
3052 ret = rtl8139_CSCR_read(s);
3053 break;
3054
3055 default:
3056 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3057
3058 ret = rtl8139_io_readb(opaque, addr);
3059 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3060
3061 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3062 break;
3063 }
3064
3065 return ret;
3066 }
3067
3068 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3069 {
3070 RTL8139State *s = opaque;
3071 uint32_t ret;
3072
3073 switch (addr)
3074 {
3075 case RxMissed:
3076 ret = s->RxMissed;
3077
3078 DPRINTF("RxMissed read val=0x%08x\n", ret);
3079 break;
3080
3081 case TxConfig:
3082 ret = rtl8139_TxConfig_read(s);
3083 break;
3084
3085 case RxConfig:
3086 ret = rtl8139_RxConfig_read(s);
3087 break;
3088
3089 case TxStatus0 ... TxStatus0+4*4-1:
3090 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3091 addr, 4);
3092 break;
3093
3094 case TxAddr0 ... TxAddr0+4*4-1:
3095 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3096 break;
3097
3098 case RxBuf:
3099 ret = rtl8139_RxBuf_read(s);
3100 break;
3101
3102 case RxRingAddrLO:
3103 ret = s->RxRingAddrLO;
3104 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3105 break;
3106
3107 case RxRingAddrHI:
3108 ret = s->RxRingAddrHI;
3109 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3110 break;
3111
3112 case Timer:
3113 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
3114 PCI_PERIOD;
3115 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3116 break;
3117
3118 case FlashReg:
3119 ret = s->TimerInt;
3120 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3121 break;
3122
3123 default:
3124 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3125
3126 ret = rtl8139_io_readb(opaque, addr);
3127 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3128 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3129 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3130
3131 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3132 break;
3133 }
3134
3135 return ret;
3136 }
3137
3138 /* */
3139
3140 static int rtl8139_post_load(void *opaque, int version_id)
3141 {
3142 RTL8139State* s = opaque;
3143 rtl8139_set_next_tctr_time(s);
3144 if (version_id < 4) {
3145 s->cplus_enabled = s->CpCmd != 0;
3146 }
3147
3148 /* nc.link_down can't be migrated, so infer link_down according
3149 * to link status bit in BasicModeStatus */
3150 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
3151
3152 return 0;
3153 }
3154
3155 static bool rtl8139_hotplug_ready_needed(void *opaque)
3156 {
3157 return qdev_machine_modified();
3158 }
3159
3160 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3161 .name = "rtl8139/hotplug_ready",
3162 .version_id = 1,
3163 .minimum_version_id = 1,
3164 .needed = rtl8139_hotplug_ready_needed,
3165 .fields = (VMStateField[]) {
3166 VMSTATE_END_OF_LIST()
3167 }
3168 };
3169
3170 static int rtl8139_pre_save(void *opaque)
3171 {
3172 RTL8139State* s = opaque;
3173 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3174
3175 /* for migration to older versions */
3176 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD;
3177 s->rtl8139_mmio_io_addr_dummy = 0;
3178
3179 return 0;
3180 }
3181
3182 static const VMStateDescription vmstate_rtl8139 = {
3183 .name = "rtl8139",
3184 .version_id = 5,
3185 .minimum_version_id = 3,
3186 .post_load = rtl8139_post_load,
3187 .pre_save = rtl8139_pre_save,
3188 .fields = (VMStateField[]) {
3189 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3190 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3191 VMSTATE_BUFFER(mult, RTL8139State),
3192 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3193 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3194
3195 VMSTATE_UINT32(RxBuf, RTL8139State),
3196 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3197 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3198 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3199
3200 VMSTATE_UINT16(IntrStatus, RTL8139State),
3201 VMSTATE_UINT16(IntrMask, RTL8139State),
3202
3203 VMSTATE_UINT32(TxConfig, RTL8139State),
3204 VMSTATE_UINT32(RxConfig, RTL8139State),
3205 VMSTATE_UINT32(RxMissed, RTL8139State),
3206 VMSTATE_UINT16(CSCR, RTL8139State),
3207
3208 VMSTATE_UINT8(Cfg9346, RTL8139State),
3209 VMSTATE_UINT8(Config0, RTL8139State),
3210 VMSTATE_UINT8(Config1, RTL8139State),
3211 VMSTATE_UINT8(Config3, RTL8139State),
3212 VMSTATE_UINT8(Config4, RTL8139State),
3213 VMSTATE_UINT8(Config5, RTL8139State),
3214
3215 VMSTATE_UINT8(clock_enabled, RTL8139State),
3216 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3217
3218 VMSTATE_UINT16(MultiIntr, RTL8139State),
3219
3220 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3221 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3222 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3223 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3224 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3225
3226 VMSTATE_UINT16(CpCmd, RTL8139State),
3227 VMSTATE_UINT8(TxThresh, RTL8139State),
3228
3229 VMSTATE_UNUSED(4),
3230 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3231 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3232
3233 VMSTATE_UINT32(currTxDesc, RTL8139State),
3234 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3235 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3236 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3237 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3238
3239 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3240 VMSTATE_INT32(eeprom.mode, RTL8139State),
3241 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3242 VMSTATE_UINT8(eeprom.address, RTL8139State),
3243 VMSTATE_UINT16(eeprom.input, RTL8139State),
3244 VMSTATE_UINT16(eeprom.output, RTL8139State),
3245
3246 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3247 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3248 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3249 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3250
3251 VMSTATE_UINT32(TCTR, RTL8139State),
3252 VMSTATE_UINT32(TimerInt, RTL8139State),
3253 VMSTATE_INT64(TCTR_base, RTL8139State),
3254
3255 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State),
3256 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State),
3257 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State),
3258 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State),
3259 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State),
3260 VMSTATE_UINT16(tally_counters.FAE, RTL8139State),
3261 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State),
3262 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State),
3263 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State),
3264 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State),
3265 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5),
3266 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State),
3267 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State),
3268
3269 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3270 VMSTATE_END_OF_LIST()
3271 },
3272 .subsections = (const VMStateDescription*[]) {
3273 &vmstate_rtl8139_hotplug_ready,
3274 NULL
3275 }
3276 };
3277
3278 /***********************************************************/
3279 /* PCI RTL8139 definitions */
3280
3281 static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3282 uint64_t val, unsigned size)
3283 {
3284 switch (size) {
3285 case 1:
3286 rtl8139_io_writeb(opaque, addr, val);
3287 break;
3288 case 2:
3289 rtl8139_io_writew(opaque, addr, val);
3290 break;
3291 case 4:
3292 rtl8139_io_writel(opaque, addr, val);
3293 break;
3294 }
3295 }
3296
3297 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3298 unsigned size)
3299 {
3300 switch (size) {
3301 case 1:
3302 return rtl8139_io_readb(opaque, addr);
3303 case 2:
3304 return rtl8139_io_readw(opaque, addr);
3305 case 4:
3306 return rtl8139_io_readl(opaque, addr);
3307 }
3308
3309 return -1;
3310 }
3311
3312 static const MemoryRegionOps rtl8139_io_ops = {
3313 .read = rtl8139_ioport_read,
3314 .write = rtl8139_ioport_write,
3315 .impl = {
3316 .min_access_size = 1,
3317 .max_access_size = 4,
3318 },
3319 .endianness = DEVICE_LITTLE_ENDIAN,
3320 };
3321
3322 static void rtl8139_timer(void *opaque)
3323 {
3324 RTL8139State *s = opaque;
3325
3326 if (!s->clock_enabled)
3327 {
3328 DPRINTF(">>> timer: clock is not running\n");
3329 return;
3330 }
3331
3332 s->IntrStatus |= PCSTimeout;
3333 rtl8139_update_irq(s);
3334 rtl8139_set_next_tctr_time(s);
3335 }
3336
3337 static void pci_rtl8139_uninit(PCIDevice *dev)
3338 {
3339 RTL8139State *s = RTL8139(dev);
3340
3341 g_free(s->cplus_txbuffer);
3342 s->cplus_txbuffer = NULL;
3343 timer_del(s->timer);
3344 timer_free(s->timer);
3345 qemu_del_nic(s->nic);
3346 }
3347
3348 static void rtl8139_set_link_status(NetClientState *nc)
3349 {
3350 RTL8139State *s = qemu_get_nic_opaque(nc);
3351
3352 if (nc->link_down) {
3353 s->BasicModeStatus &= ~0x04;
3354 } else {
3355 s->BasicModeStatus |= 0x04;
3356 }
3357
3358 s->IntrStatus |= RxUnderrun;
3359 rtl8139_update_irq(s);
3360 }
3361
3362 static NetClientInfo net_rtl8139_info = {
3363 .type = NET_CLIENT_DRIVER_NIC,
3364 .size = sizeof(NICState),
3365 .can_receive = rtl8139_can_receive,
3366 .receive = rtl8139_receive,
3367 .link_status_changed = rtl8139_set_link_status,
3368 };
3369
3370 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
3371 {
3372 RTL8139State *s = RTL8139(dev);
3373 DeviceState *d = DEVICE(dev);
3374 uint8_t *pci_conf;
3375
3376 pci_conf = dev->config;
3377 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3378 /* TODO: start of capability list, but no capability
3379 * list bit in status register, and offset 0xdc seems unused. */
3380 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3381
3382 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3383 "rtl8139", 0x100);
3384 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io,
3385 0, 0x100);
3386
3387 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3388 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3389
3390 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3391
3392 /* prepare eeprom */
3393 s->eeprom.contents[0] = 0x8129;
3394 #if 1
3395 /* PCI vendor and device ID should be mirrored here */
3396 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3397 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3398 #endif
3399 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3400 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3401 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3402
3403 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3404 object_get_typename(OBJECT(dev)), d->id, s);
3405 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
3406
3407 s->cplus_txbuffer = NULL;
3408 s->cplus_txbuffer_len = 0;
3409 s->cplus_txbuffer_offset = 0;
3410
3411 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
3412 }
3413
3414 static void rtl8139_instance_init(Object *obj)
3415 {
3416 RTL8139State *s = RTL8139(obj);
3417
3418 device_add_bootindex_property(obj, &s->conf.bootindex,
3419 "bootindex", "/ethernet-phy@0",
3420 DEVICE(obj));
3421 }
3422
3423 static Property rtl8139_properties[] = {
3424 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3425 DEFINE_PROP_END_OF_LIST(),
3426 };
3427
3428 static void rtl8139_class_init(ObjectClass *klass, void *data)
3429 {
3430 DeviceClass *dc = DEVICE_CLASS(klass);
3431 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3432
3433 k->realize = pci_rtl8139_realize;
3434 k->exit = pci_rtl8139_uninit;
3435 k->romfile = "efi-rtl8139.rom";
3436 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3437 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3438 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3439 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3440 dc->reset = rtl8139_reset;
3441 dc->vmsd = &vmstate_rtl8139;
3442 device_class_set_props(dc, rtl8139_properties);
3443 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
3444 }
3445
3446 static const TypeInfo rtl8139_info = {
3447 .name = TYPE_RTL8139,
3448 .parent = TYPE_PCI_DEVICE,
3449 .instance_size = sizeof(RTL8139State),
3450 .class_init = rtl8139_class_init,
3451 .instance_init = rtl8139_instance_init,
3452 .interfaces = (InterfaceInfo[]) {
3453 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3454 { },
3455 },
3456 };
3457
3458 static void rtl8139_register_types(void)
3459 {
3460 type_register_static(&rtl8139_info);
3461 }
3462
3463 type_init(rtl8139_register_types)
AR7 emulation for QEMU