hw/net/opencores_eth.c

   1 /*
   2  * OpenCores Ethernet MAC 10/100 + subset of
   3  * National Semiconductors DP83848C 10/100 PHY
   4  *
   5  * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
   6  * http://cache.national.com/ds/DP/DP83848C.pdf
   7  *
   8  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions are met:
  13  *     * Redistributions of source code must retain the above copyright
  14  *       notice, this list of conditions and the following disclaimer.
  15  *     * Redistributions in binary form must reproduce the above copyright
  16  *       notice, this list of conditions and the following disclaimer in the
  17  *       documentation and/or other materials provided with the distribution.
  18  *     * Neither the name of the Open Source and Linux Lab nor the
  19  *       names of its contributors may be used to endorse or promote products
  20  *       derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "qemu/osdep.h"
  35 #include "hw/irq.h"
  36 #include "hw/net/mii.h"
  37 #include "hw/qdev-properties.h"
  38 #include "hw/sysbus.h"
  39 #include "net/net.h"
  40 #include "qemu/module.h"
  41 #include "net/eth.h"
  42 #include "trace.h"
  43 #include "qom/object.h"
  44
  45 /* RECSMALL is not used because it breaks tap networking in linux:
  46  * incoming ARP responses are too short
  47  */
  48 #undef USE_RECSMALL
  49
  50 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
  51 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
  52 #define GET_REGFIELD(s, reg, field) \
  53     GET_FIELD((s)->regs[reg], reg ## _ ## field)
  54
  55 #define SET_FIELD(v, field, data) \
  56     ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
  57 #define SET_REGFIELD(s, reg, field, data) \
  58     SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
  59
  60 /* PHY MII registers */
  61 enum {
  62     MII_REG_MAX = 16,
  63 };
  64
  65 typedef struct Mii {
  66     uint16_t regs[MII_REG_MAX];
  67     bool link_ok;
  68 } Mii;
  69
  70 static void mii_set_link(Mii *s, bool link_ok)
  71 {
  72     if (link_ok) {
  73         s->regs[MII_BMSR] |= MII_BMSR_LINK_ST;
  74         s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX |
  75             MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
  76     } else {
  77         s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST;
  78         s->regs[MII_ANLPAR] &= 0x01ff;
  79     }
  80     s->link_ok = link_ok;
  81 }
  82
  83 static void mii_reset(Mii *s)
  84 {
  85     memset(s->regs, 0, sizeof(s->regs));
  86     s->regs[MII_BMCR] = MII_BMCR_AUTOEN;
  87     s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD |
  88         MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS |
  89         MII_BMSR_AN_COMP | MII_BMSR_AUTONEG;
  90     s->regs[MII_PHYID1] = 0x2000;
  91     s->regs[MII_PHYID2] = 0x5c90;
  92     s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX |
  93         MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD;
  94     mii_set_link(s, s->link_ok);
  95 }
  96
  97 static void mii_ro(Mii *s, uint16_t v)
  98 {
  99 }
 100
 101 static void mii_write_bmcr(Mii *s, uint16_t v)
 102 {
 103     if (v & MII_BMCR_RESET) {
 104         mii_reset(s);
 105     } else {
 106         s->regs[MII_BMCR] = v;
 107     }
 108 }
 109
 110 static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
 111 {
 112     static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
 113         [MII_BMCR] = mii_write_bmcr,
 114         [MII_BMSR] = mii_ro,
 115         [MII_PHYID1] = mii_ro,
 116         [MII_PHYID2] = mii_ro,
 117     };
 118
 119     if (idx < MII_REG_MAX) {
 120         trace_open_eth_mii_write(idx, v);
 121         if (reg_write[idx]) {
 122             reg_write[idx](s, v);
 123         } else {
 124             s->regs[idx] = v;
 125         }
 126     }
 127 }
 128
 129 static uint16_t mii_read_host(Mii *s, unsigned idx)
 130 {
 131     trace_open_eth_mii_read(idx, s->regs[idx]);
 132     return s->regs[idx];
 133 }
 134
 135 /* OpenCores Ethernet registers */
 136 enum {
 137     MODER,
 138     INT_SOURCE,
 139     INT_MASK,
 140     IPGT,
 141     IPGR1,
 142     IPGR2,
 143     PACKETLEN,
 144     COLLCONF,
 145     TX_BD_NUM,
 146     CTRLMODER,
 147     MIIMODER,
 148     MIICOMMAND,
 149     MIIADDRESS,
 150     MIITX_DATA,
 151     MIIRX_DATA,
 152     MIISTATUS,
 153     MAC_ADDR0,
 154     MAC_ADDR1,
 155     HASH0,
 156     HASH1,
 157     TXCTRL,
 158     REG_MAX,
 159 };
 160
 161 enum {
 162     MODER_RECSMALL = 0x10000,
 163     MODER_PAD = 0x8000,
 164     MODER_HUGEN = 0x4000,
 165     MODER_RST = 0x800,
 166     MODER_LOOPBCK = 0x80,
 167     MODER_PRO = 0x20,
 168     MODER_IAM = 0x10,
 169     MODER_BRO = 0x8,
 170     MODER_TXEN = 0x2,
 171     MODER_RXEN = 0x1,
 172 };
 173
 174 enum {
 175     INT_SOURCE_BUSY = 0x10,
 176     INT_SOURCE_RXB = 0x4,
 177     INT_SOURCE_TXB = 0x1,
 178 };
 179
 180 enum {
 181     PACKETLEN_MINFL = 0xffff0000,
 182     PACKETLEN_MINFL_LBN = 16,
 183     PACKETLEN_MAXFL = 0xffff,
 184     PACKETLEN_MAXFL_LBN = 0,
 185 };
 186
 187 enum {
 188     MIICOMMAND_WCTRLDATA = 0x4,
 189     MIICOMMAND_RSTAT = 0x2,
 190     MIICOMMAND_SCANSTAT = 0x1,
 191 };
 192
 193 enum {
 194     MIIADDRESS_RGAD = 0x1f00,
 195     MIIADDRESS_RGAD_LBN = 8,
 196     MIIADDRESS_FIAD = 0x1f,
 197     MIIADDRESS_FIAD_LBN = 0,
 198 };
 199
 200 enum {
 201     MIITX_DATA_CTRLDATA = 0xffff,
 202     MIITX_DATA_CTRLDATA_LBN = 0,
 203 };
 204
 205 enum {
 206     MIIRX_DATA_PRSD = 0xffff,
 207     MIIRX_DATA_PRSD_LBN = 0,
 208 };
 209
 210 enum {
 211     MIISTATUS_LINKFAIL = 0x1,
 212     MIISTATUS_LINKFAIL_LBN = 0,
 213 };
 214
 215 enum {
 216     MAC_ADDR0_BYTE2 = 0xff000000,
 217     MAC_ADDR0_BYTE2_LBN = 24,
 218     MAC_ADDR0_BYTE3 = 0xff0000,
 219     MAC_ADDR0_BYTE3_LBN = 16,
 220     MAC_ADDR0_BYTE4 = 0xff00,
 221     MAC_ADDR0_BYTE4_LBN = 8,
 222     MAC_ADDR0_BYTE5 = 0xff,
 223     MAC_ADDR0_BYTE5_LBN = 0,
 224 };
 225
 226 enum {
 227     MAC_ADDR1_BYTE0 = 0xff00,
 228     MAC_ADDR1_BYTE0_LBN = 8,
 229     MAC_ADDR1_BYTE1 = 0xff,
 230     MAC_ADDR1_BYTE1_LBN = 0,
 231 };
 232
 233 enum {
 234     TXD_LEN = 0xffff0000,
 235     TXD_LEN_LBN = 16,
 236     TXD_RD = 0x8000,
 237     TXD_IRQ = 0x4000,
 238     TXD_WR = 0x2000,
 239     TXD_PAD = 0x1000,
 240     TXD_CRC = 0x800,
 241     TXD_UR = 0x100,
 242     TXD_RTRY = 0xf0,
 243     TXD_RTRY_LBN = 4,
 244     TXD_RL = 0x8,
 245     TXD_LC = 0x4,
 246     TXD_DF = 0x2,
 247     TXD_CS = 0x1,
 248 };
 249
 250 enum {
 251     RXD_LEN = 0xffff0000,
 252     RXD_LEN_LBN = 16,
 253     RXD_E = 0x8000,
 254     RXD_IRQ = 0x4000,
 255     RXD_WRAP = 0x2000,
 256     RXD_CF = 0x100,
 257     RXD_M = 0x80,
 258     RXD_OR = 0x40,
 259     RXD_IS = 0x20,
 260     RXD_DN = 0x10,
 261     RXD_TL = 0x8,
 262     RXD_SF = 0x4,
 263     RXD_CRC = 0x2,
 264     RXD_LC = 0x1,
 265 };
 266
 267 typedef struct desc {
 268     uint32_t len_flags;
 269     uint32_t buf_ptr;
 270 } desc;
 271
 272 #define DEFAULT_PHY 1
 273
 274 #define TYPE_OPEN_ETH "open_eth"
 275 typedef struct OpenEthState OpenEthState;
 276 DECLARE_INSTANCE_CHECKER(OpenEthState, OPEN_ETH,
 277                          TYPE_OPEN_ETH)
 278
 279 struct OpenEthState {
 280     SysBusDevice parent_obj;
 281
 282     NICState *nic;
 283     NICConf conf;
 284     MemoryRegion reg_io;
 285     MemoryRegion desc_io;
 286     qemu_irq irq;
 287
 288     Mii mii;
 289     uint32_t regs[REG_MAX];
 290     unsigned tx_desc;
 291     unsigned rx_desc;
 292     desc desc[128];
 293 };
 294
 295 static desc *rx_desc(OpenEthState *s)
 296 {
 297     return s->desc + s->rx_desc;
 298 }
 299
 300 static desc *tx_desc(OpenEthState *s)
 301 {
 302     return s->desc + s->tx_desc;
 303 }
 304
 305 static void open_eth_update_irq(OpenEthState *s,
 306         uint32_t old, uint32_t new)
 307 {
 308     if (!old != !new) {
 309         trace_open_eth_update_irq(new);
 310         qemu_set_irq(s->irq, new);
 311     }
 312 }
 313
 314 static void open_eth_int_source_write(OpenEthState *s,
 315         uint32_t val)
 316 {
 317     uint32_t old_val = s->regs[INT_SOURCE];
 318
 319     s->regs[INT_SOURCE] = val;
 320     open_eth_update_irq(s, old_val & s->regs[INT_MASK],
 321             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 322 }
 323
 324 static void open_eth_set_link_status(NetClientState *nc)
 325 {
 326     OpenEthState *s = qemu_get_nic_opaque(nc);
 327
 328     if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
 329         SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
 330     }
 331     mii_set_link(&s->mii, !nc->link_down);
 332 }
 333
 334 static void open_eth_reset(void *opaque)
 335 {
 336     OpenEthState *s = opaque;
 337
 338     memset(s->regs, 0, sizeof(s->regs));
 339     s->regs[MODER] = 0xa000;
 340     s->regs[IPGT] = 0x12;
 341     s->regs[IPGR1] = 0xc;
 342     s->regs[IPGR2] = 0x12;
 343     s->regs[PACKETLEN] = 0x400600;
 344     s->regs[COLLCONF] = 0xf003f;
 345     s->regs[TX_BD_NUM] = 0x40;
 346     s->regs[MIIMODER] = 0x64;
 347
 348     s->tx_desc = 0;
 349     s->rx_desc = 0x40;
 350
 351     mii_reset(&s->mii);
 352     open_eth_set_link_status(qemu_get_queue(s->nic));
 353 }
 354
 355 static bool open_eth_can_receive(NetClientState *nc)
 356 {
 357     OpenEthState *s = qemu_get_nic_opaque(nc);
 358
 359     return GET_REGBIT(s, MODER, RXEN) && (s->regs[TX_BD_NUM] < 0x80);
 360 }
 361
 362 static ssize_t open_eth_receive(NetClientState *nc,
 363         const uint8_t *buf, size_t size)
 364 {
 365     OpenEthState *s = qemu_get_nic_opaque(nc);
 366     size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
 367     size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
 368     size_t fcsl = 4;
 369     bool miss = true;
 370
 371     trace_open_eth_receive((unsigned)size);
 372
 373     if (size >= 6) {
 374         static const uint8_t bcast_addr[] = {
 375             0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 376         };
 377         if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
 378             miss = GET_REGBIT(s, MODER, BRO);
 379         } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
 380             unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
 381             miss = !(s->regs[HASH0 + mcast_idx / 32] &
 382                     (1 << (mcast_idx % 32)));
 383             trace_open_eth_receive_mcast(
 384                     mcast_idx, s->regs[HASH0], s->regs[HASH1]);
 385         } else {
 386             miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
 387                 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
 388                 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
 389                 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
 390                 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
 391                 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
 392         }
 393     }
 394
 395     if (miss && !GET_REGBIT(s, MODER, PRO)) {
 396         trace_open_eth_receive_reject();
 397         return size;
 398     }
 399
 400 #ifdef USE_RECSMALL
 401     if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
 402 #else
 403     {
 404 #endif
 405         static const uint8_t zero[64] = {0};
 406         desc *desc = rx_desc(s);
 407         size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
 408
 409         if (!(desc->len_flags & RXD_E)) {
 410             open_eth_int_source_write(s,
 411                     s->regs[INT_SOURCE] | INT_SOURCE_BUSY);
 412             return size;
 413         }
 414
 415         desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
 416                 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
 417
 418         if (copy_size > size) {
 419             copy_size = size;
 420         } else {
 421             fcsl = 0;
 422         }
 423         if (miss) {
 424             desc->len_flags |= RXD_M;
 425         }
 426         if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
 427             desc->len_flags |= RXD_TL;
 428         }
 429 #ifdef USE_RECSMALL
 430         if (size < minfl) {
 431             desc->len_flags |= RXD_SF;
 432         }
 433 #endif
 434
 435         cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
 436
 437         if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
 438             if (minfl - copy_size > fcsl) {
 439                 fcsl = 0;
 440             } else {
 441                 fcsl -= minfl - copy_size;
 442             }
 443             while (copy_size < minfl) {
 444                 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
 445                     minfl - copy_size : sizeof(zero);
 446
 447                 cpu_physical_memory_write(desc->buf_ptr + copy_size,
 448                         zero, zero_sz);
 449                 copy_size += zero_sz;
 450             }
 451         }
 452
 453         /* There's no FCS in the frames handed to us by the QEMU, zero fill it.
 454          * Don't do it if the frame is cut at the MAXFL or padded with 4 or
 455          * more bytes to the MINFL.
 456          */
 457         cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
 458         copy_size += fcsl;
 459
 460         SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
 461
 462         if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
 463             s->rx_desc = s->regs[TX_BD_NUM];
 464         } else {
 465             ++s->rx_desc;
 466         }
 467         desc->len_flags &= ~RXD_E;
 468
 469         trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
 470
 471         if (desc->len_flags & RXD_IRQ) {
 472             open_eth_int_source_write(s,
 473                     s->regs[INT_SOURCE] | INT_SOURCE_RXB);
 474         }
 475     }
 476     return size;
 477 }
 478
 479 static NetClientInfo net_open_eth_info = {
 480     .type = NET_CLIENT_DRIVER_NIC,
 481     .size = sizeof(NICState),
 482     .can_receive = open_eth_can_receive,
 483     .receive = open_eth_receive,
 484     .link_status_changed = open_eth_set_link_status,
 485 };
 486
 487 static void open_eth_start_xmit(OpenEthState *s, desc *tx)
 488 {
 489     uint8_t *buf = NULL;
 490     uint8_t buffer[0x600];
 491     unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
 492     unsigned tx_len = len;
 493
 494     if ((tx->len_flags & TXD_PAD) &&
 495             tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
 496         tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
 497     }
 498     if (!GET_REGBIT(s, MODER, HUGEN) &&
 499             tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
 500         tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
 501     }
 502
 503     trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
 504
 505     if (tx_len > sizeof(buffer)) {
 506         buf = g_new(uint8_t, tx_len);
 507     } else {
 508         buf = buffer;
 509     }
 510     if (len > tx_len) {
 511         len = tx_len;
 512     }
 513     cpu_physical_memory_read(tx->buf_ptr, buf, len);
 514     if (tx_len > len) {
 515         memset(buf + len, 0, tx_len - len);
 516     }
 517     qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len);
 518     if (tx_len > sizeof(buffer)) {
 519         g_free(buf);
 520     }
 521
 522     if (tx->len_flags & TXD_WR) {
 523         s->tx_desc = 0;
 524     } else {
 525         ++s->tx_desc;
 526         if (s->tx_desc >= s->regs[TX_BD_NUM]) {
 527             s->tx_desc = 0;
 528         }
 529     }
 530     tx->len_flags &= ~(TXD_RD | TXD_UR |
 531             TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
 532     if (tx->len_flags & TXD_IRQ) {
 533         open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
 534     }
 535
 536 }
 537
 538 static void open_eth_check_start_xmit(OpenEthState *s)
 539 {
 540     desc *tx = tx_desc(s);
 541     if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
 542             (tx->len_flags & TXD_RD) &&
 543             GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
 544         open_eth_start_xmit(s, tx);
 545     }
 546 }
 547
 548 static uint64_t open_eth_reg_read(void *opaque,
 549         hwaddr addr, unsigned int size)
 550 {
 551     static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
 552     };
 553     OpenEthState *s = opaque;
 554     unsigned idx = addr / 4;
 555     uint64_t v = 0;
 556
 557     if (idx < REG_MAX) {
 558         if (reg_read[idx]) {
 559             v = reg_read[idx](s);
 560         } else {
 561             v = s->regs[idx];
 562         }
 563     }
 564     trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
 565     return v;
 566 }
 567
 568 static void open_eth_notify_can_receive(OpenEthState *s)
 569 {
 570     NetClientState *nc = qemu_get_queue(s->nic);
 571
 572     if (open_eth_can_receive(nc)) {
 573         qemu_flush_queued_packets(nc);
 574     }
 575 }
 576
 577 static void open_eth_ro(OpenEthState *s, uint32_t val)
 578 {
 579 }
 580
 581 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
 582 {
 583     uint32_t set = val & ~s->regs[MODER];
 584
 585     if (set & MODER_RST) {
 586         open_eth_reset(s);
 587     }
 588
 589     s->regs[MODER] = val;
 590
 591     if (set & MODER_RXEN) {
 592         s->rx_desc = s->regs[TX_BD_NUM];
 593         open_eth_notify_can_receive(s);
 594     }
 595     if (set & MODER_TXEN) {
 596         s->tx_desc = 0;
 597         open_eth_check_start_xmit(s);
 598     }
 599 }
 600
 601 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
 602 {
 603     uint32_t old = s->regs[INT_SOURCE];
 604
 605     s->regs[INT_SOURCE] &= ~val;
 606     open_eth_update_irq(s, old & s->regs[INT_MASK],
 607             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 608 }
 609
 610 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
 611 {
 612     uint32_t old = s->regs[INT_MASK];
 613
 614     s->regs[INT_MASK] = val;
 615     open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
 616             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 617 }
 618
 619 static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val)
 620 {
 621     if (val < 0x80) {
 622         bool enable = s->regs[TX_BD_NUM] == 0x80;
 623
 624         s->regs[TX_BD_NUM] = val;
 625         if (enable) {
 626             open_eth_notify_can_receive(s);
 627         }
 628     }
 629 }
 630
 631 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
 632 {
 633     unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
 634     unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
 635
 636     if (val & MIICOMMAND_WCTRLDATA) {
 637         if (fiad == DEFAULT_PHY) {
 638             mii_write_host(&s->mii, rgad,
 639                     GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 640         }
 641     }
 642     if (val & MIICOMMAND_RSTAT) {
 643         if (fiad == DEFAULT_PHY) {
 644             SET_REGFIELD(s, MIIRX_DATA, PRSD,
 645                     mii_read_host(&s->mii, rgad));
 646         } else {
 647             s->regs[MIIRX_DATA] = 0xffff;
 648         }
 649         SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down);
 650     }
 651 }
 652
 653 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
 654 {
 655     SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
 656     if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
 657         mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
 658                 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 659     }
 660 }
 661
 662 static void open_eth_reg_write(void *opaque,
 663         hwaddr addr, uint64_t val, unsigned int size)
 664 {
 665     static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
 666         [MODER] = open_eth_moder_host_write,
 667         [INT_SOURCE] = open_eth_int_source_host_write,
 668         [INT_MASK] = open_eth_int_mask_host_write,
 669         [TX_BD_NUM] = open_eth_tx_bd_num_host_write,
 670         [MIICOMMAND] = open_eth_mii_command_host_write,
 671         [MIITX_DATA] = open_eth_mii_tx_host_write,
 672         [MIISTATUS] = open_eth_ro,
 673     };
 674     OpenEthState *s = opaque;
 675     unsigned idx = addr / 4;
 676
 677     if (idx < REG_MAX) {
 678         trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
 679         if (reg_write[idx]) {
 680             reg_write[idx](s, val);
 681         } else {
 682             s->regs[idx] = val;
 683         }
 684     }
 685 }
 686
 687 static uint64_t open_eth_desc_read(void *opaque,
 688         hwaddr addr, unsigned int size)
 689 {
 690     OpenEthState *s = opaque;
 691     uint64_t v = 0;
 692
 693     addr &= 0x3ff;
 694     memcpy(&v, (uint8_t *)s->desc + addr, size);
 695     trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
 696     return v;
 697 }
 698
 699 static void open_eth_desc_write(void *opaque,
 700         hwaddr addr, uint64_t val, unsigned int size)
 701 {
 702     OpenEthState *s = opaque;
 703
 704     addr &= 0x3ff;
 705     trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
 706     memcpy((uint8_t *)s->desc + addr, &val, size);
 707     open_eth_check_start_xmit(s);
 708 }
 709
 710
 711 static const MemoryRegionOps open_eth_reg_ops = {
 712     .read = open_eth_reg_read,
 713     .write = open_eth_reg_write,
 714 };
 715
 716 static const MemoryRegionOps open_eth_desc_ops = {
 717     .read = open_eth_desc_read,
 718     .write = open_eth_desc_write,
 719 };
 720
 721 static void sysbus_open_eth_realize(DeviceState *dev, Error **errp)
 722 {
 723     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 724     OpenEthState *s = OPEN_ETH(dev);
 725
 726     memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
 727             "open_eth.regs", 0x54);
 728     sysbus_init_mmio(sbd, &s->reg_io);
 729
 730     memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
 731             "open_eth.desc", 0x400);
 732     sysbus_init_mmio(sbd, &s->desc_io);
 733
 734     sysbus_init_irq(sbd, &s->irq);
 735
 736     s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
 737                           object_get_typename(OBJECT(s)), dev->id, s);
 738 }
 739
 740 static void qdev_open_eth_reset(DeviceState *dev)
 741 {
 742     OpenEthState *d = OPEN_ETH(dev);
 743
 744     open_eth_reset(d);
 745 }
 746
 747 static Property open_eth_properties[] = {
 748     DEFINE_NIC_PROPERTIES(OpenEthState, conf),
 749     DEFINE_PROP_END_OF_LIST(),
 750 };
 751
 752 static void open_eth_class_init(ObjectClass *klass, void *data)
 753 {
 754     DeviceClass *dc = DEVICE_CLASS(klass);
 755
 756     dc->realize = sysbus_open_eth_realize;
 757     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 758     dc->desc = "Opencores 10/100 Mbit Ethernet";
 759     dc->reset = qdev_open_eth_reset;
 760     device_class_set_props(dc, open_eth_properties);
 761 }
 762
 763 static const TypeInfo open_eth_info = {
 764     .name          = TYPE_OPEN_ETH,
 765     .parent        = TYPE_SYS_BUS_DEVICE,
 766     .instance_size = sizeof(OpenEthState),
 767     .class_init    = open_eth_class_init,
 768 };
 769
 770 static void open_eth_register_types(void)
 771 {
 772     type_register_static(&open_eth_info);
 773 }
 774
 775 type_init(open_eth_register_types)