hw/intc/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "migration/vmstate.h"
  27 #include "monitor/monitor.h"
  28 #include "qemu/module.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/intc/intc.h"
  31 #include "hw/irq.h"
  32 #include "trace.h"
  33 #include "qom/object.h"
  34
  35 //#define DEBUG_IRQ_COUNT
  36
  37 /*
  38  * Registers of interrupt controller in sun4m.
  39  *
  40  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  41  * produced as NCR89C105. See
  42  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  43  *
  44  * There is a system master controller and one for each cpu.
  45  *
  46  */
  47
  48 #define MAX_CPUS 16
  49 #define MAX_PILS 16
  50
  51 struct SLAVIO_INTCTLState;
  52
  53 typedef struct SLAVIO_CPUINTCTLState {
  54     MemoryRegion iomem;
  55     struct SLAVIO_INTCTLState *master;
  56     uint32_t intreg_pending;
  57     uint32_t cpu;
  58     uint32_t irl_out;
  59 } SLAVIO_CPUINTCTLState;
  60
  61 #define TYPE_SLAVIO_INTCTL "slavio_intctl"
  62 typedef struct SLAVIO_INTCTLState SLAVIO_INTCTLState;
  63 DECLARE_INSTANCE_CHECKER(SLAVIO_INTCTLState, SLAVIO_INTCTL,
  64                          TYPE_SLAVIO_INTCTL)
  65
  66 struct SLAVIO_INTCTLState {
  67     SysBusDevice parent_obj;
  68
  69     MemoryRegion iomem;
  70 #ifdef DEBUG_IRQ_COUNT
  71     uint64_t irq_count[32];
  72 #endif
  73     qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
  74     SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
  75     uint32_t intregm_pending;
  76     uint32_t intregm_disabled;
  77     uint32_t target_cpu;
  78 };
  79
  80 #define INTCTL_MAXADDR 0xf
  81 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  82 #define INTCTLM_SIZE 0x14
  83 #define MASTER_IRQ_MASK ~0x0fa2007f
  84 #define MASTER_DISABLE 0x80000000
  85 #define CPU_SOFTIRQ_MASK 0xfffe0000
  86 #define CPU_IRQ_INT15_IN (1 << 15)
  87 #define CPU_IRQ_TIMER_IN (1 << 14)
  88
  89 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  90
  91 // per-cpu interrupt controller
  92 static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr,
  93                                         unsigned size)
  94 {
  95     SLAVIO_CPUINTCTLState *s = opaque;
  96     uint32_t saddr, ret;
  97
  98     saddr = addr >> 2;
  99     switch (saddr) {
 100     case 0:
 101         ret = s->intreg_pending;
 102         break;
 103     default:
 104         ret = 0;
 105         break;
 106     }
 107     trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
 108
 109     return ret;
 110 }
 111
 112 static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
 113                                      uint64_t val, unsigned size)
 114 {
 115     SLAVIO_CPUINTCTLState *s = opaque;
 116     uint32_t saddr;
 117
 118     saddr = addr >> 2;
 119     trace_slavio_intctl_mem_writel(s->cpu, addr, val);
 120     switch (saddr) {
 121     case 1: // clear pending softints
 122         val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
 123         s->intreg_pending &= ~val;
 124         slavio_check_interrupts(s->master, 1);
 125         trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending);
 126         break;
 127     case 2: // set softint
 128         val &= CPU_SOFTIRQ_MASK;
 129         s->intreg_pending |= val;
 130         slavio_check_interrupts(s->master, 1);
 131         trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending);
 132         break;
 133     default:
 134         break;
 135     }
 136 }
 137
 138 static const MemoryRegionOps slavio_intctl_mem_ops = {
 139     .read = slavio_intctl_mem_readl,
 140     .write = slavio_intctl_mem_writel,
 141     .endianness = DEVICE_NATIVE_ENDIAN,
 142     .valid = {
 143         .min_access_size = 4,
 144         .max_access_size = 4,
 145     },
 146 };
 147
 148 // master system interrupt controller
 149 static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr,
 150                                          unsigned size)
 151 {
 152     SLAVIO_INTCTLState *s = opaque;
 153     uint32_t saddr, ret;
 154
 155     saddr = addr >> 2;
 156     switch (saddr) {
 157     case 0:
 158         ret = s->intregm_pending & ~MASTER_DISABLE;
 159         break;
 160     case 1:
 161         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 162         break;
 163     case 4:
 164         ret = s->target_cpu;
 165         break;
 166     default:
 167         ret = 0;
 168         break;
 169     }
 170     trace_slavio_intctlm_mem_readl(addr, ret);
 171
 172     return ret;
 173 }
 174
 175 static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
 176                                       uint64_t val, unsigned size)
 177 {
 178     SLAVIO_INTCTLState *s = opaque;
 179     uint32_t saddr;
 180
 181     saddr = addr >> 2;
 182     trace_slavio_intctlm_mem_writel(addr, val);
 183     switch (saddr) {
 184     case 2: // clear (enable)
 185         // Force clear unused bits
 186         val &= MASTER_IRQ_MASK;
 187         s->intregm_disabled &= ~val;
 188         trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled);
 189         slavio_check_interrupts(s, 1);
 190         break;
 191     case 3: // set (disable; doesn't affect pending)
 192         // Force clear unused bits
 193         val &= MASTER_IRQ_MASK;
 194         s->intregm_disabled |= val;
 195         slavio_check_interrupts(s, 1);
 196         trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled);
 197         break;
 198     case 4:
 199         s->target_cpu = val & (MAX_CPUS - 1);
 200         slavio_check_interrupts(s, 1);
 201         trace_slavio_intctlm_mem_writel_target(s->target_cpu);
 202         break;
 203     default:
 204         break;
 205     }
 206 }
 207
 208 static const MemoryRegionOps slavio_intctlm_mem_ops = {
 209     .read = slavio_intctlm_mem_readl,
 210     .write = slavio_intctlm_mem_writel,
 211     .endianness = DEVICE_NATIVE_ENDIAN,
 212     .valid = {
 213         .min_access_size = 4,
 214         .max_access_size = 4,
 215     },
 216 };
 217
 218 static const uint32_t intbit_to_level[] = {
 219     2, 3, 5, 7, 9, 11, 13, 2,   3, 5, 7, 9, 11, 13, 12, 12,
 220     6, 13, 4, 10, 8, 9, 11, 0,  0, 0, 0, 15, 15, 15, 15, 0,
 221 };
 222
 223 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 224 {
 225     uint32_t pending = s->intregm_pending, pil_pending;
 226     unsigned int i, j;
 227
 228     pending &= ~s->intregm_disabled;
 229
 230     trace_slavio_check_interrupts(pending, s->intregm_disabled);
 231     for (i = 0; i < MAX_CPUS; i++) {
 232         pil_pending = 0;
 233
 234         /* If we are the current interrupt target, get hard interrupts */
 235         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 236             (i == s->target_cpu)) {
 237             for (j = 0; j < 32; j++) {
 238                 if ((pending & (1 << j)) && intbit_to_level[j]) {
 239                     pil_pending |= 1 << intbit_to_level[j];
 240                 }
 241             }
 242         }
 243
 244         /* Calculate current pending hard interrupts for display */
 245         s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
 246             CPU_IRQ_TIMER_IN;
 247         if (i == s->target_cpu) {
 248             for (j = 0; j < 32; j++) {
 249                 if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) {
 250                     s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
 251                 }
 252             }
 253         }
 254
 255         /* Level 15 and CPU timer interrupts are only masked when
 256            the MASTER_DISABLE bit is set */
 257         if (!(s->intregm_disabled & MASTER_DISABLE)) {
 258             pil_pending |= s->slaves[i].intreg_pending &
 259                 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
 260         }
 261
 262         /* Add soft interrupts */
 263         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 264
 265         if (set_irqs) {
 266             /* Since there is not really an interrupt 0 (and pil_pending
 267              * and irl_out bit zero are thus always zero) there is no need
 268              * to do anything with cpu_irqs[i][0] and it is OK not to do
 269              * the j=0 iteration of this loop.
 270              */
 271             for (j = MAX_PILS-1; j > 0; j--) {
 272                 if (pil_pending & (1 << j)) {
 273                     if (!(s->slaves[i].irl_out & (1 << j))) {
 274                         qemu_irq_raise(s->cpu_irqs[i][j]);
 275                     }
 276                 } else {
 277                     if (s->slaves[i].irl_out & (1 << j)) {
 278                         qemu_irq_lower(s->cpu_irqs[i][j]);
 279                     }
 280                 }
 281             }
 282         }
 283         s->slaves[i].irl_out = pil_pending;
 284     }
 285 }
 286
 287 /*
 288  * "irq" here is the bit number in the system interrupt register to
 289  * separate serial and keyboard interrupts sharing a level.
 290  */
 291 static void slavio_set_irq(void *opaque, int irq, int level)
 292 {
 293     SLAVIO_INTCTLState *s = opaque;
 294     uint32_t mask = 1 << irq;
 295     uint32_t pil = intbit_to_level[irq];
 296     unsigned int i;
 297
 298     trace_slavio_set_irq(s->target_cpu, irq, pil, level);
 299     if (pil > 0) {
 300         if (level) {
 301 #ifdef DEBUG_IRQ_COUNT
 302             s->irq_count[pil]++;
 303 #endif
 304             s->intregm_pending |= mask;
 305             if (pil == 15) {
 306                 for (i = 0; i < MAX_CPUS; i++) {
 307                     s->slaves[i].intreg_pending |= 1 << pil;
 308                 }
 309             }
 310         } else {
 311             s->intregm_pending &= ~mask;
 312             if (pil == 15) {
 313                 for (i = 0; i < MAX_CPUS; i++) {
 314                     s->slaves[i].intreg_pending &= ~(1 << pil);
 315                 }
 316             }
 317         }
 318         slavio_check_interrupts(s, 1);
 319     }
 320 }
 321
 322 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 323 {
 324     SLAVIO_INTCTLState *s = opaque;
 325
 326     trace_slavio_set_timer_irq_cpu(cpu, level);
 327
 328     if (level) {
 329         s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
 330     } else {
 331         s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
 332     }
 333
 334     slavio_check_interrupts(s, 1);
 335 }
 336
 337 static void slavio_set_irq_all(void *opaque, int irq, int level)
 338 {
 339     if (irq < 32) {
 340         slavio_set_irq(opaque, irq, level);
 341     } else {
 342         slavio_set_timer_irq_cpu(opaque, irq - 32, level);
 343     }
 344 }
 345
 346 static int vmstate_intctl_post_load(void *opaque, int version_id)
 347 {
 348     SLAVIO_INTCTLState *s = opaque;
 349
 350     slavio_check_interrupts(s, 0);
 351     return 0;
 352 }
 353
 354 static const VMStateDescription vmstate_intctl_cpu = {
 355     .name ="slavio_intctl_cpu",
 356     .version_id = 1,
 357     .minimum_version_id = 1,
 358     .fields = (VMStateField[]) {
 359         VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
 360         VMSTATE_END_OF_LIST()
 361     }
 362 };
 363
 364 static const VMStateDescription vmstate_intctl = {
 365     .name ="slavio_intctl",
 366     .version_id = 1,
 367     .minimum_version_id = 1,
 368     .post_load = vmstate_intctl_post_load,
 369     .fields = (VMStateField[]) {
 370         VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
 371                              vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
 372         VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
 373         VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
 374         VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
 375         VMSTATE_END_OF_LIST()
 376     }
 377 };
 378
 379 static void slavio_intctl_reset(DeviceState *d)
 380 {
 381     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(d);
 382     int i;
 383
 384     for (i = 0; i < MAX_CPUS; i++) {
 385         s->slaves[i].intreg_pending = 0;
 386         s->slaves[i].irl_out = 0;
 387     }
 388     s->intregm_disabled = ~MASTER_IRQ_MASK;
 389     s->intregm_pending = 0;
 390     s->target_cpu = 0;
 391     slavio_check_interrupts(s, 0);
 392 }
 393
 394 #ifdef DEBUG_IRQ_COUNT
 395 static bool slavio_intctl_get_statistics(InterruptStatsProvider *obj,
 396                                          uint64_t **irq_counts,
 397                                          unsigned int *nb_irqs)
 398 {
 399     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 400     *irq_counts = s->irq_count;
 401     *nb_irqs = ARRAY_SIZE(s->irq_count);
 402     return true;
 403 }
 404 #endif
 405
 406 static void slavio_intctl_print_info(InterruptStatsProvider *obj, Monitor *mon)
 407 {
 408     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 409     int i;
 410
 411     for (i = 0; i < MAX_CPUS; i++) {
 412         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 413                        s->slaves[i].intreg_pending);
 414     }
 415     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 416                    s->intregm_pending, s->intregm_disabled);
 417 }
 418
 419 static void slavio_intctl_init(Object *obj)
 420 {
 421     DeviceState *dev = DEVICE(obj);
 422     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 423     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 424     unsigned int i, j;
 425     char slave_name[45];
 426
 427     qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS);
 428     memory_region_init_io(&s->iomem, obj, &slavio_intctlm_mem_ops, s,
 429                           "master-interrupt-controller", INTCTLM_SIZE);
 430     sysbus_init_mmio(sbd, &s->iomem);
 431
 432     for (i = 0; i < MAX_CPUS; i++) {
 433         snprintf(slave_name, sizeof(slave_name),
 434                  "slave-interrupt-controller-%i", i);
 435         for (j = 0; j < MAX_PILS; j++) {
 436             sysbus_init_irq(sbd, &s->cpu_irqs[i][j]);
 437         }
 438         memory_region_init_io(&s->slaves[i].iomem, OBJECT(s),
 439                               &slavio_intctl_mem_ops,
 440                               &s->slaves[i], slave_name, INTCTL_SIZE);
 441         sysbus_init_mmio(sbd, &s->slaves[i].iomem);
 442         s->slaves[i].cpu = i;
 443         s->slaves[i].master = s;
 444     }
 445 }
 446
 447 static void slavio_intctl_class_init(ObjectClass *klass, void *data)
 448 {
 449     DeviceClass *dc = DEVICE_CLASS(klass);
 450     InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 451
 452     dc->reset = slavio_intctl_reset;
 453     dc->vmsd = &vmstate_intctl;
 454 #ifdef DEBUG_IRQ_COUNT
 455     ic->get_statistics = slavio_intctl_get_statistics;
 456 #endif
 457     ic->print_info = slavio_intctl_print_info;
 458 }
 459
 460 static const TypeInfo slavio_intctl_info = {
 461     .name          = TYPE_SLAVIO_INTCTL,
 462     .parent        = TYPE_SYS_BUS_DEVICE,
 463     .instance_size = sizeof(SLAVIO_INTCTLState),
 464     .instance_init = slavio_intctl_init,
 465     .class_init    = slavio_intctl_class_init,
 466     .interfaces = (InterfaceInfo[]) {
 467         { TYPE_INTERRUPT_STATS_PROVIDER },
 468         { }
 469     },
 470 };
 471
 472 static void slavio_intctl_register_types(void)
 473 {
 474     type_register_static(&slavio_intctl_info);
 475 }
 476
 477 type_init(slavio_intctl_register_types)