hw/char/milkymist-uart.c

   1 /*
   2  *  QEMU model of the Milkymist UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/uart.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/qdev-properties.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "trace.h"
  30 #include "chardev/char-fe.h"
  31 #include "qemu/error-report.h"
  32 #include "qemu/module.h"
  33 #include "qom/object.h"
  34
  35 enum {
  36     R_RXTX = 0,
  37     R_DIV,
  38     R_STAT,
  39     R_CTRL,
  40     R_DBG,
  41     R_MAX
  42 };
  43
  44 enum {
  45     STAT_THRE   = (1<<0),
  46     STAT_RX_EVT = (1<<1),
  47     STAT_TX_EVT = (1<<2),
  48 };
  49
  50 enum {
  51     CTRL_RX_IRQ_EN = (1<<0),
  52     CTRL_TX_IRQ_EN = (1<<1),
  53     CTRL_THRU_EN   = (1<<2),
  54 };
  55
  56 enum {
  57     DBG_BREAK_EN = (1<<0),
  58 };
  59
  60 #define TYPE_MILKYMIST_UART "milkymist-uart"
  61 typedef struct MilkymistUartState MilkymistUartState;
  62 DECLARE_INSTANCE_CHECKER(MilkymistUartState, MILKYMIST_UART,
  63                          TYPE_MILKYMIST_UART)
  64
  65 struct MilkymistUartState {
  66     SysBusDevice parent_obj;
  67
  68     MemoryRegion regs_region;
  69     CharBackend chr;
  70     qemu_irq irq;
  71
  72     uint32_t regs[R_MAX];
  73 };
  74
  75 static void uart_update_irq(MilkymistUartState *s)
  76 {
  77     int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
  78     int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
  79     int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
  80     int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
  81
  82     if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
  83         trace_milkymist_uart_raise_irq();
  84         qemu_irq_raise(s->irq);
  85     } else {
  86         trace_milkymist_uart_lower_irq();
  87         qemu_irq_lower(s->irq);
  88     }
  89 }
  90
  91 static uint64_t uart_read(void *opaque, hwaddr addr,
  92                           unsigned size)
  93 {
  94     MilkymistUartState *s = opaque;
  95     uint32_t r = 0;
  96
  97     addr >>= 2;
  98     switch (addr) {
  99     case R_RXTX:
 100         r = s->regs[addr];
 101         break;
 102     case R_DIV:
 103     case R_STAT:
 104     case R_CTRL:
 105     case R_DBG:
 106         r = s->regs[addr];
 107         break;
 108
 109     default:
 110         error_report("milkymist_uart: read access to unknown register 0x"
 111                 TARGET_FMT_plx, addr << 2);
 112         break;
 113     }
 114
 115     trace_milkymist_uart_memory_read(addr << 2, r);
 116
 117     return r;
 118 }
 119
 120 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
 121                        unsigned size)
 122 {
 123     MilkymistUartState *s = opaque;
 124     unsigned char ch = value;
 125
 126     trace_milkymist_uart_memory_write(addr, value);
 127
 128     addr >>= 2;
 129     switch (addr) {
 130     case R_RXTX:
 131         qemu_chr_fe_write_all(&s->chr, &ch, 1);
 132         s->regs[R_STAT] |= STAT_TX_EVT;
 133         break;
 134     case R_DIV:
 135     case R_CTRL:
 136     case R_DBG:
 137         s->regs[addr] = value;
 138         break;
 139
 140     case R_STAT:
 141         /* write one to clear bits */
 142         s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
 143         qemu_chr_fe_accept_input(&s->chr);
 144         break;
 145
 146     default:
 147         error_report("milkymist_uart: write access to unknown register 0x"
 148                 TARGET_FMT_plx, addr << 2);
 149         break;
 150     }
 151
 152     uart_update_irq(s);
 153 }
 154
 155 static const MemoryRegionOps uart_mmio_ops = {
 156     .read = uart_read,
 157     .write = uart_write,
 158     .valid = {
 159         .min_access_size = 4,
 160         .max_access_size = 4,
 161     },
 162     .endianness = DEVICE_NATIVE_ENDIAN,
 163 };
 164
 165 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 166 {
 167     MilkymistUartState *s = opaque;
 168
 169     assert(!(s->regs[R_STAT] & STAT_RX_EVT));
 170
 171     s->regs[R_STAT] |= STAT_RX_EVT;
 172     s->regs[R_RXTX] = *buf;
 173
 174     uart_update_irq(s);
 175 }
 176
 177 static int uart_can_rx(void *opaque)
 178 {
 179     MilkymistUartState *s = opaque;
 180
 181     return !(s->regs[R_STAT] & STAT_RX_EVT);
 182 }
 183
 184 static void uart_event(void *opaque, QEMUChrEvent event)
 185 {
 186 }
 187
 188 static void milkymist_uart_reset(DeviceState *d)
 189 {
 190     MilkymistUartState *s = MILKYMIST_UART(d);
 191     int i;
 192
 193     for (i = 0; i < R_MAX; i++) {
 194         s->regs[i] = 0;
 195     }
 196
 197     /* THRE is always set */
 198     s->regs[R_STAT] = STAT_THRE;
 199 }
 200
 201 static void milkymist_uart_realize(DeviceState *dev, Error **errp)
 202 {
 203     MilkymistUartState *s = MILKYMIST_UART(dev);
 204
 205     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 206                              uart_event, NULL, s, NULL, true);
 207 }
 208
 209 static void milkymist_uart_init(Object *obj)
 210 {
 211     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 212     MilkymistUartState *s = MILKYMIST_UART(obj);
 213
 214     sysbus_init_irq(sbd, &s->irq);
 215
 216     memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 217                           "milkymist-uart", R_MAX * 4);
 218     sysbus_init_mmio(sbd, &s->regs_region);
 219 }
 220
 221 static const VMStateDescription vmstate_milkymist_uart = {
 222     .name = "milkymist-uart",
 223     .version_id = 1,
 224     .minimum_version_id = 1,
 225     .fields = (VMStateField[]) {
 226         VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
 227         VMSTATE_END_OF_LIST()
 228     }
 229 };
 230
 231 static Property milkymist_uart_properties[] = {
 232     DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
 233     DEFINE_PROP_END_OF_LIST(),
 234 };
 235
 236 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
 237 {
 238     DeviceClass *dc = DEVICE_CLASS(klass);
 239
 240     dc->realize = milkymist_uart_realize;
 241     dc->reset = milkymist_uart_reset;
 242     dc->vmsd = &vmstate_milkymist_uart;
 243     device_class_set_props(dc, milkymist_uart_properties);
 244 }
 245
 246 static const TypeInfo milkymist_uart_info = {
 247     .name          = TYPE_MILKYMIST_UART,
 248     .parent        = TYPE_SYS_BUS_DEVICE,
 249     .instance_size = sizeof(MilkymistUartState),
 250     .instance_init = milkymist_uart_init,
 251     .class_init    = milkymist_uart_class_init,
 252 };
 253
 254 static void milkymist_uart_register_types(void)
 255 {
 256     type_register_static(&milkymist_uart_info);
 257 }
 258
 259 type_init(milkymist_uart_register_types)