hw/i2c/smbus_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6  *               VA Linux Systems Japan K.K.
   7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, see <http://www.gnu.org/licenses/>
  21  */
  22 #include "qemu/osdep.h"
  23 #include "hw/hw.h"
  24 #include "hw/i2c/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "sysemu/sysemu.h"
  27
  28 #include "hw/i386/ich9.h"
  29
  30 #define ICH9_SMB_DEVICE(obj) \
  31      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
  32
  33 typedef struct ICH9SMBState {
  34     PCIDevice dev;
  35
  36     bool irq_enabled;
  37
  38     PMSMBus smb;
  39 } ICH9SMBState;
  40
  41 static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
  42 {
  43     return pm_smbus_vmstate_needed();
  44 }
  45
  46 static const VMStateDescription vmstate_ich9_smbus = {
  47     .name = "ich9_smb",
  48     .version_id = 1,
  49     .minimum_version_id = 1,
  50     .fields = (VMStateField[]) {
  51         VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
  52         VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
  53         VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
  54                             pmsmb_vmstate, PMSMBus),
  55         VMSTATE_END_OF_LIST()
  56     }
  57 };
  58
  59 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
  60                                     uint32_t val, int len)
  61 {
  62     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  63
  64     pci_default_write_config(d, address, val, len);
  65     if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
  66         uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
  67         if (hostc & ICH9_SMB_HOSTC_HST_EN) {
  68             memory_region_set_enabled(&s->smb.io, true);
  69         } else {
  70             memory_region_set_enabled(&s->smb.io, false);
  71         }
  72         s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
  73         if (hostc & ICH9_SMB_HOSTC_SSRESET) {
  74             s->smb.reset(&s->smb);
  75             s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
  76         }
  77     }
  78 }
  79
  80 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
  81 {
  82     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  83
  84     /* TODO? D31IP.SMIP in chipset configuration space */
  85     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
  86
  87     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
  88     /* TODO bar0, bar1: 64bit BAR support*/
  89
  90     pm_smbus_init(&d->qdev, &s->smb, false);
  91     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
  92                      &s->smb.io);
  93 }
  94
  95 static void ich9_smb_class_init(ObjectClass *klass, void *data)
  96 {
  97     DeviceClass *dc = DEVICE_CLASS(klass);
  98     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  99
 100     k->vendor_id = PCI_VENDOR_ID_INTEL;
 101     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
 102     k->revision = ICH9_A2_SMB_REVISION;
 103     k->class_id = PCI_CLASS_SERIAL_SMBUS;
 104     dc->vmsd = &vmstate_ich9_smbus;
 105     dc->desc = "ICH9 SMBUS Bridge";
 106     k->realize = ich9_smbus_realize;
 107     k->config_write = ich9_smbus_write_config;
 108     /*
 109      * Reason: part of ICH9 southbridge, needs to be wired up by
 110      * pc_q35_init()
 111      */
 112     dc->user_creatable = false;
 113 }
 114
 115 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
 116 {
 117     ICH9SMBState *s = pmsmb->opaque;
 118
 119     if (enabled == s->irq_enabled) {
 120         return;
 121     }
 122
 123     s->irq_enabled = enabled;
 124     pci_set_irq(&s->dev, enabled);
 125 }
 126
 127 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
 128 {
 129     PCIDevice *d =
 130         pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
 131     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
 132     s->smb.set_irq = ich9_smb_set_irq;
 133     s->smb.opaque = s;
 134     return s->smb.smbus;
 135 }
 136
 137 static const TypeInfo ich9_smb_info = {
 138     .name   = TYPE_ICH9_SMB_DEVICE,
 139     .parent = TYPE_PCI_DEVICE,
 140     .instance_size = sizeof(ICH9SMBState),
 141     .class_init = ich9_smb_class_init,
 142     .interfaces = (InterfaceInfo[]) {
 143         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 144         { },
 145     },
 146 };
 147
 148 static void ich9_smb_register(void)
 149 {
 150     type_register_static(&ich9_smb_info);
 151 }
 152
 153 type_init(ich9_smb_register);