4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
31 #include "hyperv-proto.h"
33 #include "exec/gdbstub.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "hw/i386/pc.h"
39 #include "hw/i386/apic.h"
40 #include "hw/i386/apic_internal.h"
41 #include "hw/i386/apic-msidef.h"
42 #include "hw/i386/intel_iommu.h"
43 #include "hw/i386/x86-iommu.h"
44 #include "hw/i386/e820_memory_layout.h"
46 #include "hw/pci/pci.h"
47 #include "hw/pci/msi.h"
48 #include "hw/pci/msix.h"
49 #include "migration/blocker.h"
50 #include "exec/memattrs.h"
56 #define DPRINTF(fmt, ...) \
57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
59 #define DPRINTF(fmt, ...) \
63 #define MSR_KVM_WALL_CLOCK 0x11
64 #define MSR_KVM_SYSTEM_TIME 0x12
66 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
67 * 255 kvm_msr_entry structs */
68 #define MSR_BUF_SIZE 4096
70 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR
),
72 KVM_CAP_INFO(EXT_CPUID
),
73 KVM_CAP_INFO(MP_STATE
),
77 static bool has_msr_star
;
78 static bool has_msr_hsave_pa
;
79 static bool has_msr_tsc_aux
;
80 static bool has_msr_tsc_adjust
;
81 static bool has_msr_tsc_deadline
;
82 static bool has_msr_feature_control
;
83 static bool has_msr_misc_enable
;
84 static bool has_msr_smbase
;
85 static bool has_msr_bndcfgs
;
86 static int lm_capable_kernel
;
87 static bool has_msr_hv_hypercall
;
88 static bool has_msr_hv_crash
;
89 static bool has_msr_hv_reset
;
90 static bool has_msr_hv_vpindex
;
91 static bool hv_vpindex_settable
;
92 static bool has_msr_hv_runtime
;
93 static bool has_msr_hv_synic
;
94 static bool has_msr_hv_stimer
;
95 static bool has_msr_hv_frequencies
;
96 static bool has_msr_hv_reenlightenment
;
97 static bool has_msr_xss
;
98 static bool has_msr_spec_ctrl
;
99 static bool has_msr_virt_ssbd
;
100 static bool has_msr_smi_count
;
101 static bool has_msr_arch_capabs
;
102 static bool has_msr_core_capabs
;
103 static bool has_msr_vmx_vmfunc
;
105 static uint32_t has_architectural_pmu_version
;
106 static uint32_t num_architectural_pmu_gp_counters
;
107 static uint32_t num_architectural_pmu_fixed_counters
;
109 static int has_xsave
;
111 static int has_pit_state2
;
112 static int has_exception_payload
;
114 static bool has_msr_mcg_ext_ctl
;
116 static struct kvm_cpuid2
*cpuid_cache
;
117 static struct kvm_msr_list
*kvm_feature_msrs
;
119 int kvm_has_pit_state2(void)
121 return has_pit_state2
;
124 bool kvm_has_smm(void)
126 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
129 bool kvm_has_adjust_clock_stable(void)
131 int ret
= kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
);
133 return (ret
== KVM_CLOCK_TSC_STABLE
);
136 bool kvm_has_exception_payload(void)
138 return has_exception_payload
;
141 bool kvm_allows_irq0_override(void)
143 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
146 static bool kvm_x2apic_api_set_flags(uint64_t flags
)
148 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
150 return !kvm_vm_enable_cap(s
, KVM_CAP_X2APIC_API
, 0, flags
);
153 #define MEMORIZE(fn, _result) \
155 static bool _memorized; \
164 static bool has_x2apic_api
;
166 bool kvm_has_x2apic_api(void)
168 return has_x2apic_api
;
171 bool kvm_enable_x2apic(void)
174 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS
|
175 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK
),
179 bool kvm_hv_vpindex_settable(void)
181 return hv_vpindex_settable
;
184 static int kvm_get_tsc(CPUState
*cs
)
186 X86CPU
*cpu
= X86_CPU(cs
);
187 CPUX86State
*env
= &cpu
->env
;
189 struct kvm_msrs info
;
190 struct kvm_msr_entry entries
[1];
194 if (env
->tsc_valid
) {
198 memset(&msr_data
, 0, sizeof(msr_data
));
199 msr_data
.info
.nmsrs
= 1;
200 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
201 env
->tsc_valid
= !runstate_is_running();
203 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
209 env
->tsc
= msr_data
.entries
[0].data
;
213 static inline void do_kvm_synchronize_tsc(CPUState
*cpu
, run_on_cpu_data arg
)
218 void kvm_synchronize_all_tsc(void)
224 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, RUN_ON_CPU_NULL
);
229 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
231 struct kvm_cpuid2
*cpuid
;
234 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
235 cpuid
= g_malloc0(size
);
237 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
238 if (r
== 0 && cpuid
->nent
>= max
) {
246 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
254 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
257 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
259 struct kvm_cpuid2
*cpuid
;
262 if (cpuid_cache
!= NULL
) {
265 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
272 static const struct kvm_para_features
{
275 } para_features
[] = {
276 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
277 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
278 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
279 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
282 static int get_para_features(KVMState
*s
)
286 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
287 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
288 features
|= (1 << para_features
[i
].feature
);
295 static bool host_tsx_blacklisted(void)
297 int family
, model
, stepping
;\
298 char vendor
[CPUID_VENDOR_SZ
+ 1];
300 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
302 /* Check if we are running on a Haswell host known to have broken TSX */
303 return !strcmp(vendor
, CPUID_VENDOR_INTEL
) &&
305 ((model
== 63 && stepping
< 4) ||
306 model
== 60 || model
== 69 || model
== 70);
309 /* Returns the value for a specific register on the cpuid entry
311 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
331 /* Find matching entry for function/index on kvm_cpuid2 struct
333 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
338 for (i
= 0; i
< cpuid
->nent
; ++i
) {
339 if (cpuid
->entries
[i
].function
== function
&&
340 cpuid
->entries
[i
].index
== index
) {
341 return &cpuid
->entries
[i
];
348 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
349 uint32_t index
, int reg
)
351 struct kvm_cpuid2
*cpuid
;
353 uint32_t cpuid_1_edx
;
356 cpuid
= get_supported_cpuid(s
);
358 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
361 ret
= cpuid_entry_get_reg(entry
, reg
);
364 /* Fixups for the data returned by KVM, below */
366 if (function
== 1 && reg
== R_EDX
) {
367 /* KVM before 2.6.30 misreports the following features */
368 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
369 } else if (function
== 1 && reg
== R_ECX
) {
370 /* We can set the hypervisor flag, even if KVM does not return it on
371 * GET_SUPPORTED_CPUID
373 ret
|= CPUID_EXT_HYPERVISOR
;
374 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
375 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
376 * and the irqchip is in the kernel.
378 if (kvm_irqchip_in_kernel() &&
379 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
380 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
383 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
384 * without the in-kernel irqchip
386 if (!kvm_irqchip_in_kernel()) {
387 ret
&= ~CPUID_EXT_X2APIC
;
391 int disable_exits
= kvm_check_extension(s
,
392 KVM_CAP_X86_DISABLE_EXITS
);
394 if (disable_exits
& KVM_X86_DISABLE_EXITS_MWAIT
) {
395 ret
|= CPUID_EXT_MONITOR
;
398 } else if (function
== 6 && reg
== R_EAX
) {
399 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
400 } else if (function
== 7 && index
== 0 && reg
== R_EBX
) {
401 if (host_tsx_blacklisted()) {
402 ret
&= ~(CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_HLE
);
404 } else if (function
== 7 && index
== 0 && reg
== R_EDX
) {
406 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
407 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
408 * returned by KVM_GET_MSR_INDEX_LIST.
410 if (!has_msr_arch_capabs
) {
411 ret
&= ~CPUID_7_0_EDX_ARCH_CAPABILITIES
;
413 } else if (function
== 0x80000001 && reg
== R_ECX
) {
415 * It's safe to enable TOPOEXT even if it's not returned by
416 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
417 * us to keep CPU models including TOPOEXT runnable on older kernels.
419 ret
|= CPUID_EXT3_TOPOEXT
;
420 } else if (function
== 0x80000001 && reg
== R_EDX
) {
421 /* On Intel, kvm returns cpuid according to the Intel spec,
422 * so add missing bits according to the AMD spec:
424 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
425 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
426 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EAX
) {
427 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
428 * be enabled without the in-kernel irqchip
430 if (!kvm_irqchip_in_kernel()) {
431 ret
&= ~(1U << KVM_FEATURE_PV_UNHALT
);
433 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EDX
) {
434 ret
|= 1U << KVM_HINTS_REALTIME
;
438 /* fallback for older kernels */
439 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
440 ret
= get_para_features(s
);
446 uint64_t kvm_arch_get_supported_msr_feature(KVMState
*s
, uint32_t index
)
449 struct kvm_msrs info
;
450 struct kvm_msr_entry entries
[1];
453 uint32_t ret
, can_be_one
, must_be_one
;
455 if (kvm_feature_msrs
== NULL
) { /* Host doesn't support feature MSRs */
459 /* Check if requested MSR is supported feature MSR */
461 for (i
= 0; i
< kvm_feature_msrs
->nmsrs
; i
++)
462 if (kvm_feature_msrs
->indices
[i
] == index
) {
465 if (i
== kvm_feature_msrs
->nmsrs
) {
466 return 0; /* if the feature MSR is not supported, simply return 0 */
469 msr_data
.info
.nmsrs
= 1;
470 msr_data
.entries
[0].index
= index
;
472 ret
= kvm_ioctl(s
, KVM_GET_MSRS
, &msr_data
);
474 error_report("KVM get MSR (index=0x%x) feature failed, %s",
475 index
, strerror(-ret
));
479 value
= msr_data
.entries
[0].data
;
481 case MSR_IA32_VMX_PROCBASED_CTLS2
:
482 /* KVM forgot to add these bits for some time, do this ourselves. */
483 if (kvm_arch_get_supported_cpuid(s
, 0xD, 1, R_ECX
) & CPUID_XSAVE_XSAVES
) {
484 value
|= (uint64_t)VMX_SECONDARY_EXEC_XSAVES
<< 32;
486 if (kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
) & CPUID_EXT_RDRAND
) {
487 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING
<< 32;
489 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) & CPUID_7_0_EBX_INVPCID
) {
490 value
|= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID
<< 32;
492 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) & CPUID_7_0_EBX_RDSEED
) {
493 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING
<< 32;
495 if (kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
) & CPUID_EXT2_RDTSCP
) {
496 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP
<< 32;
499 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
500 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
501 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
502 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
504 * Return true for bits that can be one, but do not have to be one.
505 * The SDM tells us which bits could have a "must be one" setting,
506 * so we can do the opposite transformation in make_vmx_msr_value.
508 must_be_one
= (uint32_t)value
;
509 can_be_one
= (uint32_t)(value
>> 32);
510 return can_be_one
& ~must_be_one
;
518 typedef struct HWPoisonPage
{
520 QLIST_ENTRY(HWPoisonPage
) list
;
523 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
524 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
526 static void kvm_unpoison_all(void *param
)
528 HWPoisonPage
*page
, *next_page
;
530 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
531 QLIST_REMOVE(page
, list
);
532 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
537 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
541 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
542 if (page
->ram_addr
== ram_addr
) {
546 page
= g_new(HWPoisonPage
, 1);
547 page
->ram_addr
= ram_addr
;
548 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
551 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
556 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
559 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
564 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
566 CPUState
*cs
= CPU(cpu
);
567 CPUX86State
*env
= &cpu
->env
;
568 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
569 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
570 uint64_t mcg_status
= MCG_STATUS_MCIP
;
573 if (code
== BUS_MCEERR_AR
) {
574 status
|= MCI_STATUS_AR
| 0x134;
575 mcg_status
|= MCG_STATUS_EIPV
;
578 mcg_status
|= MCG_STATUS_RIPV
;
581 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
582 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
583 * guest kernel back into env->mcg_ext_ctl.
585 cpu_synchronize_state(cs
);
586 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
587 mcg_status
|= MCG_STATUS_LMCE
;
591 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
592 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
595 static void hardware_memory_error(void)
597 fprintf(stderr
, "Hardware memory error!\n");
601 void kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
603 X86CPU
*cpu
= X86_CPU(c
);
604 CPUX86State
*env
= &cpu
->env
;
608 /* If we get an action required MCE, it has been injected by KVM
609 * while the VM was running. An action optional MCE instead should
610 * be coming from the main thread, which qemu_init_sigbus identifies
611 * as the "early kill" thread.
613 assert(code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
);
615 if ((env
->mcg_cap
& MCG_SER_P
) && addr
) {
616 ram_addr
= qemu_ram_addr_from_host(addr
);
617 if (ram_addr
!= RAM_ADDR_INVALID
&&
618 kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
619 kvm_hwpoison_page_add(ram_addr
);
620 kvm_mce_inject(cpu
, paddr
, code
);
624 fprintf(stderr
, "Hardware memory error for memory used by "
625 "QEMU itself instead of guest system!\n");
628 if (code
== BUS_MCEERR_AR
) {
629 hardware_memory_error();
632 /* Hope we are lucky for AO MCE */
635 static void kvm_reset_exception(CPUX86State
*env
)
637 env
->exception_nr
= -1;
638 env
->exception_pending
= 0;
639 env
->exception_injected
= 0;
640 env
->exception_has_payload
= false;
641 env
->exception_payload
= 0;
644 static void kvm_queue_exception(CPUX86State
*env
,
645 int32_t exception_nr
,
646 uint8_t exception_has_payload
,
647 uint64_t exception_payload
)
649 assert(env
->exception_nr
== -1);
650 assert(!env
->exception_pending
);
651 assert(!env
->exception_injected
);
652 assert(!env
->exception_has_payload
);
654 env
->exception_nr
= exception_nr
;
656 if (has_exception_payload
) {
657 env
->exception_pending
= 1;
659 env
->exception_has_payload
= exception_has_payload
;
660 env
->exception_payload
= exception_payload
;
662 env
->exception_injected
= 1;
664 if (exception_nr
== EXCP01_DB
) {
665 assert(exception_has_payload
);
666 env
->dr
[6] = exception_payload
;
667 } else if (exception_nr
== EXCP0E_PAGE
) {
668 assert(exception_has_payload
);
669 env
->cr
[2] = exception_payload
;
671 assert(!exception_has_payload
);
676 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
678 CPUX86State
*env
= &cpu
->env
;
680 if (!kvm_has_vcpu_events() && env
->exception_nr
== EXCP12_MCHK
) {
681 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
682 struct kvm_x86_mce mce
;
684 kvm_reset_exception(env
);
687 * There must be at least one bank in use if an MCE is pending.
688 * Find it and use its values for the event injection.
690 for (bank
= 0; bank
< bank_num
; bank
++) {
691 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
695 assert(bank
< bank_num
);
698 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
699 mce
.mcg_status
= env
->mcg_status
;
700 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
701 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
703 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
708 static void cpu_update_state(void *opaque
, int running
, RunState state
)
710 CPUX86State
*env
= opaque
;
713 env
->tsc_valid
= false;
717 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
719 X86CPU
*cpu
= X86_CPU(cs
);
723 #ifndef KVM_CPUID_SIGNATURE_NEXT
724 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
727 static bool hyperv_enabled(X86CPU
*cpu
)
729 CPUState
*cs
= CPU(cpu
);
730 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
731 ((cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) ||
732 cpu
->hyperv_features
|| cpu
->hyperv_passthrough
);
735 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
737 X86CPU
*cpu
= X86_CPU(cs
);
738 CPUX86State
*env
= &cpu
->env
;
745 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
746 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
749 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
750 * TSC frequency doesn't match the one we want.
752 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
753 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
755 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
756 warn_report("TSC frequency mismatch between "
757 "VM (%" PRId64
" kHz) and host (%d kHz), "
758 "and TSC scaling unavailable",
759 env
->tsc_khz
, cur_freq
);
767 static bool tsc_is_stable_and_known(CPUX86State
*env
)
772 return (env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
)
773 || env
->user_tsc_khz
;
782 uint64_t dependencies
;
783 } kvm_hyperv_properties
[] = {
784 [HYPERV_FEAT_RELAXED
] = {
785 .desc
= "relaxed timing (hv-relaxed)",
787 {.fw
= FEAT_HYPERV_EAX
,
788 .bits
= HV_HYPERCALL_AVAILABLE
},
789 {.fw
= FEAT_HV_RECOMM_EAX
,
790 .bits
= HV_RELAXED_TIMING_RECOMMENDED
}
793 [HYPERV_FEAT_VAPIC
] = {
794 .desc
= "virtual APIC (hv-vapic)",
796 {.fw
= FEAT_HYPERV_EAX
,
797 .bits
= HV_HYPERCALL_AVAILABLE
| HV_APIC_ACCESS_AVAILABLE
},
798 {.fw
= FEAT_HV_RECOMM_EAX
,
799 .bits
= HV_APIC_ACCESS_RECOMMENDED
}
802 [HYPERV_FEAT_TIME
] = {
803 .desc
= "clocksources (hv-time)",
805 {.fw
= FEAT_HYPERV_EAX
,
806 .bits
= HV_HYPERCALL_AVAILABLE
| HV_TIME_REF_COUNT_AVAILABLE
|
807 HV_REFERENCE_TSC_AVAILABLE
}
810 [HYPERV_FEAT_CRASH
] = {
811 .desc
= "crash MSRs (hv-crash)",
813 {.fw
= FEAT_HYPERV_EDX
,
814 .bits
= HV_GUEST_CRASH_MSR_AVAILABLE
}
817 [HYPERV_FEAT_RESET
] = {
818 .desc
= "reset MSR (hv-reset)",
820 {.fw
= FEAT_HYPERV_EAX
,
821 .bits
= HV_RESET_AVAILABLE
}
824 [HYPERV_FEAT_VPINDEX
] = {
825 .desc
= "VP_INDEX MSR (hv-vpindex)",
827 {.fw
= FEAT_HYPERV_EAX
,
828 .bits
= HV_VP_INDEX_AVAILABLE
}
831 [HYPERV_FEAT_RUNTIME
] = {
832 .desc
= "VP_RUNTIME MSR (hv-runtime)",
834 {.fw
= FEAT_HYPERV_EAX
,
835 .bits
= HV_VP_RUNTIME_AVAILABLE
}
838 [HYPERV_FEAT_SYNIC
] = {
839 .desc
= "synthetic interrupt controller (hv-synic)",
841 {.fw
= FEAT_HYPERV_EAX
,
842 .bits
= HV_SYNIC_AVAILABLE
}
845 [HYPERV_FEAT_STIMER
] = {
846 .desc
= "synthetic timers (hv-stimer)",
848 {.fw
= FEAT_HYPERV_EAX
,
849 .bits
= HV_SYNTIMERS_AVAILABLE
}
851 .dependencies
= BIT(HYPERV_FEAT_SYNIC
) | BIT(HYPERV_FEAT_TIME
)
853 [HYPERV_FEAT_FREQUENCIES
] = {
854 .desc
= "frequency MSRs (hv-frequencies)",
856 {.fw
= FEAT_HYPERV_EAX
,
857 .bits
= HV_ACCESS_FREQUENCY_MSRS
},
858 {.fw
= FEAT_HYPERV_EDX
,
859 .bits
= HV_FREQUENCY_MSRS_AVAILABLE
}
862 [HYPERV_FEAT_REENLIGHTENMENT
] = {
863 .desc
= "reenlightenment MSRs (hv-reenlightenment)",
865 {.fw
= FEAT_HYPERV_EAX
,
866 .bits
= HV_ACCESS_REENLIGHTENMENTS_CONTROL
}
869 [HYPERV_FEAT_TLBFLUSH
] = {
870 .desc
= "paravirtualized TLB flush (hv-tlbflush)",
872 {.fw
= FEAT_HV_RECOMM_EAX
,
873 .bits
= HV_REMOTE_TLB_FLUSH_RECOMMENDED
|
874 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
876 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
878 [HYPERV_FEAT_EVMCS
] = {
879 .desc
= "enlightened VMCS (hv-evmcs)",
881 {.fw
= FEAT_HV_RECOMM_EAX
,
882 .bits
= HV_ENLIGHTENED_VMCS_RECOMMENDED
}
884 .dependencies
= BIT(HYPERV_FEAT_VAPIC
)
886 [HYPERV_FEAT_IPI
] = {
887 .desc
= "paravirtualized IPI (hv-ipi)",
889 {.fw
= FEAT_HV_RECOMM_EAX
,
890 .bits
= HV_CLUSTER_IPI_RECOMMENDED
|
891 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
893 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
895 [HYPERV_FEAT_STIMER_DIRECT
] = {
896 .desc
= "direct mode synthetic timers (hv-stimer-direct)",
898 {.fw
= FEAT_HYPERV_EDX
,
899 .bits
= HV_STIMER_DIRECT_MODE_AVAILABLE
}
901 .dependencies
= BIT(HYPERV_FEAT_STIMER
)
905 static struct kvm_cpuid2
*try_get_hv_cpuid(CPUState
*cs
, int max
)
907 struct kvm_cpuid2
*cpuid
;
910 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
911 cpuid
= g_malloc0(size
);
914 r
= kvm_vcpu_ioctl(cs
, KVM_GET_SUPPORTED_HV_CPUID
, cpuid
);
915 if (r
== 0 && cpuid
->nent
>= max
) {
923 fprintf(stderr
, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
932 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
935 static struct kvm_cpuid2
*get_supported_hv_cpuid(CPUState
*cs
)
937 struct kvm_cpuid2
*cpuid
;
938 int max
= 7; /* 0x40000000..0x40000005, 0x4000000A */
941 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
942 * -E2BIG, however, it doesn't report back the right size. Keep increasing
943 * it and re-trying until we succeed.
945 while ((cpuid
= try_get_hv_cpuid(cs
, max
)) == NULL
) {
952 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
953 * leaves from KVM_CAP_HYPERV* and present MSRs data.
955 static struct kvm_cpuid2
*get_supported_hv_cpuid_legacy(CPUState
*cs
)
957 X86CPU
*cpu
= X86_CPU(cs
);
958 struct kvm_cpuid2
*cpuid
;
959 struct kvm_cpuid_entry2
*entry_feat
, *entry_recomm
;
961 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
962 cpuid
= g_malloc0(sizeof(*cpuid
) + 2 * sizeof(*cpuid
->entries
));
965 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
966 entry_feat
= &cpuid
->entries
[0];
967 entry_feat
->function
= HV_CPUID_FEATURES
;
969 entry_recomm
= &cpuid
->entries
[1];
970 entry_recomm
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
971 entry_recomm
->ebx
= cpu
->hyperv_spinlock_attempts
;
973 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0) {
974 entry_feat
->eax
|= HV_HYPERCALL_AVAILABLE
;
975 entry_feat
->eax
|= HV_APIC_ACCESS_AVAILABLE
;
976 entry_feat
->edx
|= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
977 entry_recomm
->eax
|= HV_RELAXED_TIMING_RECOMMENDED
;
978 entry_recomm
->eax
|= HV_APIC_ACCESS_RECOMMENDED
;
981 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
982 entry_feat
->eax
|= HV_TIME_REF_COUNT_AVAILABLE
;
983 entry_feat
->eax
|= HV_REFERENCE_TSC_AVAILABLE
;
986 if (has_msr_hv_frequencies
) {
987 entry_feat
->eax
|= HV_ACCESS_FREQUENCY_MSRS
;
988 entry_feat
->edx
|= HV_FREQUENCY_MSRS_AVAILABLE
;
991 if (has_msr_hv_crash
) {
992 entry_feat
->edx
|= HV_GUEST_CRASH_MSR_AVAILABLE
;
995 if (has_msr_hv_reenlightenment
) {
996 entry_feat
->eax
|= HV_ACCESS_REENLIGHTENMENTS_CONTROL
;
999 if (has_msr_hv_reset
) {
1000 entry_feat
->eax
|= HV_RESET_AVAILABLE
;
1003 if (has_msr_hv_vpindex
) {
1004 entry_feat
->eax
|= HV_VP_INDEX_AVAILABLE
;
1007 if (has_msr_hv_runtime
) {
1008 entry_feat
->eax
|= HV_VP_RUNTIME_AVAILABLE
;
1011 if (has_msr_hv_synic
) {
1012 unsigned int cap
= cpu
->hyperv_synic_kvm_only
?
1013 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1015 if (kvm_check_extension(cs
->kvm_state
, cap
) > 0) {
1016 entry_feat
->eax
|= HV_SYNIC_AVAILABLE
;
1020 if (has_msr_hv_stimer
) {
1021 entry_feat
->eax
|= HV_SYNTIMERS_AVAILABLE
;
1024 if (kvm_check_extension(cs
->kvm_state
,
1025 KVM_CAP_HYPERV_TLBFLUSH
) > 0) {
1026 entry_recomm
->eax
|= HV_REMOTE_TLB_FLUSH_RECOMMENDED
;
1027 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1030 if (kvm_check_extension(cs
->kvm_state
,
1031 KVM_CAP_HYPERV_ENLIGHTENED_VMCS
) > 0) {
1032 entry_recomm
->eax
|= HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1035 if (kvm_check_extension(cs
->kvm_state
,
1036 KVM_CAP_HYPERV_SEND_IPI
) > 0) {
1037 entry_recomm
->eax
|= HV_CLUSTER_IPI_RECOMMENDED
;
1038 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1044 static int hv_cpuid_get_fw(struct kvm_cpuid2
*cpuid
, int fw
, uint32_t *r
)
1046 struct kvm_cpuid_entry2
*entry
;
1051 case FEAT_HYPERV_EAX
:
1053 func
= HV_CPUID_FEATURES
;
1055 case FEAT_HYPERV_EDX
:
1057 func
= HV_CPUID_FEATURES
;
1059 case FEAT_HV_RECOMM_EAX
:
1061 func
= HV_CPUID_ENLIGHTMENT_INFO
;
1067 entry
= cpuid_find_entry(cpuid
, func
, 0);
1086 static int hv_cpuid_check_and_set(CPUState
*cs
, struct kvm_cpuid2
*cpuid
,
1089 X86CPU
*cpu
= X86_CPU(cs
);
1090 CPUX86State
*env
= &cpu
->env
;
1091 uint32_t r
, fw
, bits
;
1095 if (!hyperv_feat_enabled(cpu
, feature
) && !cpu
->hyperv_passthrough
) {
1099 deps
= kvm_hyperv_properties
[feature
].dependencies
;
1101 dep_feat
= ctz64(deps
);
1102 if (!(hyperv_feat_enabled(cpu
, dep_feat
))) {
1104 "Hyper-V %s requires Hyper-V %s\n",
1105 kvm_hyperv_properties
[feature
].desc
,
1106 kvm_hyperv_properties
[dep_feat
].desc
);
1109 deps
&= ~(1ull << dep_feat
);
1112 for (i
= 0; i
< ARRAY_SIZE(kvm_hyperv_properties
[feature
].flags
); i
++) {
1113 fw
= kvm_hyperv_properties
[feature
].flags
[i
].fw
;
1114 bits
= kvm_hyperv_properties
[feature
].flags
[i
].bits
;
1120 if (hv_cpuid_get_fw(cpuid
, fw
, &r
) || (r
& bits
) != bits
) {
1121 if (hyperv_feat_enabled(cpu
, feature
)) {
1123 "Hyper-V %s is not supported by kernel\n",
1124 kvm_hyperv_properties
[feature
].desc
);
1131 env
->features
[fw
] |= bits
;
1134 if (cpu
->hyperv_passthrough
) {
1135 cpu
->hyperv_features
|= BIT(feature
);
1142 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1143 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1144 * extentions are enabled.
1146 static int hyperv_handle_properties(CPUState
*cs
,
1147 struct kvm_cpuid_entry2
*cpuid_ent
)
1149 X86CPU
*cpu
= X86_CPU(cs
);
1150 CPUX86State
*env
= &cpu
->env
;
1151 struct kvm_cpuid2
*cpuid
;
1152 struct kvm_cpuid_entry2
*c
;
1153 uint32_t signature
[3];
1154 uint32_t cpuid_i
= 0;
1157 if (!hyperv_enabled(cpu
))
1160 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ||
1161 cpu
->hyperv_passthrough
) {
1162 uint16_t evmcs_version
;
1164 r
= kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_ENLIGHTENED_VMCS
, 0,
1165 (uintptr_t)&evmcs_version
);
1167 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) && r
) {
1168 fprintf(stderr
, "Hyper-V %s is not supported by kernel\n",
1169 kvm_hyperv_properties
[HYPERV_FEAT_EVMCS
].desc
);
1174 env
->features
[FEAT_HV_RECOMM_EAX
] |=
1175 HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1176 env
->features
[FEAT_HV_NESTED_EAX
] = evmcs_version
;
1180 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_CPUID
) > 0) {
1181 cpuid
= get_supported_hv_cpuid(cs
);
1183 cpuid
= get_supported_hv_cpuid_legacy(cs
);
1186 if (cpu
->hyperv_passthrough
) {
1187 memcpy(cpuid_ent
, &cpuid
->entries
[0],
1188 cpuid
->nent
* sizeof(cpuid
->entries
[0]));
1190 c
= cpuid_find_entry(cpuid
, HV_CPUID_FEATURES
, 0);
1192 env
->features
[FEAT_HYPERV_EAX
] = c
->eax
;
1193 env
->features
[FEAT_HYPERV_EBX
] = c
->ebx
;
1194 env
->features
[FEAT_HYPERV_EDX
] = c
->eax
;
1196 c
= cpuid_find_entry(cpuid
, HV_CPUID_ENLIGHTMENT_INFO
, 0);
1198 env
->features
[FEAT_HV_RECOMM_EAX
] = c
->eax
;
1200 /* hv-spinlocks may have been overriden */
1201 if (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) {
1202 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1205 c
= cpuid_find_entry(cpuid
, HV_CPUID_NESTED_FEATURES
, 0);
1207 env
->features
[FEAT_HV_NESTED_EAX
] = c
->eax
;
1212 r
= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RELAXED
);
1213 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VAPIC
);
1214 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TIME
);
1215 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_CRASH
);
1216 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RESET
);
1217 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VPINDEX
);
1218 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RUNTIME
);
1219 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_SYNIC
);
1220 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER
);
1221 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_FREQUENCIES
);
1222 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_REENLIGHTENMENT
);
1223 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TLBFLUSH
);
1224 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_EVMCS
);
1225 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_IPI
);
1226 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER_DIRECT
);
1228 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1229 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
) &&
1230 !cpu
->hyperv_synic_kvm_only
&&
1231 !hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)) {
1232 fprintf(stderr
, "Hyper-V %s requires Hyper-V %s\n",
1233 kvm_hyperv_properties
[HYPERV_FEAT_SYNIC
].desc
,
1234 kvm_hyperv_properties
[HYPERV_FEAT_VPINDEX
].desc
);
1238 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1239 env
->features
[FEAT_HYPERV_EDX
] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
1246 if (cpu
->hyperv_passthrough
) {
1247 /* We already copied all feature words from KVM as is */
1252 c
= &cpuid_ent
[cpuid_i
++];
1253 c
->function
= HV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
1254 if (!cpu
->hyperv_vendor_id
) {
1255 memcpy(signature
, "Microsoft Hv", 12);
1257 size_t len
= strlen(cpu
->hyperv_vendor_id
);
1260 error_report("hv-vendor-id truncated to 12 characters");
1263 memset(signature
, 0, 12);
1264 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
1266 c
->eax
= hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ?
1267 HV_CPUID_NESTED_FEATURES
: HV_CPUID_IMPLEMENT_LIMITS
;
1268 c
->ebx
= signature
[0];
1269 c
->ecx
= signature
[1];
1270 c
->edx
= signature
[2];
1272 c
= &cpuid_ent
[cpuid_i
++];
1273 c
->function
= HV_CPUID_INTERFACE
;
1274 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
1275 c
->eax
= signature
[0];
1280 c
= &cpuid_ent
[cpuid_i
++];
1281 c
->function
= HV_CPUID_VERSION
;
1282 c
->eax
= 0x00001bbc;
1283 c
->ebx
= 0x00060001;
1285 c
= &cpuid_ent
[cpuid_i
++];
1286 c
->function
= HV_CPUID_FEATURES
;
1287 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
1288 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
1289 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
1291 c
= &cpuid_ent
[cpuid_i
++];
1292 c
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
1293 c
->eax
= env
->features
[FEAT_HV_RECOMM_EAX
];
1294 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1296 c
= &cpuid_ent
[cpuid_i
++];
1297 c
->function
= HV_CPUID_IMPLEMENT_LIMITS
;
1298 c
->eax
= cpu
->hv_max_vps
;
1301 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
)) {
1304 /* Create zeroed 0x40000006..0x40000009 leaves */
1305 for (function
= HV_CPUID_IMPLEMENT_LIMITS
+ 1;
1306 function
< HV_CPUID_NESTED_FEATURES
; function
++) {
1307 c
= &cpuid_ent
[cpuid_i
++];
1308 c
->function
= function
;
1311 c
= &cpuid_ent
[cpuid_i
++];
1312 c
->function
= HV_CPUID_NESTED_FEATURES
;
1313 c
->eax
= env
->features
[FEAT_HV_NESTED_EAX
];
1323 static Error
*hv_passthrough_mig_blocker
;
1325 static int hyperv_init_vcpu(X86CPU
*cpu
)
1327 CPUState
*cs
= CPU(cpu
);
1328 Error
*local_err
= NULL
;
1331 if (cpu
->hyperv_passthrough
&& hv_passthrough_mig_blocker
== NULL
) {
1332 error_setg(&hv_passthrough_mig_blocker
,
1333 "'hv-passthrough' CPU flag prevents migration, use explicit"
1334 " set of hv-* flags instead");
1335 ret
= migrate_add_blocker(hv_passthrough_mig_blocker
, &local_err
);
1337 error_report_err(local_err
);
1338 error_free(hv_passthrough_mig_blocker
);
1343 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
) && !hv_vpindex_settable
) {
1345 * the kernel doesn't support setting vp_index; assert that its value
1349 struct kvm_msrs info
;
1350 struct kvm_msr_entry entries
[1];
1353 .entries
[0].index
= HV_X64_MSR_VP_INDEX
,
1356 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MSRS
, &msr_data
);
1362 if (msr_data
.entries
[0].data
!= hyperv_vp_index(CPU(cpu
))) {
1363 error_report("kernel's vp_index != QEMU's vp_index");
1368 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1369 uint32_t synic_cap
= cpu
->hyperv_synic_kvm_only
?
1370 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1371 ret
= kvm_vcpu_enable_cap(cs
, synic_cap
, 0);
1373 error_report("failed to turn on HyperV SynIC in KVM: %s",
1378 if (!cpu
->hyperv_synic_kvm_only
) {
1379 ret
= hyperv_x86_synic_add(cpu
);
1381 error_report("failed to create HyperV SynIC: %s",
1391 static Error
*invtsc_mig_blocker
;
1393 #define KVM_MAX_CPUID_ENTRIES 100
1395 int kvm_arch_init_vcpu(CPUState
*cs
)
1398 struct kvm_cpuid2 cpuid
;
1399 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
1402 * The kernel defines these structs with padding fields so there
1403 * should be no extra padding in our cpuid_data struct.
1405 QEMU_BUILD_BUG_ON(sizeof(cpuid_data
) !=
1406 sizeof(struct kvm_cpuid2
) +
1407 sizeof(struct kvm_cpuid_entry2
) * KVM_MAX_CPUID_ENTRIES
);
1409 X86CPU
*cpu
= X86_CPU(cs
);
1410 CPUX86State
*env
= &cpu
->env
;
1411 uint32_t limit
, i
, j
, cpuid_i
;
1413 struct kvm_cpuid_entry2
*c
;
1414 uint32_t signature
[3];
1415 int kvm_base
= KVM_CPUID_SIGNATURE
;
1416 int max_nested_state_len
;
1418 Error
*local_err
= NULL
;
1420 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
1424 r
= kvm_arch_set_tsc_khz(cs
);
1429 /* vcpu's TSC frequency is either specified by user, or following
1430 * the value used by KVM if the former is not present. In the
1431 * latter case, we query it from KVM and record in env->tsc_khz,
1432 * so that vcpu's TSC frequency can be migrated later via this field.
1434 if (!env
->tsc_khz
) {
1435 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
1436 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
1443 /* Paravirtualization CPUIDs */
1444 r
= hyperv_handle_properties(cs
, cpuid_data
.entries
);
1449 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
1450 has_msr_hv_hypercall
= true;
1453 if (cpu
->expose_kvm
) {
1454 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
1455 c
= &cpuid_data
.entries
[cpuid_i
++];
1456 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
1457 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
1458 c
->ebx
= signature
[0];
1459 c
->ecx
= signature
[1];
1460 c
->edx
= signature
[2];
1462 c
= &cpuid_data
.entries
[cpuid_i
++];
1463 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
1464 c
->eax
= env
->features
[FEAT_KVM
];
1465 c
->edx
= env
->features
[FEAT_KVM_HINTS
];
1468 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
1470 for (i
= 0; i
<= limit
; i
++) {
1471 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1472 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
1475 c
= &cpuid_data
.entries
[cpuid_i
++];
1479 /* Keep reading function 2 till all the input is received */
1483 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
1484 KVM_CPUID_FLAG_STATE_READ_NEXT
;
1485 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1486 times
= c
->eax
& 0xff;
1488 for (j
= 1; j
< times
; ++j
) {
1489 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1490 fprintf(stderr
, "cpuid_data is full, no space for "
1491 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
1494 c
= &cpuid_data
.entries
[cpuid_i
++];
1496 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
1497 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1502 if (env
->nr_dies
< 2) {
1508 for (j
= 0; ; j
++) {
1509 if (i
== 0xd && j
== 64) {
1513 if (i
== 0x1f && j
== 64) {
1518 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1520 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1522 if (i
== 4 && c
->eax
== 0) {
1525 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
1528 if (i
== 0x1f && !(c
->ecx
& 0xff00)) {
1531 if (i
== 0xd && c
->eax
== 0) {
1534 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1535 fprintf(stderr
, "cpuid_data is full, no space for "
1536 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1539 c
= &cpuid_data
.entries
[cpuid_i
++];
1548 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1549 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1552 for (j
= 1; j
<= times
; ++j
) {
1553 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1554 fprintf(stderr
, "cpuid_data is full, no space for "
1555 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1558 c
= &cpuid_data
.entries
[cpuid_i
++];
1561 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1562 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1569 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1570 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1572 * KVM already returns all zeroes if a CPUID entry is missing,
1573 * so we can omit it and avoid hitting KVM's 80-entry limit.
1581 if (limit
>= 0x0a) {
1584 cpu_x86_cpuid(env
, 0x0a, 0, &eax
, &unused
, &unused
, &edx
);
1586 has_architectural_pmu_version
= eax
& 0xff;
1587 if (has_architectural_pmu_version
> 0) {
1588 num_architectural_pmu_gp_counters
= (eax
& 0xff00) >> 8;
1590 /* Shouldn't be more than 32, since that's the number of bits
1591 * available in EBX to tell us _which_ counters are available.
1594 if (num_architectural_pmu_gp_counters
> MAX_GP_COUNTERS
) {
1595 num_architectural_pmu_gp_counters
= MAX_GP_COUNTERS
;
1598 if (has_architectural_pmu_version
> 1) {
1599 num_architectural_pmu_fixed_counters
= edx
& 0x1f;
1601 if (num_architectural_pmu_fixed_counters
> MAX_FIXED_COUNTERS
) {
1602 num_architectural_pmu_fixed_counters
= MAX_FIXED_COUNTERS
;
1608 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
1610 for (i
= 0x80000000; i
<= limit
; i
++) {
1611 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1612 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
1615 c
= &cpuid_data
.entries
[cpuid_i
++];
1619 /* Query for all AMD cache information leaves */
1620 for (j
= 0; ; j
++) {
1622 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1624 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1629 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1630 fprintf(stderr
, "cpuid_data is full, no space for "
1631 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1634 c
= &cpuid_data
.entries
[cpuid_i
++];
1640 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1641 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1643 * KVM already returns all zeroes if a CPUID entry is missing,
1644 * so we can omit it and avoid hitting KVM's 80-entry limit.
1652 /* Call Centaur's CPUID instructions they are supported. */
1653 if (env
->cpuid_xlevel2
> 0) {
1654 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
1656 for (i
= 0xC0000000; i
<= limit
; i
++) {
1657 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1658 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
1661 c
= &cpuid_data
.entries
[cpuid_i
++];
1665 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1669 cpuid_data
.cpuid
.nent
= cpuid_i
;
1671 if (((env
->cpuid_version
>> 8)&0xF) >= 6
1672 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
1673 (CPUID_MCE
| CPUID_MCA
)
1674 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
1675 uint64_t mcg_cap
, unsupported_caps
;
1679 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
1681 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
1685 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
1686 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1687 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
1691 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
1692 if (unsupported_caps
) {
1693 if (unsupported_caps
& MCG_LMCE_P
) {
1694 error_report("kvm: LMCE not supported");
1697 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64
,
1701 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
1702 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
1704 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
1709 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
1711 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
1713 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
1714 !!(c
->ecx
& CPUID_EXT_SMX
);
1717 if (env
->mcg_cap
& MCG_LMCE_P
) {
1718 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
1721 if (!env
->user_tsc_khz
) {
1722 if ((env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
) &&
1723 invtsc_mig_blocker
== NULL
) {
1724 error_setg(&invtsc_mig_blocker
,
1725 "State blocked by non-migratable CPU device"
1727 r
= migrate_add_blocker(invtsc_mig_blocker
, &local_err
);
1729 error_report_err(local_err
);
1730 error_free(invtsc_mig_blocker
);
1736 if (cpu
->vmware_cpuid_freq
1737 /* Guests depend on 0x40000000 to detect this feature, so only expose
1738 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1740 && kvm_base
== KVM_CPUID_SIGNATURE
1741 /* TSC clock must be stable and known for this feature. */
1742 && tsc_is_stable_and_known(env
)) {
1744 c
= &cpuid_data
.entries
[cpuid_i
++];
1745 c
->function
= KVM_CPUID_SIGNATURE
| 0x10;
1746 c
->eax
= env
->tsc_khz
;
1747 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1748 * APIC_BUS_CYCLE_NS */
1750 c
->ecx
= c
->edx
= 0;
1752 c
= cpuid_find_entry(&cpuid_data
.cpuid
, kvm_base
, 0);
1753 c
->eax
= MAX(c
->eax
, KVM_CPUID_SIGNATURE
| 0x10);
1756 cpuid_data
.cpuid
.nent
= cpuid_i
;
1758 cpuid_data
.cpuid
.padding
= 0;
1759 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
1765 env
->xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1766 memset(env
->xsave_buf
, 0, sizeof(struct kvm_xsave
));
1769 max_nested_state_len
= kvm_max_nested_state_length();
1770 if (max_nested_state_len
> 0) {
1771 assert(max_nested_state_len
>= offsetof(struct kvm_nested_state
, data
));
1773 if (cpu_has_vmx(env
)) {
1774 struct kvm_vmx_nested_state_hdr
*vmx_hdr
;
1776 env
->nested_state
= g_malloc0(max_nested_state_len
);
1777 env
->nested_state
->size
= max_nested_state_len
;
1778 env
->nested_state
->format
= KVM_STATE_NESTED_FORMAT_VMX
;
1780 vmx_hdr
= &env
->nested_state
->hdr
.vmx
;
1781 vmx_hdr
->vmxon_pa
= -1ull;
1782 vmx_hdr
->vmcs12_pa
= -1ull;
1786 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
1788 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
1789 has_msr_tsc_aux
= false;
1792 r
= hyperv_init_vcpu(cpu
);
1800 migrate_del_blocker(invtsc_mig_blocker
);
1805 int kvm_arch_destroy_vcpu(CPUState
*cs
)
1807 X86CPU
*cpu
= X86_CPU(cs
);
1808 CPUX86State
*env
= &cpu
->env
;
1810 if (cpu
->kvm_msr_buf
) {
1811 g_free(cpu
->kvm_msr_buf
);
1812 cpu
->kvm_msr_buf
= NULL
;
1815 if (env
->nested_state
) {
1816 g_free(env
->nested_state
);
1817 env
->nested_state
= NULL
;
1823 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
1825 CPUX86State
*env
= &cpu
->env
;
1828 if (kvm_irqchip_in_kernel()) {
1829 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
1830 KVM_MP_STATE_UNINITIALIZED
;
1832 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1835 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1837 for (i
= 0; i
< ARRAY_SIZE(env
->msr_hv_synic_sint
); i
++) {
1838 env
->msr_hv_synic_sint
[i
] = HV_SINT_MASKED
;
1841 hyperv_x86_synic_reset(cpu
);
1843 /* enabled by default */
1844 env
->poll_control_msr
= 1;
1847 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
1849 CPUX86State
*env
= &cpu
->env
;
1851 /* APs get directly into wait-for-SIPI state. */
1852 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1853 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1857 static int kvm_get_supported_feature_msrs(KVMState
*s
)
1861 if (kvm_feature_msrs
!= NULL
) {
1865 if (!kvm_check_extension(s
, KVM_CAP_GET_MSR_FEATURES
)) {
1869 struct kvm_msr_list msr_list
;
1872 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, &msr_list
);
1873 if (ret
< 0 && ret
!= -E2BIG
) {
1874 error_report("Fetch KVM feature MSR list failed: %s",
1879 assert(msr_list
.nmsrs
> 0);
1880 kvm_feature_msrs
= (struct kvm_msr_list
*) \
1881 g_malloc0(sizeof(msr_list
) +
1882 msr_list
.nmsrs
* sizeof(msr_list
.indices
[0]));
1884 kvm_feature_msrs
->nmsrs
= msr_list
.nmsrs
;
1885 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, kvm_feature_msrs
);
1888 error_report("Fetch KVM feature MSR list failed: %s",
1890 g_free(kvm_feature_msrs
);
1891 kvm_feature_msrs
= NULL
;
1898 static int kvm_get_supported_msrs(KVMState
*s
)
1901 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1904 * Obtain MSR list from KVM. These are the MSRs that we must
1908 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1909 if (ret
< 0 && ret
!= -E2BIG
) {
1913 * Old kernel modules had a bug and could write beyond the provided
1914 * memory. Allocate at least a safe amount of 1K.
1916 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1918 sizeof(msr_list
.indices
[0])));
1920 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1921 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1925 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1926 switch (kvm_msr_list
->indices
[i
]) {
1928 has_msr_star
= true;
1930 case MSR_VM_HSAVE_PA
:
1931 has_msr_hsave_pa
= true;
1934 has_msr_tsc_aux
= true;
1936 case MSR_TSC_ADJUST
:
1937 has_msr_tsc_adjust
= true;
1939 case MSR_IA32_TSCDEADLINE
:
1940 has_msr_tsc_deadline
= true;
1942 case MSR_IA32_SMBASE
:
1943 has_msr_smbase
= true;
1946 has_msr_smi_count
= true;
1948 case MSR_IA32_MISC_ENABLE
:
1949 has_msr_misc_enable
= true;
1951 case MSR_IA32_BNDCFGS
:
1952 has_msr_bndcfgs
= true;
1957 case HV_X64_MSR_CRASH_CTL
:
1958 has_msr_hv_crash
= true;
1960 case HV_X64_MSR_RESET
:
1961 has_msr_hv_reset
= true;
1963 case HV_X64_MSR_VP_INDEX
:
1964 has_msr_hv_vpindex
= true;
1966 case HV_X64_MSR_VP_RUNTIME
:
1967 has_msr_hv_runtime
= true;
1969 case HV_X64_MSR_SCONTROL
:
1970 has_msr_hv_synic
= true;
1972 case HV_X64_MSR_STIMER0_CONFIG
:
1973 has_msr_hv_stimer
= true;
1975 case HV_X64_MSR_TSC_FREQUENCY
:
1976 has_msr_hv_frequencies
= true;
1978 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
1979 has_msr_hv_reenlightenment
= true;
1981 case MSR_IA32_SPEC_CTRL
:
1982 has_msr_spec_ctrl
= true;
1985 has_msr_virt_ssbd
= true;
1987 case MSR_IA32_ARCH_CAPABILITIES
:
1988 has_msr_arch_capabs
= true;
1990 case MSR_IA32_CORE_CAPABILITY
:
1991 has_msr_core_capabs
= true;
1993 case MSR_IA32_VMX_VMFUNC
:
1994 has_msr_vmx_vmfunc
= true;
2000 g_free(kvm_msr_list
);
2005 static Notifier smram_machine_done
;
2006 static KVMMemoryListener smram_listener
;
2007 static AddressSpace smram_address_space
;
2008 static MemoryRegion smram_as_root
;
2009 static MemoryRegion smram_as_mem
;
2011 static void register_smram_listener(Notifier
*n
, void *unused
)
2013 MemoryRegion
*smram
=
2014 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
2016 /* Outer container... */
2017 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
2018 memory_region_set_enabled(&smram_as_root
, true);
2020 /* ... with two regions inside: normal system memory with low
2023 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
2024 get_system_memory(), 0, ~0ull);
2025 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
2026 memory_region_set_enabled(&smram_as_mem
, true);
2029 /* ... SMRAM with higher priority */
2030 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
2031 memory_region_set_enabled(smram
, true);
2034 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
2035 kvm_memory_listener_register(kvm_state
, &smram_listener
,
2036 &smram_address_space
, 1);
2039 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
2041 uint64_t identity_base
= 0xfffbc000;
2042 uint64_t shadow_mem
;
2044 struct utsname utsname
;
2046 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
2047 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
2048 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
2050 hv_vpindex_settable
= kvm_check_extension(s
, KVM_CAP_HYPERV_VP_INDEX
);
2052 has_exception_payload
= kvm_check_extension(s
, KVM_CAP_EXCEPTION_PAYLOAD
);
2053 if (has_exception_payload
) {
2054 ret
= kvm_vm_enable_cap(s
, KVM_CAP_EXCEPTION_PAYLOAD
, 0, true);
2056 error_report("kvm: Failed to enable exception payload cap: %s",
2062 ret
= kvm_get_supported_msrs(s
);
2067 kvm_get_supported_feature_msrs(s
);
2070 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
2073 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2074 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2075 * Since these must be part of guest physical memory, we need to allocate
2076 * them, both by setting their start addresses in the kernel and by
2077 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2079 * Older KVM versions may not support setting the identity map base. In
2080 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2083 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
2084 /* Allows up to 16M BIOSes. */
2085 identity_base
= 0xfeffc000;
2087 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
2093 /* Set TSS base one page after EPT identity map. */
2094 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
2099 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2100 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
2102 fprintf(stderr
, "e820_add_entry() table is full\n");
2105 qemu_register_reset(kvm_unpoison_all
, NULL
);
2107 shadow_mem
= machine_kvm_shadow_mem(ms
);
2108 if (shadow_mem
!= -1) {
2110 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
2116 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
) &&
2117 object_dynamic_cast(OBJECT(ms
), TYPE_PC_MACHINE
) &&
2118 pc_machine_is_smm_enabled(PC_MACHINE(ms
))) {
2119 smram_machine_done
.notify
= register_smram_listener
;
2120 qemu_add_machine_init_done_notifier(&smram_machine_done
);
2123 if (enable_cpu_pm
) {
2124 int disable_exits
= kvm_check_extension(s
, KVM_CAP_X86_DISABLE_EXITS
);
2127 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2128 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2129 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2131 if (disable_exits
) {
2132 disable_exits
&= (KVM_X86_DISABLE_EXITS_MWAIT
|
2133 KVM_X86_DISABLE_EXITS_HLT
|
2134 KVM_X86_DISABLE_EXITS_PAUSE
|
2135 KVM_X86_DISABLE_EXITS_CSTATE
);
2138 ret
= kvm_vm_enable_cap(s
, KVM_CAP_X86_DISABLE_EXITS
, 0,
2141 error_report("kvm: guest stopping CPU not supported: %s",
2149 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2151 lhs
->selector
= rhs
->selector
;
2152 lhs
->base
= rhs
->base
;
2153 lhs
->limit
= rhs
->limit
;
2165 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2167 unsigned flags
= rhs
->flags
;
2168 lhs
->selector
= rhs
->selector
;
2169 lhs
->base
= rhs
->base
;
2170 lhs
->limit
= rhs
->limit
;
2171 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
2172 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
2173 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2174 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
2175 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
2176 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
2177 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
2178 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
2179 lhs
->unusable
= !lhs
->present
;
2183 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
2185 lhs
->selector
= rhs
->selector
;
2186 lhs
->base
= rhs
->base
;
2187 lhs
->limit
= rhs
->limit
;
2188 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
2189 ((rhs
->present
&& !rhs
->unusable
) * DESC_P_MASK
) |
2190 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
2191 (rhs
->db
<< DESC_B_SHIFT
) |
2192 (rhs
->s
* DESC_S_MASK
) |
2193 (rhs
->l
<< DESC_L_SHIFT
) |
2194 (rhs
->g
* DESC_G_MASK
) |
2195 (rhs
->avl
* DESC_AVL_MASK
);
2198 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
2201 *kvm_reg
= *qemu_reg
;
2203 *qemu_reg
= *kvm_reg
;
2207 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
2209 CPUX86State
*env
= &cpu
->env
;
2210 struct kvm_regs regs
;
2214 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
2220 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
2221 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
2222 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
2223 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
2224 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
2225 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
2226 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
2227 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
2228 #ifdef TARGET_X86_64
2229 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
2230 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
2231 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
2232 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
2233 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
2234 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
2235 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
2236 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
2239 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
2240 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
2243 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
2249 static int kvm_put_fpu(X86CPU
*cpu
)
2251 CPUX86State
*env
= &cpu
->env
;
2255 memset(&fpu
, 0, sizeof fpu
);
2256 fpu
.fsw
= env
->fpus
& ~(7 << 11);
2257 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
2258 fpu
.fcw
= env
->fpuc
;
2259 fpu
.last_opcode
= env
->fpop
;
2260 fpu
.last_ip
= env
->fpip
;
2261 fpu
.last_dp
= env
->fpdp
;
2262 for (i
= 0; i
< 8; ++i
) {
2263 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
2265 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
2266 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2267 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
2268 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
2270 fpu
.mxcsr
= env
->mxcsr
;
2272 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
2275 #define XSAVE_FCW_FSW 0
2276 #define XSAVE_FTW_FOP 1
2277 #define XSAVE_CWD_RIP 2
2278 #define XSAVE_CWD_RDP 4
2279 #define XSAVE_MXCSR 6
2280 #define XSAVE_ST_SPACE 8
2281 #define XSAVE_XMM_SPACE 40
2282 #define XSAVE_XSTATE_BV 128
2283 #define XSAVE_YMMH_SPACE 144
2284 #define XSAVE_BNDREGS 240
2285 #define XSAVE_BNDCSR 256
2286 #define XSAVE_OPMASK 272
2287 #define XSAVE_ZMM_Hi256 288
2288 #define XSAVE_Hi16_ZMM 416
2289 #define XSAVE_PKRU 672
2291 #define XSAVE_BYTE_OFFSET(word_offset) \
2292 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2294 #define ASSERT_OFFSET(word_offset, field) \
2295 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2296 offsetof(X86XSaveArea, field))
2298 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
2299 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
2300 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
2301 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
2302 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
2303 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
2304 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
2305 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
2306 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
2307 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
2308 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
2309 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
2310 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
2311 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
2312 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
2314 static int kvm_put_xsave(X86CPU
*cpu
)
2316 CPUX86State
*env
= &cpu
->env
;
2317 X86XSaveArea
*xsave
= env
->xsave_buf
;
2320 return kvm_put_fpu(cpu
);
2322 x86_cpu_xsave_all_areas(cpu
, xsave
);
2324 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
2327 static int kvm_put_xcrs(X86CPU
*cpu
)
2329 CPUX86State
*env
= &cpu
->env
;
2330 struct kvm_xcrs xcrs
= {};
2338 xcrs
.xcrs
[0].xcr
= 0;
2339 xcrs
.xcrs
[0].value
= env
->xcr0
;
2340 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
2343 static int kvm_put_sregs(X86CPU
*cpu
)
2345 CPUX86State
*env
= &cpu
->env
;
2346 struct kvm_sregs sregs
;
2348 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
2349 if (env
->interrupt_injected
>= 0) {
2350 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
2351 (uint64_t)1 << (env
->interrupt_injected
% 64);
2354 if ((env
->eflags
& VM_MASK
)) {
2355 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2356 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2357 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2358 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2359 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2360 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2362 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2363 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2364 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2365 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2366 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2367 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2370 set_seg(&sregs
.tr
, &env
->tr
);
2371 set_seg(&sregs
.ldt
, &env
->ldt
);
2373 sregs
.idt
.limit
= env
->idt
.limit
;
2374 sregs
.idt
.base
= env
->idt
.base
;
2375 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
2376 sregs
.gdt
.limit
= env
->gdt
.limit
;
2377 sregs
.gdt
.base
= env
->gdt
.base
;
2378 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
2380 sregs
.cr0
= env
->cr
[0];
2381 sregs
.cr2
= env
->cr
[2];
2382 sregs
.cr3
= env
->cr
[3];
2383 sregs
.cr4
= env
->cr
[4];
2385 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
2386 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
2388 sregs
.efer
= env
->efer
;
2390 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
2393 static void kvm_msr_buf_reset(X86CPU
*cpu
)
2395 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
2398 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
2400 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
2401 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
2402 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
2404 assert((void *)(entry
+ 1) <= limit
);
2406 entry
->index
= index
;
2407 entry
->reserved
= 0;
2408 entry
->data
= value
;
2412 static int kvm_put_one_msr(X86CPU
*cpu
, int index
, uint64_t value
)
2414 kvm_msr_buf_reset(cpu
);
2415 kvm_msr_entry_add(cpu
, index
, value
);
2417 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2420 void kvm_put_apicbase(X86CPU
*cpu
, uint64_t value
)
2424 ret
= kvm_put_one_msr(cpu
, MSR_IA32_APICBASE
, value
);
2428 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
2430 CPUX86State
*env
= &cpu
->env
;
2433 if (!has_msr_tsc_deadline
) {
2437 ret
= kvm_put_one_msr(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
2447 * Provide a separate write service for the feature control MSR in order to
2448 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2449 * before writing any other state because forcibly leaving nested mode
2450 * invalidates the VCPU state.
2452 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
2456 if (!has_msr_feature_control
) {
2460 ret
= kvm_put_one_msr(cpu
, MSR_IA32_FEATURE_CONTROL
,
2461 cpu
->env
.msr_ia32_feature_control
);
2470 static uint64_t make_vmx_msr_value(uint32_t index
, uint32_t features
)
2472 uint32_t default1
, can_be_one
, can_be_zero
;
2473 uint32_t must_be_one
;
2476 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2477 default1
= 0x00000016;
2479 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2480 default1
= 0x0401e172;
2482 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2483 default1
= 0x000011ff;
2485 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2486 default1
= 0x00036dff;
2488 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2495 /* If a feature bit is set, the control can be either set or clear.
2496 * Otherwise the value is limited to either 0 or 1 by default1.
2498 can_be_one
= features
| default1
;
2499 can_be_zero
= features
| ~default1
;
2500 must_be_one
= ~can_be_zero
;
2503 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2504 * Bit 32:63 -> 1 if the control bit can be one.
2506 return must_be_one
| (((uint64_t)can_be_one
) << 32);
2509 #define VMCS12_MAX_FIELD_INDEX (0x17)
2511 static void kvm_msr_entry_add_vmx(X86CPU
*cpu
, FeatureWordArray f
)
2513 uint64_t kvm_vmx_basic
=
2514 kvm_arch_get_supported_msr_feature(kvm_state
,
2515 MSR_IA32_VMX_BASIC
);
2516 uint64_t kvm_vmx_misc
=
2517 kvm_arch_get_supported_msr_feature(kvm_state
,
2519 uint64_t kvm_vmx_ept_vpid
=
2520 kvm_arch_get_supported_msr_feature(kvm_state
,
2521 MSR_IA32_VMX_EPT_VPID_CAP
);
2524 * If the guest is 64-bit, a value of 1 is allowed for the host address
2525 * space size vmexit control.
2527 uint64_t fixed_vmx_exit
= f
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
2528 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE
<< 32 : 0;
2531 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2532 * not change them for backwards compatibility.
2534 uint64_t fixed_vmx_basic
= kvm_vmx_basic
&
2535 (MSR_VMX_BASIC_VMCS_REVISION_MASK
|
2536 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK
|
2537 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK
);
2540 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2541 * change in the future but are always zero for now, clear them to be
2542 * future proof. Bits 32-63 in theory could change, though KVM does
2543 * not support dual-monitor treatment and probably never will; mask
2546 uint64_t fixed_vmx_misc
= kvm_vmx_misc
&
2547 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK
|
2548 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK
);
2551 * EPT memory types should not change either, so we do not bother
2552 * adding features for them.
2554 uint64_t fixed_vmx_ept_mask
=
2555 (f
[FEAT_VMX_SECONDARY_CTLS
] & VMX_SECONDARY_EXEC_ENABLE_EPT
?
2556 MSR_VMX_EPT_UC
| MSR_VMX_EPT_WB
: 0);
2557 uint64_t fixed_vmx_ept_vpid
= kvm_vmx_ept_vpid
& fixed_vmx_ept_mask
;
2559 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2560 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2561 f
[FEAT_VMX_PROCBASED_CTLS
]));
2562 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2563 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2564 f
[FEAT_VMX_PINBASED_CTLS
]));
2565 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2566 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2567 f
[FEAT_VMX_EXIT_CTLS
]) | fixed_vmx_exit
);
2568 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2569 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2570 f
[FEAT_VMX_ENTRY_CTLS
]));
2571 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_PROCBASED_CTLS2
,
2572 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2
,
2573 f
[FEAT_VMX_SECONDARY_CTLS
]));
2574 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_EPT_VPID_CAP
,
2575 f
[FEAT_VMX_EPT_VPID_CAPS
] | fixed_vmx_ept_vpid
);
2576 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_BASIC
,
2577 f
[FEAT_VMX_BASIC
] | fixed_vmx_basic
);
2578 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_MISC
,
2579 f
[FEAT_VMX_MISC
] | fixed_vmx_misc
);
2580 if (has_msr_vmx_vmfunc
) {
2581 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMFUNC
, f
[FEAT_VMX_VMFUNC
]);
2585 * Just to be safe, write these with constant values. The CRn_FIXED1
2586 * MSRs are generated by KVM based on the vCPU's CPUID.
2588 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR0_FIXED0
,
2589 CR0_PE_MASK
| CR0_PG_MASK
| CR0_NE_MASK
);
2590 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR4_FIXED0
,
2592 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMCS_ENUM
,
2593 VMCS12_MAX_FIELD_INDEX
<< 1);
2596 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
2598 CPUX86State
*env
= &cpu
->env
;
2602 kvm_msr_buf_reset(cpu
);
2604 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
2605 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
2606 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
2607 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
2609 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
2611 if (has_msr_hsave_pa
) {
2612 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
2614 if (has_msr_tsc_aux
) {
2615 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
2617 if (has_msr_tsc_adjust
) {
2618 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
2620 if (has_msr_misc_enable
) {
2621 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
2622 env
->msr_ia32_misc_enable
);
2624 if (has_msr_smbase
) {
2625 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
2627 if (has_msr_smi_count
) {
2628 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, env
->msr_smi_count
);
2630 if (has_msr_bndcfgs
) {
2631 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
2634 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
2636 if (has_msr_spec_ctrl
) {
2637 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, env
->spec_ctrl
);
2639 if (has_msr_virt_ssbd
) {
2640 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, env
->virt_ssbd
);
2643 #ifdef TARGET_X86_64
2644 if (lm_capable_kernel
) {
2645 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
2646 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
2647 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
2648 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
2652 /* If host supports feature MSR, write down. */
2653 if (has_msr_arch_capabs
) {
2654 kvm_msr_entry_add(cpu
, MSR_IA32_ARCH_CAPABILITIES
,
2655 env
->features
[FEAT_ARCH_CAPABILITIES
]);
2658 if (has_msr_core_capabs
) {
2659 kvm_msr_entry_add(cpu
, MSR_IA32_CORE_CAPABILITY
,
2660 env
->features
[FEAT_CORE_CAPABILITY
]);
2664 * The following MSRs have side effects on the guest or are too heavy
2665 * for normal writeback. Limit them to reset or full state updates.
2667 if (level
>= KVM_PUT_RESET_STATE
) {
2668 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
2669 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
2670 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
2671 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
2672 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
2674 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
2675 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
2677 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
2678 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
2681 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
2682 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, env
->poll_control_msr
);
2685 if (has_architectural_pmu_version
> 0) {
2686 if (has_architectural_pmu_version
> 1) {
2687 /* Stop the counter. */
2688 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2689 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2692 /* Set the counter values. */
2693 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
2694 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
2695 env
->msr_fixed_counters
[i
]);
2697 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
2698 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
2699 env
->msr_gp_counters
[i
]);
2700 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
2701 env
->msr_gp_evtsel
[i
]);
2703 if (has_architectural_pmu_version
> 1) {
2704 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
2705 env
->msr_global_status
);
2706 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
2707 env
->msr_global_ovf_ctrl
);
2709 /* Now start the PMU. */
2710 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
2711 env
->msr_fixed_ctr_ctrl
);
2712 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
2713 env
->msr_global_ctrl
);
2717 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2718 * only sync them to KVM on the first cpu
2720 if (current_cpu
== first_cpu
) {
2721 if (has_msr_hv_hypercall
) {
2722 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
2723 env
->msr_hv_guest_os_id
);
2724 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
2725 env
->msr_hv_hypercall
);
2727 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
2728 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
,
2731 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
2732 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
,
2733 env
->msr_hv_reenlightenment_control
);
2734 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
,
2735 env
->msr_hv_tsc_emulation_control
);
2736 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
,
2737 env
->msr_hv_tsc_emulation_status
);
2740 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
2741 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
2744 if (has_msr_hv_crash
) {
2747 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++)
2748 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
2749 env
->msr_hv_crash_params
[j
]);
2751 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
, HV_CRASH_CTL_NOTIFY
);
2753 if (has_msr_hv_runtime
) {
2754 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
2756 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)
2757 && hv_vpindex_settable
) {
2758 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_INDEX
,
2759 hyperv_vp_index(CPU(cpu
)));
2761 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
2764 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, HV_SYNIC_VERSION
);
2766 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
2767 env
->msr_hv_synic_control
);
2768 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
2769 env
->msr_hv_synic_evt_page
);
2770 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
2771 env
->msr_hv_synic_msg_page
);
2773 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
2774 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
2775 env
->msr_hv_synic_sint
[j
]);
2778 if (has_msr_hv_stimer
) {
2781 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
2782 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
2783 env
->msr_hv_stimer_config
[j
]);
2786 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
2787 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
2788 env
->msr_hv_stimer_count
[j
]);
2791 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
2792 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
2794 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
2795 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
2796 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
2797 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
2798 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
2799 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
2800 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
2801 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
2802 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
2803 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
2804 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
2805 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
2806 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2807 /* The CPU GPs if we write to a bit above the physical limit of
2808 * the host CPU (and KVM emulates that)
2810 uint64_t mask
= env
->mtrr_var
[i
].mask
;
2813 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
2814 env
->mtrr_var
[i
].base
);
2815 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
2818 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
2819 int addr_num
= kvm_arch_get_supported_cpuid(kvm_state
,
2820 0x14, 1, R_EAX
) & 0x7;
2822 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
,
2823 env
->msr_rtit_ctrl
);
2824 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
,
2825 env
->msr_rtit_status
);
2826 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
,
2827 env
->msr_rtit_output_base
);
2828 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
,
2829 env
->msr_rtit_output_mask
);
2830 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
,
2831 env
->msr_rtit_cr3_match
);
2832 for (i
= 0; i
< addr_num
; i
++) {
2833 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
,
2834 env
->msr_rtit_addrs
[i
]);
2838 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2839 * kvm_put_msr_feature_control. */
2842 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2843 * all kernels with MSR features should have them.
2845 if (kvm_feature_msrs
&& cpu_has_vmx(env
)) {
2846 kvm_msr_entry_add_vmx(cpu
, env
->features
);
2853 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
2854 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
2855 if (has_msr_mcg_ext_ctl
) {
2856 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
2858 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2859 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
2863 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2868 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
2869 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
2870 error_report("error: failed to set MSR 0x%" PRIx32
" to 0x%" PRIx64
,
2871 (uint32_t)e
->index
, (uint64_t)e
->data
);
2874 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2879 static int kvm_get_fpu(X86CPU
*cpu
)
2881 CPUX86State
*env
= &cpu
->env
;
2885 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
2890 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
2891 env
->fpus
= fpu
.fsw
;
2892 env
->fpuc
= fpu
.fcw
;
2893 env
->fpop
= fpu
.last_opcode
;
2894 env
->fpip
= fpu
.last_ip
;
2895 env
->fpdp
= fpu
.last_dp
;
2896 for (i
= 0; i
< 8; ++i
) {
2897 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
2899 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
2900 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2901 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
2902 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
2904 env
->mxcsr
= fpu
.mxcsr
;
2909 static int kvm_get_xsave(X86CPU
*cpu
)
2911 CPUX86State
*env
= &cpu
->env
;
2912 X86XSaveArea
*xsave
= env
->xsave_buf
;
2916 return kvm_get_fpu(cpu
);
2919 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
2923 x86_cpu_xrstor_all_areas(cpu
, xsave
);
2928 static int kvm_get_xcrs(X86CPU
*cpu
)
2930 CPUX86State
*env
= &cpu
->env
;
2932 struct kvm_xcrs xcrs
;
2938 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
2943 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
2944 /* Only support xcr0 now */
2945 if (xcrs
.xcrs
[i
].xcr
== 0) {
2946 env
->xcr0
= xcrs
.xcrs
[i
].value
;
2953 static int kvm_get_sregs(X86CPU
*cpu
)
2955 CPUX86State
*env
= &cpu
->env
;
2956 struct kvm_sregs sregs
;
2959 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
2964 /* There can only be one pending IRQ set in the bitmap at a time, so try
2965 to find it and save its number instead (-1 for none). */
2966 env
->interrupt_injected
= -1;
2967 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
2968 if (sregs
.interrupt_bitmap
[i
]) {
2969 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
2970 env
->interrupt_injected
= i
* 64 + bit
;
2975 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
2976 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
2977 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
2978 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
2979 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
2980 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
2982 get_seg(&env
->tr
, &sregs
.tr
);
2983 get_seg(&env
->ldt
, &sregs
.ldt
);
2985 env
->idt
.limit
= sregs
.idt
.limit
;
2986 env
->idt
.base
= sregs
.idt
.base
;
2987 env
->gdt
.limit
= sregs
.gdt
.limit
;
2988 env
->gdt
.base
= sregs
.gdt
.base
;
2990 env
->cr
[0] = sregs
.cr0
;
2991 env
->cr
[2] = sregs
.cr2
;
2992 env
->cr
[3] = sregs
.cr3
;
2993 env
->cr
[4] = sregs
.cr4
;
2995 env
->efer
= sregs
.efer
;
2997 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2998 x86_update_hflags(env
);
3003 static int kvm_get_msrs(X86CPU
*cpu
)
3005 CPUX86State
*env
= &cpu
->env
;
3006 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
3008 uint64_t mtrr_top_bits
;
3010 kvm_msr_buf_reset(cpu
);
3012 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
3013 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
3014 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
3015 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
3017 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
3019 if (has_msr_hsave_pa
) {
3020 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
3022 if (has_msr_tsc_aux
) {
3023 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
3025 if (has_msr_tsc_adjust
) {
3026 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
3028 if (has_msr_tsc_deadline
) {
3029 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
3031 if (has_msr_misc_enable
) {
3032 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
3034 if (has_msr_smbase
) {
3035 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
3037 if (has_msr_smi_count
) {
3038 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, 0);
3040 if (has_msr_feature_control
) {
3041 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
3043 if (has_msr_bndcfgs
) {
3044 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
3047 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
3049 if (has_msr_spec_ctrl
) {
3050 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, 0);
3052 if (has_msr_virt_ssbd
) {
3053 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, 0);
3055 if (!env
->tsc_valid
) {
3056 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
3057 env
->tsc_valid
= !runstate_is_running();
3060 #ifdef TARGET_X86_64
3061 if (lm_capable_kernel
) {
3062 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
3063 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
3064 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
3065 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
3068 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
3069 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
3070 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
3071 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
3073 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
3074 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
3076 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
3077 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
3079 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
3080 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, 1);
3082 if (has_architectural_pmu_version
> 0) {
3083 if (has_architectural_pmu_version
> 1) {
3084 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
3085 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
3086 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
3087 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
3089 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
3090 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
3092 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
3093 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
3094 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
3099 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
3100 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
3101 if (has_msr_mcg_ext_ctl
) {
3102 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
3104 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
3105 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
3109 if (has_msr_hv_hypercall
) {
3110 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
3111 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
3113 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
3114 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
3116 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
3117 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
3119 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
3120 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
, 0);
3121 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
, 0);
3122 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
, 0);
3124 if (has_msr_hv_crash
) {
3127 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++) {
3128 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
3131 if (has_msr_hv_runtime
) {
3132 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
3134 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
3137 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
3138 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
3139 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
3140 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
3141 kvm_msr_entry_add(cpu
, msr
, 0);
3144 if (has_msr_hv_stimer
) {
3147 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
3149 kvm_msr_entry_add(cpu
, msr
, 0);
3152 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
3153 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
3154 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
3155 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
3156 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
3157 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
3158 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
3159 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
3160 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
3161 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
3162 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
3163 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
3164 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
3165 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
3166 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
3167 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
3171 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
3173 kvm_arch_get_supported_cpuid(kvm_state
, 0x14, 1, R_EAX
) & 0x7;
3175 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
, 0);
3176 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
, 0);
3177 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
, 0);
3178 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
, 0);
3179 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
, 0);
3180 for (i
= 0; i
< addr_num
; i
++) {
3181 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
, 0);
3185 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
3190 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
3191 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
3192 error_report("error: failed to get MSR 0x%" PRIx32
,
3193 (uint32_t)e
->index
);
3196 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
3198 * MTRR masks: Each mask consists of 5 parts
3199 * a 10..0: must be zero
3201 * c n-1.12: actual mask bits
3202 * d 51..n: reserved must be zero
3203 * e 63.52: reserved must be zero
3205 * 'n' is the number of physical bits supported by the CPU and is
3206 * apparently always <= 52. We know our 'n' but don't know what
3207 * the destinations 'n' is; it might be smaller, in which case
3208 * it masks (c) on loading. It might be larger, in which case
3209 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3210 * we're migrating to.
3213 if (cpu
->fill_mtrr_mask
) {
3214 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
3215 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
3216 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
3221 for (i
= 0; i
< ret
; i
++) {
3222 uint32_t index
= msrs
[i
].index
;
3224 case MSR_IA32_SYSENTER_CS
:
3225 env
->sysenter_cs
= msrs
[i
].data
;
3227 case MSR_IA32_SYSENTER_ESP
:
3228 env
->sysenter_esp
= msrs
[i
].data
;
3230 case MSR_IA32_SYSENTER_EIP
:
3231 env
->sysenter_eip
= msrs
[i
].data
;
3234 env
->pat
= msrs
[i
].data
;
3237 env
->star
= msrs
[i
].data
;
3239 #ifdef TARGET_X86_64
3241 env
->cstar
= msrs
[i
].data
;
3243 case MSR_KERNELGSBASE
:
3244 env
->kernelgsbase
= msrs
[i
].data
;
3247 env
->fmask
= msrs
[i
].data
;
3250 env
->lstar
= msrs
[i
].data
;
3254 env
->tsc
= msrs
[i
].data
;
3257 env
->tsc_aux
= msrs
[i
].data
;
3259 case MSR_TSC_ADJUST
:
3260 env
->tsc_adjust
= msrs
[i
].data
;
3262 case MSR_IA32_TSCDEADLINE
:
3263 env
->tsc_deadline
= msrs
[i
].data
;
3265 case MSR_VM_HSAVE_PA
:
3266 env
->vm_hsave
= msrs
[i
].data
;
3268 case MSR_KVM_SYSTEM_TIME
:
3269 env
->system_time_msr
= msrs
[i
].data
;
3271 case MSR_KVM_WALL_CLOCK
:
3272 env
->wall_clock_msr
= msrs
[i
].data
;
3274 case MSR_MCG_STATUS
:
3275 env
->mcg_status
= msrs
[i
].data
;
3278 env
->mcg_ctl
= msrs
[i
].data
;
3280 case MSR_MCG_EXT_CTL
:
3281 env
->mcg_ext_ctl
= msrs
[i
].data
;
3283 case MSR_IA32_MISC_ENABLE
:
3284 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
3286 case MSR_IA32_SMBASE
:
3287 env
->smbase
= msrs
[i
].data
;
3290 env
->msr_smi_count
= msrs
[i
].data
;
3292 case MSR_IA32_FEATURE_CONTROL
:
3293 env
->msr_ia32_feature_control
= msrs
[i
].data
;
3295 case MSR_IA32_BNDCFGS
:
3296 env
->msr_bndcfgs
= msrs
[i
].data
;
3299 env
->xss
= msrs
[i
].data
;
3302 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
3303 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
3304 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
3307 case MSR_KVM_ASYNC_PF_EN
:
3308 env
->async_pf_en_msr
= msrs
[i
].data
;
3310 case MSR_KVM_PV_EOI_EN
:
3311 env
->pv_eoi_en_msr
= msrs
[i
].data
;
3313 case MSR_KVM_STEAL_TIME
:
3314 env
->steal_time_msr
= msrs
[i
].data
;
3316 case MSR_KVM_POLL_CONTROL
: {
3317 env
->poll_control_msr
= msrs
[i
].data
;
3320 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
3321 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
3323 case MSR_CORE_PERF_GLOBAL_CTRL
:
3324 env
->msr_global_ctrl
= msrs
[i
].data
;
3326 case MSR_CORE_PERF_GLOBAL_STATUS
:
3327 env
->msr_global_status
= msrs
[i
].data
;
3329 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
3330 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
3332 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
3333 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
3335 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
3336 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
3338 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
3339 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
3341 case HV_X64_MSR_HYPERCALL
:
3342 env
->msr_hv_hypercall
= msrs
[i
].data
;
3344 case HV_X64_MSR_GUEST_OS_ID
:
3345 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
3347 case HV_X64_MSR_APIC_ASSIST_PAGE
:
3348 env
->msr_hv_vapic
= msrs
[i
].data
;
3350 case HV_X64_MSR_REFERENCE_TSC
:
3351 env
->msr_hv_tsc
= msrs
[i
].data
;
3353 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
3354 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
3356 case HV_X64_MSR_VP_RUNTIME
:
3357 env
->msr_hv_runtime
= msrs
[i
].data
;
3359 case HV_X64_MSR_SCONTROL
:
3360 env
->msr_hv_synic_control
= msrs
[i
].data
;
3362 case HV_X64_MSR_SIEFP
:
3363 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
3365 case HV_X64_MSR_SIMP
:
3366 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
3368 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
3369 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
3371 case HV_X64_MSR_STIMER0_CONFIG
:
3372 case HV_X64_MSR_STIMER1_CONFIG
:
3373 case HV_X64_MSR_STIMER2_CONFIG
:
3374 case HV_X64_MSR_STIMER3_CONFIG
:
3375 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
3378 case HV_X64_MSR_STIMER0_COUNT
:
3379 case HV_X64_MSR_STIMER1_COUNT
:
3380 case HV_X64_MSR_STIMER2_COUNT
:
3381 case HV_X64_MSR_STIMER3_COUNT
:
3382 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
3385 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
3386 env
->msr_hv_reenlightenment_control
= msrs
[i
].data
;
3388 case HV_X64_MSR_TSC_EMULATION_CONTROL
:
3389 env
->msr_hv_tsc_emulation_control
= msrs
[i
].data
;
3391 case HV_X64_MSR_TSC_EMULATION_STATUS
:
3392 env
->msr_hv_tsc_emulation_status
= msrs
[i
].data
;
3394 case MSR_MTRRdefType
:
3395 env
->mtrr_deftype
= msrs
[i
].data
;
3397 case MSR_MTRRfix64K_00000
:
3398 env
->mtrr_fixed
[0] = msrs
[i
].data
;
3400 case MSR_MTRRfix16K_80000
:
3401 env
->mtrr_fixed
[1] = msrs
[i
].data
;
3403 case MSR_MTRRfix16K_A0000
:
3404 env
->mtrr_fixed
[2] = msrs
[i
].data
;
3406 case MSR_MTRRfix4K_C0000
:
3407 env
->mtrr_fixed
[3] = msrs
[i
].data
;
3409 case MSR_MTRRfix4K_C8000
:
3410 env
->mtrr_fixed
[4] = msrs
[i
].data
;
3412 case MSR_MTRRfix4K_D0000
:
3413 env
->mtrr_fixed
[5] = msrs
[i
].data
;
3415 case MSR_MTRRfix4K_D8000
:
3416 env
->mtrr_fixed
[6] = msrs
[i
].data
;
3418 case MSR_MTRRfix4K_E0000
:
3419 env
->mtrr_fixed
[7] = msrs
[i
].data
;
3421 case MSR_MTRRfix4K_E8000
:
3422 env
->mtrr_fixed
[8] = msrs
[i
].data
;
3424 case MSR_MTRRfix4K_F0000
:
3425 env
->mtrr_fixed
[9] = msrs
[i
].data
;
3427 case MSR_MTRRfix4K_F8000
:
3428 env
->mtrr_fixed
[10] = msrs
[i
].data
;
3430 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
3432 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
3435 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
3438 case MSR_IA32_SPEC_CTRL
:
3439 env
->spec_ctrl
= msrs
[i
].data
;
3442 env
->virt_ssbd
= msrs
[i
].data
;
3444 case MSR_IA32_RTIT_CTL
:
3445 env
->msr_rtit_ctrl
= msrs
[i
].data
;
3447 case MSR_IA32_RTIT_STATUS
:
3448 env
->msr_rtit_status
= msrs
[i
].data
;
3450 case MSR_IA32_RTIT_OUTPUT_BASE
:
3451 env
->msr_rtit_output_base
= msrs
[i
].data
;
3453 case MSR_IA32_RTIT_OUTPUT_MASK
:
3454 env
->msr_rtit_output_mask
= msrs
[i
].data
;
3456 case MSR_IA32_RTIT_CR3_MATCH
:
3457 env
->msr_rtit_cr3_match
= msrs
[i
].data
;
3459 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
3460 env
->msr_rtit_addrs
[index
- MSR_IA32_RTIT_ADDR0_A
] = msrs
[i
].data
;
3468 static int kvm_put_mp_state(X86CPU
*cpu
)
3470 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
3472 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
3475 static int kvm_get_mp_state(X86CPU
*cpu
)
3477 CPUState
*cs
= CPU(cpu
);
3478 CPUX86State
*env
= &cpu
->env
;
3479 struct kvm_mp_state mp_state
;
3482 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
3486 env
->mp_state
= mp_state
.mp_state
;
3487 if (kvm_irqchip_in_kernel()) {
3488 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
3493 static int kvm_get_apic(X86CPU
*cpu
)
3495 DeviceState
*apic
= cpu
->apic_state
;
3496 struct kvm_lapic_state kapic
;
3499 if (apic
&& kvm_irqchip_in_kernel()) {
3500 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
3505 kvm_get_apic_state(apic
, &kapic
);
3510 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
3512 CPUState
*cs
= CPU(cpu
);
3513 CPUX86State
*env
= &cpu
->env
;
3514 struct kvm_vcpu_events events
= {};
3516 if (!kvm_has_vcpu_events()) {
3522 if (has_exception_payload
) {
3523 events
.flags
|= KVM_VCPUEVENT_VALID_PAYLOAD
;
3524 events
.exception
.pending
= env
->exception_pending
;
3525 events
.exception_has_payload
= env
->exception_has_payload
;
3526 events
.exception_payload
= env
->exception_payload
;
3528 events
.exception
.nr
= env
->exception_nr
;
3529 events
.exception
.injected
= env
->exception_injected
;
3530 events
.exception
.has_error_code
= env
->has_error_code
;
3531 events
.exception
.error_code
= env
->error_code
;
3533 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
3534 events
.interrupt
.nr
= env
->interrupt_injected
;
3535 events
.interrupt
.soft
= env
->soft_interrupt
;
3537 events
.nmi
.injected
= env
->nmi_injected
;
3538 events
.nmi
.pending
= env
->nmi_pending
;
3539 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
3541 events
.sipi_vector
= env
->sipi_vector
;
3543 if (has_msr_smbase
) {
3544 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
3545 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
3546 if (kvm_irqchip_in_kernel()) {
3547 /* As soon as these are moved to the kernel, remove them
3548 * from cs->interrupt_request.
3550 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
3551 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
3552 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
3554 /* Keep these in cs->interrupt_request. */
3555 events
.smi
.pending
= 0;
3556 events
.smi
.latched_init
= 0;
3558 /* Stop SMI delivery on old machine types to avoid a reboot
3559 * on an inward migration of an old VM.
3561 if (!cpu
->kvm_no_smi_migration
) {
3562 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
3566 if (level
>= KVM_PUT_RESET_STATE
) {
3567 events
.flags
|= KVM_VCPUEVENT_VALID_NMI_PENDING
;
3568 if (env
->mp_state
== KVM_MP_STATE_SIPI_RECEIVED
) {
3569 events
.flags
|= KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
3573 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
3576 static int kvm_get_vcpu_events(X86CPU
*cpu
)
3578 CPUX86State
*env
= &cpu
->env
;
3579 struct kvm_vcpu_events events
;
3582 if (!kvm_has_vcpu_events()) {
3586 memset(&events
, 0, sizeof(events
));
3587 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
3592 if (events
.flags
& KVM_VCPUEVENT_VALID_PAYLOAD
) {
3593 env
->exception_pending
= events
.exception
.pending
;
3594 env
->exception_has_payload
= events
.exception_has_payload
;
3595 env
->exception_payload
= events
.exception_payload
;
3597 env
->exception_pending
= 0;
3598 env
->exception_has_payload
= false;
3600 env
->exception_injected
= events
.exception
.injected
;
3602 (env
->exception_pending
|| env
->exception_injected
) ?
3603 events
.exception
.nr
: -1;
3604 env
->has_error_code
= events
.exception
.has_error_code
;
3605 env
->error_code
= events
.exception
.error_code
;
3607 env
->interrupt_injected
=
3608 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
3609 env
->soft_interrupt
= events
.interrupt
.soft
;
3611 env
->nmi_injected
= events
.nmi
.injected
;
3612 env
->nmi_pending
= events
.nmi
.pending
;
3613 if (events
.nmi
.masked
) {
3614 env
->hflags2
|= HF2_NMI_MASK
;
3616 env
->hflags2
&= ~HF2_NMI_MASK
;
3619 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
3620 if (events
.smi
.smm
) {
3621 env
->hflags
|= HF_SMM_MASK
;
3623 env
->hflags
&= ~HF_SMM_MASK
;
3625 if (events
.smi
.pending
) {
3626 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3628 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3630 if (events
.smi
.smm_inside_nmi
) {
3631 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
3633 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
3635 if (events
.smi
.latched_init
) {
3636 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3638 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3642 env
->sipi_vector
= events
.sipi_vector
;
3647 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
3649 CPUState
*cs
= CPU(cpu
);
3650 CPUX86State
*env
= &cpu
->env
;
3652 unsigned long reinject_trap
= 0;
3654 if (!kvm_has_vcpu_events()) {
3655 if (env
->exception_nr
== EXCP01_DB
) {
3656 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
3657 } else if (env
->exception_injected
== EXCP03_INT3
) {
3658 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
3660 kvm_reset_exception(env
);
3664 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3665 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3666 * by updating the debug state once again if single-stepping is on.
3667 * Another reason to call kvm_update_guest_debug here is a pending debug
3668 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3669 * reinject them via SET_GUEST_DEBUG.
3671 if (reinject_trap
||
3672 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
3673 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
3678 static int kvm_put_debugregs(X86CPU
*cpu
)
3680 CPUX86State
*env
= &cpu
->env
;
3681 struct kvm_debugregs dbgregs
;
3684 if (!kvm_has_debugregs()) {
3688 memset(&dbgregs
, 0, sizeof(dbgregs
));
3689 for (i
= 0; i
< 4; i
++) {
3690 dbgregs
.db
[i
] = env
->dr
[i
];
3692 dbgregs
.dr6
= env
->dr
[6];
3693 dbgregs
.dr7
= env
->dr
[7];
3696 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
3699 static int kvm_get_debugregs(X86CPU
*cpu
)
3701 CPUX86State
*env
= &cpu
->env
;
3702 struct kvm_debugregs dbgregs
;
3705 if (!kvm_has_debugregs()) {
3709 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
3713 for (i
= 0; i
< 4; i
++) {
3714 env
->dr
[i
] = dbgregs
.db
[i
];
3716 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
3717 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
3722 static int kvm_put_nested_state(X86CPU
*cpu
)
3724 CPUX86State
*env
= &cpu
->env
;
3725 int max_nested_state_len
= kvm_max_nested_state_length();
3727 if (!env
->nested_state
) {
3731 assert(env
->nested_state
->size
<= max_nested_state_len
);
3732 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_NESTED_STATE
, env
->nested_state
);
3735 static int kvm_get_nested_state(X86CPU
*cpu
)
3737 CPUX86State
*env
= &cpu
->env
;
3738 int max_nested_state_len
= kvm_max_nested_state_length();
3741 if (!env
->nested_state
) {
3746 * It is possible that migration restored a smaller size into
3747 * nested_state->hdr.size than what our kernel support.
3748 * We preserve migration origin nested_state->hdr.size for
3749 * call to KVM_SET_NESTED_STATE but wish that our next call
3750 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3752 env
->nested_state
->size
= max_nested_state_len
;
3754 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_NESTED_STATE
, env
->nested_state
);
3759 if (env
->nested_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
) {
3760 env
->hflags
|= HF_GUEST_MASK
;
3762 env
->hflags
&= ~HF_GUEST_MASK
;
3768 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
3770 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3773 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
3775 if (level
>= KVM_PUT_RESET_STATE
) {
3776 ret
= kvm_put_nested_state(x86_cpu
);
3781 ret
= kvm_put_msr_feature_control(x86_cpu
);
3787 if (level
== KVM_PUT_FULL_STATE
) {
3788 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3789 * because TSC frequency mismatch shouldn't abort migration,
3790 * unless the user explicitly asked for a more strict TSC
3791 * setting (e.g. using an explicit "tsc-freq" option).
3793 kvm_arch_set_tsc_khz(cpu
);
3796 ret
= kvm_getput_regs(x86_cpu
, 1);
3800 ret
= kvm_put_xsave(x86_cpu
);
3804 ret
= kvm_put_xcrs(x86_cpu
);
3808 ret
= kvm_put_sregs(x86_cpu
);
3812 /* must be before kvm_put_msrs */
3813 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
3817 ret
= kvm_put_msrs(x86_cpu
, level
);
3821 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
3825 if (level
>= KVM_PUT_RESET_STATE
) {
3826 ret
= kvm_put_mp_state(x86_cpu
);
3832 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
3836 ret
= kvm_put_debugregs(x86_cpu
);
3841 ret
= kvm_guest_debug_workarounds(x86_cpu
);
3848 int kvm_arch_get_registers(CPUState
*cs
)
3850 X86CPU
*cpu
= X86_CPU(cs
);
3853 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
3855 ret
= kvm_get_vcpu_events(cpu
);
3860 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3861 * KVM_GET_REGS and KVM_GET_SREGS.
3863 ret
= kvm_get_mp_state(cpu
);
3867 ret
= kvm_getput_regs(cpu
, 0);
3871 ret
= kvm_get_xsave(cpu
);
3875 ret
= kvm_get_xcrs(cpu
);
3879 ret
= kvm_get_sregs(cpu
);
3883 ret
= kvm_get_msrs(cpu
);
3887 ret
= kvm_get_apic(cpu
);
3891 ret
= kvm_get_debugregs(cpu
);
3895 ret
= kvm_get_nested_state(cpu
);
3901 cpu_sync_bndcs_hflags(&cpu
->env
);
3905 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
3907 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3908 CPUX86State
*env
= &x86_cpu
->env
;
3912 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
3913 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
3914 qemu_mutex_lock_iothread();
3915 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
3916 qemu_mutex_unlock_iothread();
3917 DPRINTF("injected NMI\n");
3918 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
3920 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
3924 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
3925 qemu_mutex_lock_iothread();
3926 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
3927 qemu_mutex_unlock_iothread();
3928 DPRINTF("injected SMI\n");
3929 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
3931 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
3937 if (!kvm_pic_in_kernel()) {
3938 qemu_mutex_lock_iothread();
3941 /* Force the VCPU out of its inner loop to process any INIT requests
3942 * or (for userspace APIC, but it is cheap to combine the checks here)
3943 * pending TPR access reports.
3945 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
3946 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
3947 !(env
->hflags
& HF_SMM_MASK
)) {
3948 cpu
->exit_request
= 1;
3950 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
3951 cpu
->exit_request
= 1;
3955 if (!kvm_pic_in_kernel()) {
3956 /* Try to inject an interrupt if the guest can accept it */
3957 if (run
->ready_for_interrupt_injection
&&
3958 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
3959 (env
->eflags
& IF_MASK
)) {
3962 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
3963 irq
= cpu_get_pic_interrupt(env
);
3965 struct kvm_interrupt intr
;
3968 DPRINTF("injected interrupt %d\n", irq
);
3969 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
3972 "KVM: injection failed, interrupt lost (%s)\n",
3978 /* If we have an interrupt but the guest is not ready to receive an
3979 * interrupt, request an interrupt window exit. This will
3980 * cause a return to userspace as soon as the guest is ready to
3981 * receive interrupts. */
3982 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
3983 run
->request_interrupt_window
= 1;
3985 run
->request_interrupt_window
= 0;
3988 DPRINTF("setting tpr\n");
3989 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
3991 qemu_mutex_unlock_iothread();
3995 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
3997 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3998 CPUX86State
*env
= &x86_cpu
->env
;
4000 if (run
->flags
& KVM_RUN_X86_SMM
) {
4001 env
->hflags
|= HF_SMM_MASK
;
4003 env
->hflags
&= ~HF_SMM_MASK
;
4006 env
->eflags
|= IF_MASK
;
4008 env
->eflags
&= ~IF_MASK
;
4011 /* We need to protect the apic state against concurrent accesses from
4012 * different threads in case the userspace irqchip is used. */
4013 if (!kvm_irqchip_in_kernel()) {
4014 qemu_mutex_lock_iothread();
4016 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
4017 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
4018 if (!kvm_irqchip_in_kernel()) {
4019 qemu_mutex_unlock_iothread();
4021 return cpu_get_mem_attrs(env
);
4024 int kvm_arch_process_async_events(CPUState
*cs
)
4026 X86CPU
*cpu
= X86_CPU(cs
);
4027 CPUX86State
*env
= &cpu
->env
;
4029 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
4030 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4031 assert(env
->mcg_cap
);
4033 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
4035 kvm_cpu_synchronize_state(cs
);
4037 if (env
->exception_nr
== EXCP08_DBLE
) {
4038 /* this means triple fault */
4039 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
4040 cs
->exit_request
= 1;
4043 kvm_queue_exception(env
, EXCP12_MCHK
, 0, 0);
4044 env
->has_error_code
= 0;
4047 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
4048 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
4052 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
4053 !(env
->hflags
& HF_SMM_MASK
)) {
4054 kvm_cpu_synchronize_state(cs
);
4058 if (kvm_irqchip_in_kernel()) {
4062 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
4063 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
4064 apic_poll_irq(cpu
->apic_state
);
4066 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4067 (env
->eflags
& IF_MASK
)) ||
4068 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4071 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
4072 kvm_cpu_synchronize_state(cs
);
4075 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
4076 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
4077 kvm_cpu_synchronize_state(cs
);
4078 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
4079 env
->tpr_access_type
);
4085 static int kvm_handle_halt(X86CPU
*cpu
)
4087 CPUState
*cs
= CPU(cpu
);
4088 CPUX86State
*env
= &cpu
->env
;
4090 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4091 (env
->eflags
& IF_MASK
)) &&
4092 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4100 static int kvm_handle_tpr_access(X86CPU
*cpu
)
4102 CPUState
*cs
= CPU(cpu
);
4103 struct kvm_run
*run
= cs
->kvm_run
;
4105 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
4106 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
4111 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4113 static const uint8_t int3
= 0xcc;
4115 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
4116 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
4122 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4126 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
4127 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
4139 static int nb_hw_breakpoint
;
4141 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
4145 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4146 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
4147 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
4154 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
4155 target_ulong len
, int type
)
4158 case GDB_BREAKPOINT_HW
:
4161 case GDB_WATCHPOINT_WRITE
:
4162 case GDB_WATCHPOINT_ACCESS
:
4169 if (addr
& (len
- 1)) {
4181 if (nb_hw_breakpoint
== 4) {
4184 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
4187 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
4188 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
4189 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
4195 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
4196 target_ulong len
, int type
)
4200 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
4205 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
4210 void kvm_arch_remove_all_hw_breakpoints(void)
4212 nb_hw_breakpoint
= 0;
4215 static CPUWatchpoint hw_watchpoint
;
4217 static int kvm_handle_debug(X86CPU
*cpu
,
4218 struct kvm_debug_exit_arch
*arch_info
)
4220 CPUState
*cs
= CPU(cpu
);
4221 CPUX86State
*env
= &cpu
->env
;
4225 if (arch_info
->exception
== EXCP01_DB
) {
4226 if (arch_info
->dr6
& DR6_BS
) {
4227 if (cs
->singlestep_enabled
) {
4231 for (n
= 0; n
< 4; n
++) {
4232 if (arch_info
->dr6
& (1 << n
)) {
4233 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
4239 cs
->watchpoint_hit
= &hw_watchpoint
;
4240 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4241 hw_watchpoint
.flags
= BP_MEM_WRITE
;
4245 cs
->watchpoint_hit
= &hw_watchpoint
;
4246 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4247 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
4253 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
4257 cpu_synchronize_state(cs
);
4258 assert(env
->exception_nr
== -1);
4261 kvm_queue_exception(env
, arch_info
->exception
,
4262 arch_info
->exception
== EXCP01_DB
,
4264 env
->has_error_code
= 0;
4270 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
4272 const uint8_t type_code
[] = {
4273 [GDB_BREAKPOINT_HW
] = 0x0,
4274 [GDB_WATCHPOINT_WRITE
] = 0x1,
4275 [GDB_WATCHPOINT_ACCESS
] = 0x3
4277 const uint8_t len_code
[] = {
4278 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4282 if (kvm_sw_breakpoints_active(cpu
)) {
4283 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
4285 if (nb_hw_breakpoint
> 0) {
4286 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
4287 dbg
->arch
.debugreg
[7] = 0x0600;
4288 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4289 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
4290 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
4291 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
4292 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
4297 static bool host_supports_vmx(void)
4299 uint32_t ecx
, unused
;
4301 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
4302 return ecx
& CPUID_EXT_VMX
;
4305 #define VMX_INVALID_GUEST_STATE 0x80000021
4307 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
4309 X86CPU
*cpu
= X86_CPU(cs
);
4313 switch (run
->exit_reason
) {
4315 DPRINTF("handle_hlt\n");
4316 qemu_mutex_lock_iothread();
4317 ret
= kvm_handle_halt(cpu
);
4318 qemu_mutex_unlock_iothread();
4320 case KVM_EXIT_SET_TPR
:
4323 case KVM_EXIT_TPR_ACCESS
:
4324 qemu_mutex_lock_iothread();
4325 ret
= kvm_handle_tpr_access(cpu
);
4326 qemu_mutex_unlock_iothread();
4328 case KVM_EXIT_FAIL_ENTRY
:
4329 code
= run
->fail_entry
.hardware_entry_failure_reason
;
4330 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
4332 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
4334 "\nIf you're running a guest on an Intel machine without "
4335 "unrestricted mode\n"
4336 "support, the failure can be most likely due to the guest "
4337 "entering an invalid\n"
4338 "state for Intel VT. For example, the guest maybe running "
4339 "in big real mode\n"
4340 "which is not supported on less recent Intel processors."
4345 case KVM_EXIT_EXCEPTION
:
4346 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
4347 run
->ex
.exception
, run
->ex
.error_code
);
4350 case KVM_EXIT_DEBUG
:
4351 DPRINTF("kvm_exit_debug\n");
4352 qemu_mutex_lock_iothread();
4353 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
4354 qemu_mutex_unlock_iothread();
4356 case KVM_EXIT_HYPERV
:
4357 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
4359 case KVM_EXIT_IOAPIC_EOI
:
4360 ioapic_eoi_broadcast(run
->eoi
.vector
);
4364 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
4372 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
4374 X86CPU
*cpu
= X86_CPU(cs
);
4375 CPUX86State
*env
= &cpu
->env
;
4377 kvm_cpu_synchronize_state(cs
);
4378 return !(env
->cr
[0] & CR0_PE_MASK
) ||
4379 ((env
->segs
[R_CS
].selector
& 3) != 3);
4382 void kvm_arch_init_irq_routing(KVMState
*s
)
4384 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
4385 /* If kernel can't do irq routing, interrupt source
4386 * override 0->2 cannot be set up as required by HPET.
4387 * So we have to disable it.
4391 /* We know at this point that we're using the in-kernel
4392 * irqchip, so we can use irqfds, and on x86 we know
4393 * we can use msi via irqfd and GSI routing.
4395 kvm_msi_via_irqfd_allowed
= true;
4396 kvm_gsi_routing_allowed
= true;
4398 if (kvm_irqchip_is_split()) {
4401 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4402 MSI routes for signaling interrupts to the local apics. */
4403 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
4404 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
4405 error_report("Could not enable split IRQ mode.");
4412 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
4415 if (machine_kernel_irqchip_split(ms
)) {
4416 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
4418 error_report("Could not enable split irqchip mode: %s",
4422 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4423 kvm_split_irqchip
= true;
4431 /* Classic KVM device assignment interface. Will remain x86 only. */
4432 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
4433 uint32_t flags
, uint32_t *dev_id
)
4435 struct kvm_assigned_pci_dev dev_data
= {
4436 .segnr
= dev_addr
->domain
,
4437 .busnr
= dev_addr
->bus
,
4438 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
4443 dev_data
.assigned_dev_id
=
4444 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
4446 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
4451 *dev_id
= dev_data
.assigned_dev_id
;
4456 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
4458 struct kvm_assigned_pci_dev dev_data
= {
4459 .assigned_dev_id
= dev_id
,
4462 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
4465 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
4466 uint32_t irq_type
, uint32_t guest_irq
)
4468 struct kvm_assigned_irq assigned_irq
= {
4469 .assigned_dev_id
= dev_id
,
4470 .guest_irq
= guest_irq
,
4474 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
4475 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
4477 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
4481 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
4484 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
4485 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
4487 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
4490 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
4492 struct kvm_assigned_pci_dev dev_data
= {
4493 .assigned_dev_id
= dev_id
,
4494 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
4497 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
4500 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
4503 struct kvm_assigned_irq assigned_irq
= {
4504 .assigned_dev_id
= dev_id
,
4508 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
4511 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
4513 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
4514 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
4517 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
4519 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
4520 KVM_DEV_IRQ_GUEST_MSI
, virq
);
4523 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
4525 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
4526 KVM_DEV_IRQ_HOST_MSI
);
4529 bool kvm_device_msix_supported(KVMState
*s
)
4531 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4532 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4533 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
4536 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
4537 uint32_t nr_vectors
)
4539 struct kvm_assigned_msix_nr msix_nr
= {
4540 .assigned_dev_id
= dev_id
,
4541 .entry_nr
= nr_vectors
,
4544 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
4547 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
4550 struct kvm_assigned_msix_entry msix_entry
= {
4551 .assigned_dev_id
= dev_id
,
4556 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
4559 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
4561 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
4562 KVM_DEV_IRQ_GUEST_MSIX
, 0);
4565 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
4567 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
4568 KVM_DEV_IRQ_HOST_MSIX
);
4571 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
4572 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
4574 X86IOMMUState
*iommu
= x86_iommu_get_default();
4578 MSIMessage src
, dst
;
4579 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
4581 if (!class->int_remap
) {
4585 src
.address
= route
->u
.msi
.address_hi
;
4586 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
4587 src
.address
|= route
->u
.msi
.address_lo
;
4588 src
.data
= route
->u
.msi
.data
;
4590 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
4591 pci_requester_id(dev
) : \
4592 X86_IOMMU_SID_INVALID
);
4594 trace_kvm_x86_fixup_msi_error(route
->gsi
);
4598 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
4599 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
4600 route
->u
.msi
.data
= dst
.data
;
4606 typedef struct MSIRouteEntry MSIRouteEntry
;
4608 struct MSIRouteEntry
{
4609 PCIDevice
*dev
; /* Device pointer */
4610 int vector
; /* MSI/MSIX vector index */
4611 int virq
; /* Virtual IRQ index */
4612 QLIST_ENTRY(MSIRouteEntry
) list
;
4615 /* List of used GSI routes */
4616 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
4617 QLIST_HEAD_INITIALIZER(msi_route_list
);
4619 static void kvm_update_msi_routes_all(void *private, bool global
,
4620 uint32_t index
, uint32_t mask
)
4622 int cnt
= 0, vector
;
4623 MSIRouteEntry
*entry
;
4627 /* TODO: explicit route update */
4628 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
4630 vector
= entry
->vector
;
4632 if (msix_enabled(dev
) && !msix_is_masked(dev
, vector
)) {
4633 msg
= msix_get_message(dev
, vector
);
4634 } else if (msi_enabled(dev
) && !msi_is_masked(dev
, vector
)) {
4635 msg
= msi_get_message(dev
, vector
);
4638 * Either MSI/MSIX is disabled for the device, or the
4639 * specific message was masked out. Skip this one.
4643 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
, msg
, dev
);
4645 kvm_irqchip_commit_routes(kvm_state
);
4646 trace_kvm_x86_update_msi_routes(cnt
);
4649 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
4650 int vector
, PCIDevice
*dev
)
4652 static bool notify_list_inited
= false;
4653 MSIRouteEntry
*entry
;
4656 /* These are (possibly) IOAPIC routes only used for split
4657 * kernel irqchip mode, while what we are housekeeping are
4658 * PCI devices only. */
4662 entry
= g_new0(MSIRouteEntry
, 1);
4664 entry
->vector
= vector
;
4665 entry
->virq
= route
->gsi
;
4666 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
4668 trace_kvm_x86_add_msi_route(route
->gsi
);
4670 if (!notify_list_inited
) {
4671 /* For the first time we do add route, add ourselves into
4672 * IOMMU's IEC notify list if needed. */
4673 X86IOMMUState
*iommu
= x86_iommu_get_default();
4675 x86_iommu_iec_register_notifier(iommu
,
4676 kvm_update_msi_routes_all
,
4679 notify_list_inited
= true;
4684 int kvm_arch_release_virq_post(int virq
)
4686 MSIRouteEntry
*entry
, *next
;
4687 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
4688 if (entry
->virq
== virq
) {
4689 trace_kvm_x86_remove_msi_route(virq
);
4690 QLIST_REMOVE(entry
, list
);
4698 int kvm_arch_msi_data_to_gsi(uint32_t data
)