hw/display/g364fb.c

   1 /*
   2  * QEMU G364 framebuffer Emulator.
   3  *
   4  * Copyright (c) 2007-2011 Herve Poussineau
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/hw.h"
  22 #include "qemu/error-report.h"
  23 #include "ui/console.h"
  24 #include "ui/pixel_ops.h"
  25 #include "trace.h"
  26 #include "hw/sysbus.h"
  27
  28 typedef struct G364State {
  29     /* hardware */
  30     uint8_t *vram;
  31     uint32_t vram_size;
  32     qemu_irq irq;
  33     MemoryRegion mem_vram;
  34     MemoryRegion mem_ctrl;
  35     /* registers */
  36     uint8_t color_palette[256][3];
  37     uint8_t cursor_palette[3][3];
  38     uint16_t cursor[512];
  39     uint32_t cursor_position;
  40     uint32_t ctla;
  41     uint32_t top_of_screen;
  42     uint32_t width, height; /* in pixels */
  43     /* display refresh support */
  44     QemuConsole *con;
  45     int depth;
  46     int blanked;
  47 } G364State;
  48
  49 #define REG_BOOT     0x000000
  50 #define REG_DISPLAY  0x000118
  51 #define REG_VDISPLAY 0x000150
  52 #define REG_CTLA     0x000300
  53 #define REG_TOP      0x000400
  54 #define REG_CURS_PAL 0x000508
  55 #define REG_CURS_POS 0x000638
  56 #define REG_CLR_PAL  0x000800
  57 #define REG_CURS_PAT 0x001000
  58 #define REG_RESET    0x100000
  59
  60 #define CTLA_FORCE_BLANK 0x00000400
  61 #define CTLA_NO_CURSOR   0x00800000
  62
  63 #define G364_PAGE_SIZE 4096
  64
  65 static inline int check_dirty(G364State *s, ram_addr_t page)
  66 {
  67     return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
  68                                    DIRTY_MEMORY_VGA);
  69 }
  70
  71 static inline void reset_dirty(G364State *s,
  72                                ram_addr_t page_min, ram_addr_t page_max)
  73 {
  74     memory_region_reset_dirty(&s->mem_vram,
  75                               page_min,
  76                               page_max + G364_PAGE_SIZE - page_min - 1,
  77                               DIRTY_MEMORY_VGA);
  78 }
  79
  80 static void g364fb_draw_graphic8(G364State *s)
  81 {
  82     DisplaySurface *surface = qemu_console_surface(s->con);
  83     int i, w;
  84     uint8_t *vram;
  85     uint8_t *data_display, *dd;
  86     ram_addr_t page, page_min, page_max;
  87     int x, y;
  88     int xmin, xmax;
  89     int ymin, ymax;
  90     int xcursor, ycursor;
  91     unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
  92
  93     switch (surface_bits_per_pixel(surface)) {
  94         case 8:
  95             rgb_to_pixel = rgb_to_pixel8;
  96             w = 1;
  97             break;
  98         case 15:
  99             rgb_to_pixel = rgb_to_pixel15;
 100             w = 2;
 101             break;
 102         case 16:
 103             rgb_to_pixel = rgb_to_pixel16;
 104             w = 2;
 105             break;
 106         case 32:
 107             rgb_to_pixel = rgb_to_pixel32;
 108             w = 4;
 109             break;
 110         default:
 111             hw_error("g364: unknown host depth %d",
 112                      surface_bits_per_pixel(surface));
 113             return;
 114     }
 115
 116     page = 0;
 117     page_min = (ram_addr_t)-1;
 118     page_max = 0;
 119
 120     x = y = 0;
 121     xmin = s->width;
 122     xmax = 0;
 123     ymin = s->height;
 124     ymax = 0;
 125
 126     if (!(s->ctla & CTLA_NO_CURSOR)) {
 127         xcursor = s->cursor_position >> 12;
 128         ycursor = s->cursor_position & 0xfff;
 129     } else {
 130         xcursor = ycursor = -65;
 131     }
 132
 133     vram = s->vram + s->top_of_screen;
 134     /* XXX: out of range in vram? */
 135     data_display = dd = surface_data(surface);
 136     while (y < s->height) {
 137         if (check_dirty(s, page)) {
 138             if (y < ymin)
 139                 ymin = ymax = y;
 140             if (page_min == (ram_addr_t)-1)
 141                 page_min = page;
 142             page_max = page;
 143             if (x < xmin)
 144                 xmin = x;
 145             for (i = 0; i < G364_PAGE_SIZE; i++) {
 146                 uint8_t index;
 147                 unsigned int color;
 148                 if (unlikely((y >= ycursor && y < ycursor + 64) &&
 149                     (x >= xcursor && x < xcursor + 64))) {
 150                     /* pointer area */
 151                     int xdiff = x - xcursor;
 152                     uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
 153                     int op = (curs >> ((xdiff & 7) * 2)) & 3;
 154                     if (likely(op == 0)) {
 155                         /* transparent */
 156                         index = *vram;
 157                         color = (*rgb_to_pixel)(
 158                             s->color_palette[index][0],
 159                             s->color_palette[index][1],
 160                             s->color_palette[index][2]);
 161                     } else {
 162                         /* get cursor color */
 163                         index = op - 1;
 164                         color = (*rgb_to_pixel)(
 165                             s->cursor_palette[index][0],
 166                             s->cursor_palette[index][1],
 167                             s->cursor_palette[index][2]);
 168                     }
 169                 } else {
 170                     /* normal area */
 171                     index = *vram;
 172                     color = (*rgb_to_pixel)(
 173                         s->color_palette[index][0],
 174                         s->color_palette[index][1],
 175                         s->color_palette[index][2]);
 176                 }
 177                 memcpy(dd, &color, w);
 178                 dd += w;
 179                 x++;
 180                 vram++;
 181                 if (x == s->width) {
 182                     xmax = s->width - 1;
 183                     y++;
 184                     if (y == s->height) {
 185                         ymax = s->height - 1;
 186                         goto done;
 187                     }
 188                     data_display = dd = data_display + surface_stride(surface);
 189                     xmin = 0;
 190                     x = 0;
 191                 }
 192             }
 193             if (x > xmax)
 194                 xmax = x;
 195             if (y > ymax)
 196                 ymax = y;
 197         } else {
 198             int dy;
 199             if (page_min != (ram_addr_t)-1) {
 200                 reset_dirty(s, page_min, page_max);
 201                 page_min = (ram_addr_t)-1;
 202                 page_max = 0;
 203                 dpy_gfx_update(s->con, xmin, ymin,
 204                                xmax - xmin + 1, ymax - ymin + 1);
 205                 xmin = s->width;
 206                 xmax = 0;
 207                 ymin = s->height;
 208                 ymax = 0;
 209             }
 210             x += G364_PAGE_SIZE;
 211             dy = x / s->width;
 212             x = x % s->width;
 213             y += dy;
 214             vram += G364_PAGE_SIZE;
 215             data_display += dy * surface_stride(surface);
 216             dd = data_display + x * w;
 217         }
 218         page += G364_PAGE_SIZE;
 219     }
 220
 221 done:
 222     if (page_min != (ram_addr_t)-1) {
 223         dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
 224         reset_dirty(s, page_min, page_max);
 225     }
 226 }
 227
 228 static void g364fb_draw_blank(G364State *s)
 229 {
 230     DisplaySurface *surface = qemu_console_surface(s->con);
 231     int i, w;
 232     uint8_t *d;
 233
 234     if (s->blanked) {
 235         /* Screen is already blank. No need to redraw it */
 236         return;
 237     }
 238
 239     w = s->width * surface_bytes_per_pixel(surface);
 240     d = surface_data(surface);
 241     for (i = 0; i < s->height; i++) {
 242         memset(d, 0, w);
 243         d += surface_stride(surface);
 244     }
 245
 246     dpy_gfx_update(s->con, 0, 0, s->width, s->height);
 247     s->blanked = 1;
 248 }
 249
 250 static void g364fb_update_display(void *opaque)
 251 {
 252     G364State *s = opaque;
 253     DisplaySurface *surface = qemu_console_surface(s->con);
 254
 255     qemu_flush_coalesced_mmio_buffer();
 256
 257     if (s->width == 0 || s->height == 0)
 258         return;
 259
 260     if (s->width != surface_width(surface) ||
 261         s->height != surface_height(surface)) {
 262         qemu_console_resize(s->con, s->width, s->height);
 263     }
 264
 265     memory_region_sync_dirty_bitmap(&s->mem_vram);
 266     if (s->ctla & CTLA_FORCE_BLANK) {
 267         g364fb_draw_blank(s);
 268     } else if (s->depth == 8) {
 269         g364fb_draw_graphic8(s);
 270     } else {
 271         error_report("g364: unknown guest depth %d", s->depth);
 272     }
 273
 274     qemu_irq_raise(s->irq);
 275 }
 276
 277 static inline void g364fb_invalidate_display(void *opaque)
 278 {
 279     G364State *s = opaque;
 280
 281     s->blanked = 0;
 282     memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
 283 }
 284
 285 static void g364fb_reset(G364State *s)
 286 {
 287     qemu_irq_lower(s->irq);
 288
 289     memset(s->color_palette, 0, sizeof(s->color_palette));
 290     memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
 291     memset(s->cursor, 0, sizeof(s->cursor));
 292     s->cursor_position = 0;
 293     s->ctla = 0;
 294     s->top_of_screen = 0;
 295     s->width = s->height = 0;
 296     memset(s->vram, 0, s->vram_size);
 297     g364fb_invalidate_display(s);
 298 }
 299
 300 /* called for accesses to io ports */
 301 static uint64_t g364fb_ctrl_read(void *opaque,
 302                                  hwaddr addr,
 303                                  unsigned int size)
 304 {
 305     G364State *s = opaque;
 306     uint32_t val;
 307
 308     if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
 309         /* cursor pattern */
 310         int idx = (addr - REG_CURS_PAT) >> 3;
 311         val = s->cursor[idx];
 312     } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
 313         /* cursor palette */
 314         int idx = (addr - REG_CURS_PAL) >> 3;
 315         val = ((uint32_t)s->cursor_palette[idx][0] << 16);
 316         val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
 317         val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
 318     } else {
 319         switch (addr) {
 320             case REG_DISPLAY:
 321                 val = s->width / 4;
 322                 break;
 323             case REG_VDISPLAY:
 324                 val = s->height * 2;
 325                 break;
 326             case REG_CTLA:
 327                 val = s->ctla;
 328                 break;
 329             default:
 330             {
 331                 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
 332                              addr);
 333                 val = 0;
 334                 break;
 335             }
 336         }
 337     }
 338
 339     trace_g364fb_read(addr, val);
 340
 341     return val;
 342 }
 343
 344 static void g364fb_update_depth(G364State *s)
 345 {
 346     static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
 347     s->depth = depths[(s->ctla & 0x00700000) >> 20];
 348 }
 349
 350 static void g364_invalidate_cursor_position(G364State *s)
 351 {
 352     DisplaySurface *surface = qemu_console_surface(s->con);
 353     int ymin, ymax, start, end;
 354
 355     /* invalidate only near the cursor */
 356     ymin = s->cursor_position & 0xfff;
 357     ymax = MIN(s->height, ymin + 64);
 358     start = ymin * surface_stride(surface);
 359     end = (ymax + 1) * surface_stride(surface);
 360
 361     memory_region_set_dirty(&s->mem_vram, start, end - start);
 362 }
 363
 364 static void g364fb_ctrl_write(void *opaque,
 365                               hwaddr addr,
 366                               uint64_t val,
 367                               unsigned int size)
 368 {
 369     G364State *s = opaque;
 370
 371     trace_g364fb_write(addr, val);
 372
 373     if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
 374         /* color palette */
 375         int idx = (addr - REG_CLR_PAL) >> 3;
 376         s->color_palette[idx][0] = (val >> 16) & 0xff;
 377         s->color_palette[idx][1] = (val >> 8) & 0xff;
 378         s->color_palette[idx][2] = val & 0xff;
 379         g364fb_invalidate_display(s);
 380     } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
 381         /* cursor pattern */
 382         int idx = (addr - REG_CURS_PAT) >> 3;
 383         s->cursor[idx] = val;
 384         g364fb_invalidate_display(s);
 385     } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
 386         /* cursor palette */
 387         int idx = (addr - REG_CURS_PAL) >> 3;
 388         s->cursor_palette[idx][0] = (val >> 16) & 0xff;
 389         s->cursor_palette[idx][1] = (val >> 8) & 0xff;
 390         s->cursor_palette[idx][2] = val & 0xff;
 391         g364fb_invalidate_display(s);
 392     } else {
 393         switch (addr) {
 394         case REG_BOOT: /* Boot timing */
 395         case 0x00108: /* Line timing: half sync */
 396         case 0x00110: /* Line timing: back porch */
 397         case 0x00120: /* Line timing: short display */
 398         case 0x00128: /* Frame timing: broad pulse */
 399         case 0x00130: /* Frame timing: v sync */
 400         case 0x00138: /* Frame timing: v preequalise */
 401         case 0x00140: /* Frame timing: v postequalise */
 402         case 0x00148: /* Frame timing: v blank */
 403         case 0x00158: /* Line timing: line time */
 404         case 0x00160: /* Frame store: line start */
 405         case 0x00168: /* vram cycle: mem init */
 406         case 0x00170: /* vram cycle: transfer delay */
 407         case 0x00200: /* vram cycle: mask register */
 408             /* ignore */
 409             break;
 410         case REG_TOP:
 411             s->top_of_screen = val;
 412             g364fb_invalidate_display(s);
 413             break;
 414         case REG_DISPLAY:
 415             s->width = val * 4;
 416             break;
 417         case REG_VDISPLAY:
 418             s->height = val / 2;
 419             break;
 420         case REG_CTLA:
 421             s->ctla = val;
 422             g364fb_update_depth(s);
 423             g364fb_invalidate_display(s);
 424             break;
 425         case REG_CURS_POS:
 426             g364_invalidate_cursor_position(s);
 427             s->cursor_position = val;
 428             g364_invalidate_cursor_position(s);
 429             break;
 430         case REG_RESET:
 431             g364fb_reset(s);
 432             break;
 433         default:
 434             error_report("g364: invalid write of 0x%" PRIx64
 435                          " at [" TARGET_FMT_plx "]", val, addr);
 436             break;
 437         }
 438     }
 439     qemu_irq_lower(s->irq);
 440 }
 441
 442 static const MemoryRegionOps g364fb_ctrl_ops = {
 443     .read = g364fb_ctrl_read,
 444     .write = g364fb_ctrl_write,
 445     .endianness = DEVICE_LITTLE_ENDIAN,
 446     .impl.min_access_size = 4,
 447     .impl.max_access_size = 4,
 448 };
 449
 450 static int g364fb_post_load(void *opaque, int version_id)
 451 {
 452     G364State *s = opaque;
 453
 454     /* force refresh */
 455     g364fb_update_depth(s);
 456     g364fb_invalidate_display(s);
 457
 458     return 0;
 459 }
 460
 461 static const VMStateDescription vmstate_g364fb = {
 462     .name = "g364fb",
 463     .version_id = 1,
 464     .minimum_version_id = 1,
 465     .post_load = g364fb_post_load,
 466     .fields = (VMStateField[]) {
 467         VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
 468         VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
 469         VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
 470         VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
 471         VMSTATE_UINT32(cursor_position, G364State),
 472         VMSTATE_UINT32(ctla, G364State),
 473         VMSTATE_UINT32(top_of_screen, G364State),
 474         VMSTATE_UINT32(width, G364State),
 475         VMSTATE_UINT32(height, G364State),
 476         VMSTATE_END_OF_LIST()
 477     }
 478 };
 479
 480 static const GraphicHwOps g364fb_ops = {
 481     .invalidate  = g364fb_invalidate_display,
 482     .gfx_update  = g364fb_update_display,
 483 };
 484
 485 static void g364fb_init(DeviceState *dev, G364State *s)
 486 {
 487     s->vram = g_malloc0(s->vram_size);
 488
 489     s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
 490
 491     memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
 492     memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
 493                                s->vram_size, s->vram);
 494     vmstate_register_ram(&s->mem_vram, dev);
 495     memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA);
 496 }
 497
 498 #define TYPE_G364 "sysbus-g364"
 499 #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364)
 500
 501 typedef struct {
 502     SysBusDevice parent_obj;
 503
 504     G364State g364;
 505 } G364SysBusState;
 506
 507 static int g364fb_sysbus_init(SysBusDevice *sbd)
 508 {
 509     DeviceState *dev = DEVICE(sbd);
 510     G364SysBusState *sbs = G364(dev);
 511     G364State *s = &sbs->g364;
 512
 513     g364fb_init(dev, s);
 514     sysbus_init_irq(sbd, &s->irq);
 515     sysbus_init_mmio(sbd, &s->mem_ctrl);
 516     sysbus_init_mmio(sbd, &s->mem_vram);
 517
 518     return 0;
 519 }
 520
 521 static void g364fb_sysbus_reset(DeviceState *d)
 522 {
 523     G364SysBusState *s = G364(d);
 524
 525     g364fb_reset(&s->g364);
 526 }
 527
 528 static Property g364fb_sysbus_properties[] = {
 529     DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size,
 530     8 * 1024 * 1024),
 531     DEFINE_PROP_END_OF_LIST(),
 532 };
 533
 534 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
 535 {
 536     DeviceClass *dc = DEVICE_CLASS(klass);
 537     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 538
 539     k->init = g364fb_sysbus_init;
 540     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 541     dc->desc = "G364 framebuffer";
 542     dc->reset = g364fb_sysbus_reset;
 543     dc->vmsd = &vmstate_g364fb;
 544     dc->props = g364fb_sysbus_properties;
 545 }
 546
 547 static const TypeInfo g364fb_sysbus_info = {
 548     .name          = TYPE_G364,
 549     .parent        = TYPE_SYS_BUS_DEVICE,
 550     .instance_size = sizeof(G364SysBusState),
 551     .class_init    = g364fb_sysbus_class_init,
 552 };
 553
 554 static void g364fb_register_types(void)
 555 {
 556     type_register_static(&g364fb_sysbus_info);
 557 }
 558
 559 type_init(g364fb_register_types)