hw/display/cg3.c

   1 /*
   2  * QEMU CG3 Frame buffer
   3  *
   4  * Copyright (c) 2012 Bob Breuer
   5  * Copyright (c) 2013 Mark Cave-Ayland
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu-common.h"
  28 #include "qapi/error.h"
  29 #include "qemu/error-report.h"
  30 #include "ui/console.h"
  31 #include "hw/sysbus.h"
  32 #include "migration/vmstate.h"
  33 #include "hw/irq.h"
  34 #include "hw/loader.h"
  35 #include "hw/qdev-properties.h"
  36 #include "qemu/log.h"
  37 #include "qemu/module.h"
  38
  39 /* Change to 1 to enable debugging */
  40 #define DEBUG_CG3 0
  41
  42 #define CG3_ROM_FILE  "QEMU,cgthree.bin"
  43 #define FCODE_MAX_ROM_SIZE 0x10000
  44
  45 #define CG3_REG_SIZE            0x20
  46
  47 #define CG3_REG_BT458_ADDR      0x0
  48 #define CG3_REG_BT458_COLMAP    0x4
  49 #define CG3_REG_FBC_CTRL        0x10
  50 #define CG3_REG_FBC_STATUS      0x11
  51 #define CG3_REG_FBC_CURSTART    0x12
  52 #define CG3_REG_FBC_CUREND      0x13
  53 #define CG3_REG_FBC_VCTRL       0x14
  54
  55 /* Control register flags */
  56 #define CG3_CR_ENABLE_INTS      0x80
  57
  58 /* Status register flags */
  59 #define CG3_SR_PENDING_INT      0x80
  60 #define CG3_SR_1152_900_76_B    0x60
  61 #define CG3_SR_ID_COLOR         0x01
  62
  63 #define CG3_VRAM_SIZE 0x100000
  64 #define CG3_VRAM_OFFSET 0x800000
  65
  66 #define DPRINTF(fmt, ...) do { \
  67     if (DEBUG_CG3) { \
  68         printf("CG3: " fmt , ## __VA_ARGS__); \
  69     } \
  70 } while (0)
  71
  72 #define TYPE_CG3 "cgthree"
  73 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
  74
  75 typedef struct CG3State {
  76     SysBusDevice parent_obj;
  77
  78     QemuConsole *con;
  79     qemu_irq irq;
  80     hwaddr prom_addr;
  81     MemoryRegion vram_mem;
  82     MemoryRegion rom;
  83     MemoryRegion reg;
  84     uint32_t vram_size;
  85     int full_update;
  86     uint8_t regs[16];
  87     uint8_t r[256], g[256], b[256];
  88     uint16_t width, height, depth;
  89     uint8_t dac_index, dac_state;
  90 } CG3State;
  91
  92 static void cg3_update_display(void *opaque)
  93 {
  94     CG3State *s = opaque;
  95     DisplaySurface *surface = qemu_console_surface(s->con);
  96     const uint8_t *pix;
  97     uint32_t *data;
  98     uint32_t dval;
  99     int x, y, y_start;
 100     unsigned int width, height;
 101     ram_addr_t page;
 102     DirtyBitmapSnapshot *snap = NULL;
 103
 104     if (surface_bits_per_pixel(surface) != 32) {
 105         return;
 106     }
 107     width = s->width;
 108     height = s->height;
 109
 110     y_start = -1;
 111     pix = memory_region_get_ram_ptr(&s->vram_mem);
 112     data = (uint32_t *)surface_data(surface);
 113
 114     if (!s->full_update) {
 115         snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0,
 116                                               memory_region_size(&s->vram_mem),
 117                                               DIRTY_MEMORY_VGA);
 118     }
 119
 120     for (y = 0; y < height; y++) {
 121         int update;
 122
 123         page = (ram_addr_t)y * width;
 124
 125         if (s->full_update) {
 126             update = 1;
 127         } else {
 128             update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page,
 129                                                       width);
 130         }
 131
 132         if (update) {
 133             if (y_start < 0) {
 134                 y_start = y;
 135             }
 136
 137             for (x = 0; x < width; x++) {
 138                 dval = *pix++;
 139                 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
 140                 *data++ = dval;
 141             }
 142         } else {
 143             if (y_start >= 0) {
 144                 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
 145                 y_start = -1;
 146             }
 147             pix += width;
 148             data += width;
 149         }
 150     }
 151     s->full_update = 0;
 152     if (y_start >= 0) {
 153         dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
 154     }
 155     /* vsync interrupt? */
 156     if (s->regs[0] & CG3_CR_ENABLE_INTS) {
 157         s->regs[1] |= CG3_SR_PENDING_INT;
 158         qemu_irq_raise(s->irq);
 159     }
 160     g_free(snap);
 161 }
 162
 163 static void cg3_invalidate_display(void *opaque)
 164 {
 165     CG3State *s = opaque;
 166
 167     memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
 168 }
 169
 170 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
 171 {
 172     CG3State *s = opaque;
 173     int val;
 174
 175     switch (addr) {
 176     case CG3_REG_BT458_ADDR:
 177     case CG3_REG_BT458_COLMAP:
 178         val = 0;
 179         break;
 180     case CG3_REG_FBC_CTRL:
 181         val = s->regs[0];
 182         break;
 183     case CG3_REG_FBC_STATUS:
 184         /* monitor ID 6, board type = 1 (color) */
 185         val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
 186         break;
 187     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
 188         val = s->regs[addr - 0x10];
 189         break;
 190     default:
 191         qemu_log_mask(LOG_UNIMP,
 192                   "cg3: Unimplemented register read "
 193                   "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 194                   addr, size);
 195         val = 0;
 196         break;
 197     }
 198     DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
 199     return val;
 200 }
 201
 202 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
 203                           unsigned size)
 204 {
 205     CG3State *s = opaque;
 206     uint8_t regval;
 207     int i;
 208
 209     DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
 210             val, addr, size);
 211
 212     switch (addr) {
 213     case CG3_REG_BT458_ADDR:
 214         s->dac_index = val;
 215         s->dac_state = 0;
 216         break;
 217     case CG3_REG_BT458_COLMAP:
 218         /* This register can be written to as either a long word or a byte */
 219         if (size == 1) {
 220             val <<= 24;
 221         }
 222
 223         for (i = 0; i < size; i++) {
 224             regval = val >> 24;
 225
 226             switch (s->dac_state) {
 227             case 0:
 228                 s->r[s->dac_index] = regval;
 229                 s->dac_state++;
 230                 break;
 231             case 1:
 232                 s->g[s->dac_index] = regval;
 233                 s->dac_state++;
 234                 break;
 235             case 2:
 236                 s->b[s->dac_index] = regval;
 237                 /* Index autoincrement */
 238                 s->dac_index = (s->dac_index + 1) & 0xff;
 239                 /* fall through */
 240             default:
 241                 s->dac_state = 0;
 242                 break;
 243             }
 244             val <<= 8;
 245         }
 246         s->full_update = 1;
 247         break;
 248     case CG3_REG_FBC_CTRL:
 249         s->regs[0] = val;
 250         break;
 251     case CG3_REG_FBC_STATUS:
 252         if (s->regs[1] & CG3_SR_PENDING_INT) {
 253             /* clear interrupt */
 254             s->regs[1] &= ~CG3_SR_PENDING_INT;
 255             qemu_irq_lower(s->irq);
 256         }
 257         break;
 258     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
 259         s->regs[addr - 0x10] = val;
 260         break;
 261     default:
 262         qemu_log_mask(LOG_UNIMP,
 263                   "cg3: Unimplemented register write "
 264                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 265                   addr, size, val);
 266         break;
 267     }
 268 }
 269
 270 static const MemoryRegionOps cg3_reg_ops = {
 271     .read = cg3_reg_read,
 272     .write = cg3_reg_write,
 273     .endianness = DEVICE_NATIVE_ENDIAN,
 274     .valid = {
 275         .min_access_size = 1,
 276         .max_access_size = 4,
 277     },
 278 };
 279
 280 static const GraphicHwOps cg3_ops = {
 281     .invalidate = cg3_invalidate_display,
 282     .gfx_update = cg3_update_display,
 283 };
 284
 285 static void cg3_initfn(Object *obj)
 286 {
 287     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 288     CG3State *s = CG3(obj);
 289
 290     memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom",
 291                                      FCODE_MAX_ROM_SIZE, &error_fatal);
 292     sysbus_init_mmio(sbd, &s->rom);
 293
 294     memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
 295                           CG3_REG_SIZE);
 296     sysbus_init_mmio(sbd, &s->reg);
 297 }
 298
 299 static void cg3_realizefn(DeviceState *dev, Error **errp)
 300 {
 301     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 302     CG3State *s = CG3(dev);
 303     int ret;
 304     char *fcode_filename;
 305
 306     /* FCode ROM */
 307     vmstate_register_ram_global(&s->rom);
 308     fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
 309     if (fcode_filename) {
 310         ret = load_image_mr(fcode_filename, &s->rom);
 311         g_free(fcode_filename);
 312         if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
 313             warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
 314         }
 315     }
 316
 317     memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
 318                            &error_fatal);
 319     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
 320     sysbus_init_mmio(sbd, &s->vram_mem);
 321
 322     sysbus_init_irq(sbd, &s->irq);
 323
 324     s->con = graphic_console_init(dev, 0, &cg3_ops, s);
 325     qemu_console_resize(s->con, s->width, s->height);
 326 }
 327
 328 static int vmstate_cg3_post_load(void *opaque, int version_id)
 329 {
 330     CG3State *s = opaque;
 331
 332     cg3_invalidate_display(s);
 333
 334     return 0;
 335 }
 336
 337 static const VMStateDescription vmstate_cg3 = {
 338     .name = "cg3",
 339     .version_id = 1,
 340     .minimum_version_id = 1,
 341     .post_load = vmstate_cg3_post_load,
 342     .fields = (VMStateField[]) {
 343         VMSTATE_UINT16(height, CG3State),
 344         VMSTATE_UINT16(width, CG3State),
 345         VMSTATE_UINT16(depth, CG3State),
 346         VMSTATE_BUFFER(r, CG3State),
 347         VMSTATE_BUFFER(g, CG3State),
 348         VMSTATE_BUFFER(b, CG3State),
 349         VMSTATE_UINT8(dac_index, CG3State),
 350         VMSTATE_UINT8(dac_state, CG3State),
 351         VMSTATE_END_OF_LIST()
 352     }
 353 };
 354
 355 static void cg3_reset(DeviceState *d)
 356 {
 357     CG3State *s = CG3(d);
 358
 359     /* Initialize palette */
 360     memset(s->r, 0, 256);
 361     memset(s->g, 0, 256);
 362     memset(s->b, 0, 256);
 363
 364     s->dac_state = 0;
 365     s->full_update = 1;
 366     qemu_irq_lower(s->irq);
 367 }
 368
 369 static Property cg3_properties[] = {
 370     DEFINE_PROP_UINT32("vram-size",    CG3State, vram_size, -1),
 371     DEFINE_PROP_UINT16("width",        CG3State, width,     -1),
 372     DEFINE_PROP_UINT16("height",       CG3State, height,    -1),
 373     DEFINE_PROP_UINT16("depth",        CG3State, depth,     -1),
 374     DEFINE_PROP_END_OF_LIST(),
 375 };
 376
 377 static void cg3_class_init(ObjectClass *klass, void *data)
 378 {
 379     DeviceClass *dc = DEVICE_CLASS(klass);
 380
 381     dc->realize = cg3_realizefn;
 382     dc->reset = cg3_reset;
 383     dc->vmsd = &vmstate_cg3;
 384     device_class_set_props(dc, cg3_properties);
 385 }
 386
 387 static const TypeInfo cg3_info = {
 388     .name          = TYPE_CG3,
 389     .parent        = TYPE_SYS_BUS_DEVICE,
 390     .instance_size = sizeof(CG3State),
 391     .instance_init = cg3_initfn,
 392     .class_init    = cg3_class_init,
 393 };
 394
 395 static void cg3_register_types(void)
 396 {
 397     type_register_static(&cg3_info);
 398 }
 399
 400 type_init(cg3_register_types)