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pc: acpi: pci: move link devices into SSDT
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob799efe50cdf3d1c7f4004fb6edf03dfd607ca07b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "hw/mem/nvdimm.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
56
57 #include "hw/i386/q35-acpi-dsdt.hex"
58 #include "hw/i386/acpi-dsdt.hex"
59
60 #include "hw/acpi/aml-build.h"
61
62 #include "qapi/qmp/qint.h"
63 #include "qom/qom-qobject.h"
64
65 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
66 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
67 * a little bit, there should be plenty of free space since the DSDT
68 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
69 */
70 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
71 #define ACPI_BUILD_ALIGN_SIZE 0x1000
72
73 #define ACPI_BUILD_TABLE_SIZE 0x20000
74
75 /* #define DEBUG_ACPI_BUILD */
76 #ifdef DEBUG_ACPI_BUILD
77 #define ACPI_BUILD_DPRINTF(fmt, ...) \
78 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define ACPI_BUILD_DPRINTF(fmt, ...)
81 #endif
82
83 typedef struct AcpiCpuInfo {
84 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
85 } AcpiCpuInfo;
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t cpu_hp_io_len;
105 uint16_t mem_hp_io_base;
106 uint16_t mem_hp_io_len;
107 uint16_t pcihp_io_base;
108 uint16_t pcihp_io_len;
109 } AcpiPmInfo;
110
111 typedef struct AcpiMiscInfo {
112 bool is_piix4;
113 bool has_hpet;
114 TPMVersion tpm_version;
115 const unsigned char *dsdt_code;
116 unsigned dsdt_size;
117 uint16_t pvpanic_port;
118 uint16_t applesmc_io_base;
119 } AcpiMiscInfo;
120
121 typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
125 bool pcihp_bridge_en;
126 } AcpiBuildPciBusHotplugState;
127
128 static void acpi_get_dsdt(AcpiMiscInfo *info)
129 {
130 Object *piix = piix4_pm_find();
131 Object *lpc = ich9_lpc_find();
132 assert(!!piix != !!lpc);
133
134 if (piix) {
135 info->is_piix4 = true;
136 info->dsdt_code = AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof AcpiDsdtAmlCode;
138 }
139 if (lpc) {
140 info->is_piix4 = false;
141 info->dsdt_code = Q35AcpiDsdtAmlCode;
142 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
143 }
144 }
145
146 static
147 int acpi_add_cpu_info(Object *o, void *opaque)
148 {
149 AcpiCpuInfo *cpu = opaque;
150 uint64_t apic_id;
151
152 if (object_dynamic_cast(o, TYPE_CPU)) {
153 apic_id = object_property_get_int(o, "apic-id", NULL);
154 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
155
156 set_bit(apic_id, cpu->found_cpus);
157 }
158
159 object_child_foreach(o, acpi_add_cpu_info, opaque);
160 return 0;
161 }
162
163 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
164 {
165 Object *root = object_get_root();
166
167 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
168 object_child_foreach(root, acpi_add_cpu_info, cpu);
169 }
170
171 static void acpi_get_pm_info(AcpiPmInfo *pm)
172 {
173 Object *piix = piix4_pm_find();
174 Object *lpc = ich9_lpc_find();
175 Object *obj = NULL;
176 QObject *o;
177
178 pm->cpu_hp_io_base = 0;
179 pm->pcihp_io_base = 0;
180 pm->pcihp_io_len = 0;
181 if (piix) {
182 obj = piix;
183 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
184 pm->pcihp_io_base =
185 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
186 pm->pcihp_io_len =
187 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
188 }
189 if (lpc) {
190 obj = lpc;
191 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
192 }
193 assert(obj);
194
195 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
196 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
197 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
198
199 /* Fill in optional s3/s4 related properties */
200 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
201 if (o) {
202 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
203 } else {
204 pm->s3_disabled = false;
205 }
206 qobject_decref(o);
207 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
208 if (o) {
209 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
210 } else {
211 pm->s4_disabled = false;
212 }
213 qobject_decref(o);
214 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
215 if (o) {
216 pm->s4_val = qint_get_int(qobject_to_qint(o));
217 } else {
218 pm->s4_val = false;
219 }
220 qobject_decref(o);
221
222 /* Fill in mandatory properties */
223 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
224
225 pm->acpi_enable_cmd = object_property_get_int(obj,
226 ACPI_PM_PROP_ACPI_ENABLE_CMD,
227 NULL);
228 pm->acpi_disable_cmd = object_property_get_int(obj,
229 ACPI_PM_PROP_ACPI_DISABLE_CMD,
230 NULL);
231 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
232 NULL);
233 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
234 NULL);
235 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
236 NULL);
237 pm->pcihp_bridge_en =
238 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
239 NULL);
240 }
241
242 static void acpi_get_misc_info(AcpiMiscInfo *info)
243 {
244 info->has_hpet = hpet_find();
245 info->tpm_version = tpm_get_version();
246 info->pvpanic_port = pvpanic_port();
247 info->applesmc_io_base = applesmc_port();
248 }
249
250 /*
251 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
252 * On i386 arch we only have two pci hosts, so we can look only for them.
253 */
254 static Object *acpi_get_i386_pci_host(void)
255 {
256 PCIHostState *host;
257
258 host = OBJECT_CHECK(PCIHostState,
259 object_resolve_path("/machine/i440fx", NULL),
260 TYPE_PCI_HOST_BRIDGE);
261 if (!host) {
262 host = OBJECT_CHECK(PCIHostState,
263 object_resolve_path("/machine/q35", NULL),
264 TYPE_PCI_HOST_BRIDGE);
265 }
266
267 return OBJECT(host);
268 }
269
270 static void acpi_get_pci_info(PcPciInfo *info)
271 {
272 Object *pci_host;
273
274
275 pci_host = acpi_get_i386_pci_host();
276 g_assert(pci_host);
277
278 info->w32.begin = object_property_get_int(pci_host,
279 PCI_HOST_PROP_PCI_HOLE_START,
280 NULL);
281 info->w32.end = object_property_get_int(pci_host,
282 PCI_HOST_PROP_PCI_HOLE_END,
283 NULL);
284 info->w64.begin = object_property_get_int(pci_host,
285 PCI_HOST_PROP_PCI_HOLE64_START,
286 NULL);
287 info->w64.end = object_property_get_int(pci_host,
288 PCI_HOST_PROP_PCI_HOLE64_END,
289 NULL);
290 }
291
292 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
293
294 static void acpi_align_size(GArray *blob, unsigned align)
295 {
296 /* Align size to multiple of given size. This reduces the chance
297 * we need to change size in the future (breaking cross version migration).
298 */
299 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
300 }
301
302 /* FACS */
303 static void
304 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
305 {
306 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
307 memcpy(&facs->signature, "FACS", 4);
308 facs->length = cpu_to_le32(sizeof(*facs));
309 }
310
311 /* Load chipset information in FADT */
312 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
313 {
314 fadt->model = 1;
315 fadt->reserved1 = 0;
316 fadt->sci_int = cpu_to_le16(pm->sci_int);
317 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
318 fadt->acpi_enable = pm->acpi_enable_cmd;
319 fadt->acpi_disable = pm->acpi_disable_cmd;
320 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
321 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
322 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
323 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
324 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
325 /* EVT, CNT, TMR length matches hw/acpi/core.c */
326 fadt->pm1_evt_len = 4;
327 fadt->pm1_cnt_len = 2;
328 fadt->pm_tmr_len = 4;
329 fadt->gpe0_blk_len = pm->gpe0_blk_len;
330 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
331 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
332 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
333 (1 << ACPI_FADT_F_PROC_C1) |
334 (1 << ACPI_FADT_F_SLP_BUTTON) |
335 (1 << ACPI_FADT_F_RTC_S4));
336 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
337 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
338 * For more than 8 CPUs, "Clustered Logical" mode has to be used
339 */
340 if (max_cpus > 8) {
341 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
342 }
343 fadt->century = RTC_CENTURY;
344 }
345
346
347 /* FADT */
348 static void
349 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
350 unsigned facs, unsigned dsdt)
351 {
352 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
353
354 fadt->firmware_ctrl = cpu_to_le32(facs);
355 /* FACS address to be filled by Guest linker */
356 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
357 ACPI_BUILD_TABLE_FILE,
358 table_data, &fadt->firmware_ctrl,
359 sizeof fadt->firmware_ctrl);
360
361 fadt->dsdt = cpu_to_le32(dsdt);
362 /* DSDT address to be filled by Guest linker */
363 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
364 ACPI_BUILD_TABLE_FILE,
365 table_data, &fadt->dsdt,
366 sizeof fadt->dsdt);
367
368 fadt_setup(fadt, pm);
369
370 build_header(linker, table_data,
371 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
372 }
373
374 static void
375 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
376 PcGuestInfo *guest_info)
377 {
378 int madt_start = table_data->len;
379
380 AcpiMultipleApicTable *madt;
381 AcpiMadtIoApic *io_apic;
382 AcpiMadtIntsrcovr *intsrcovr;
383 AcpiMadtLocalNmi *local_nmi;
384 int i;
385
386 madt = acpi_data_push(table_data, sizeof *madt);
387 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
388 madt->flags = cpu_to_le32(1);
389
390 for (i = 0; i < guest_info->apic_id_limit; i++) {
391 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
392 apic->type = ACPI_APIC_PROCESSOR;
393 apic->length = sizeof(*apic);
394 apic->processor_id = i;
395 apic->local_apic_id = i;
396 if (test_bit(i, cpu->found_cpus)) {
397 apic->flags = cpu_to_le32(1);
398 } else {
399 apic->flags = cpu_to_le32(0);
400 }
401 }
402 io_apic = acpi_data_push(table_data, sizeof *io_apic);
403 io_apic->type = ACPI_APIC_IO;
404 io_apic->length = sizeof(*io_apic);
405 #define ACPI_BUILD_IOAPIC_ID 0x0
406 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
407 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
408 io_apic->interrupt = cpu_to_le32(0);
409
410 if (guest_info->apic_xrupt_override) {
411 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
412 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
413 intsrcovr->length = sizeof(*intsrcovr);
414 intsrcovr->source = 0;
415 intsrcovr->gsi = cpu_to_le32(2);
416 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
417 }
418 for (i = 1; i < 16; i++) {
419 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
420 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
421 /* No need for a INT source override structure. */
422 continue;
423 }
424 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
425 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
426 intsrcovr->length = sizeof(*intsrcovr);
427 intsrcovr->source = i;
428 intsrcovr->gsi = cpu_to_le32(i);
429 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
430 }
431
432 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
433 local_nmi->type = ACPI_APIC_LOCAL_NMI;
434 local_nmi->length = sizeof(*local_nmi);
435 local_nmi->processor_id = 0xff; /* all processors */
436 local_nmi->flags = cpu_to_le16(0);
437 local_nmi->lint = 1; /* ACPI_LINT1 */
438
439 build_header(linker, table_data,
440 (void *)(table_data->data + madt_start), "APIC",
441 table_data->len - madt_start, 1, NULL);
442 }
443
444 /* Assign BSEL property to all buses. In the future, this can be changed
445 * to only assign to buses that support hotplug.
446 */
447 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
448 {
449 unsigned *bsel_alloc = opaque;
450 unsigned *bus_bsel;
451
452 if (qbus_is_hotpluggable(BUS(bus))) {
453 bus_bsel = g_malloc(sizeof *bus_bsel);
454
455 *bus_bsel = (*bsel_alloc)++;
456 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
457 bus_bsel, NULL);
458 }
459
460 return bsel_alloc;
461 }
462
463 static void acpi_set_pci_info(void)
464 {
465 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
466 unsigned bsel_alloc = 0;
467
468 if (bus) {
469 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
470 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
471 }
472 }
473
474 static void build_append_pcihp_notify_entry(Aml *method, int slot)
475 {
476 Aml *if_ctx;
477 int32_t devfn = PCI_DEVFN(slot, 0);
478
479 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
480 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
481 aml_append(method, if_ctx);
482 }
483
484 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
485 bool pcihp_bridge_en)
486 {
487 Aml *dev, *notify_method, *method;
488 QObject *bsel;
489 PCIBus *sec;
490 int i;
491
492 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
493 if (bsel) {
494 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
495
496 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
497 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
498 }
499
500 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
501 DeviceClass *dc;
502 PCIDeviceClass *pc;
503 PCIDevice *pdev = bus->devices[i];
504 int slot = PCI_SLOT(i);
505 bool hotplug_enabled_dev;
506 bool bridge_in_acpi;
507
508 if (!pdev) {
509 if (bsel) { /* add hotplug slots for non present devices */
510 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
511 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
512 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
513 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
514 aml_append(method,
515 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
516 );
517 aml_append(dev, method);
518 aml_append(parent_scope, dev);
519
520 build_append_pcihp_notify_entry(notify_method, slot);
521 }
522 continue;
523 }
524
525 pc = PCI_DEVICE_GET_CLASS(pdev);
526 dc = DEVICE_GET_CLASS(pdev);
527
528 /* When hotplug for bridges is enabled, bridges are
529 * described in ACPI separately (see build_pci_bus_end).
530 * In this case they aren't themselves hot-pluggable.
531 * Hotplugged bridges *are* hot-pluggable.
532 */
533 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
534 !DEVICE(pdev)->hotplugged;
535
536 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
537
538 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
539 continue;
540 }
541
542 /* start to compose PCI slot descriptor */
543 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
544 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
545
546 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
547 /* add VGA specific AML methods */
548 int s3d;
549
550 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
551 s3d = 3;
552 } else {
553 s3d = 0;
554 }
555
556 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
557 aml_append(method, aml_return(aml_int(0)));
558 aml_append(dev, method);
559
560 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
561 aml_append(method, aml_return(aml_int(0)));
562 aml_append(dev, method);
563
564 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
565 aml_append(method, aml_return(aml_int(s3d)));
566 aml_append(dev, method);
567 } else if (hotplug_enabled_dev) {
568 /* add _SUN/_EJ0 to make slot hotpluggable */
569 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
570
571 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
572 aml_append(method,
573 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
574 );
575 aml_append(dev, method);
576
577 if (bsel) {
578 build_append_pcihp_notify_entry(notify_method, slot);
579 }
580 } else if (bridge_in_acpi) {
581 /*
582 * device is coldplugged bridge,
583 * add child device descriptions into its scope
584 */
585 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
586
587 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
588 }
589 /* slot descriptor has been composed, add it into parent context */
590 aml_append(parent_scope, dev);
591 }
592
593 if (bsel) {
594 aml_append(parent_scope, notify_method);
595 }
596
597 /* Append PCNT method to notify about events on local and child buses.
598 * Add unconditionally for root since DSDT expects it.
599 */
600 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
601
602 /* If bus supports hotplug select it and notify about local events */
603 if (bsel) {
604 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
605 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
606 aml_append(method,
607 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
608 );
609 aml_append(method,
610 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
611 );
612 }
613
614 /* Notify about child bus events in any case */
615 if (pcihp_bridge_en) {
616 QLIST_FOREACH(sec, &bus->child, sibling) {
617 int32_t devfn = sec->parent_dev->devfn;
618
619 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
620 }
621 }
622 aml_append(parent_scope, method);
623 qobject_decref(bsel);
624 }
625
626 /*
627 * initialize_route - Initialize the interrupt routing rule
628 * through a specific LINK:
629 * if (lnk_idx == idx)
630 * route using link 'link_name'
631 */
632 static Aml *initialize_route(Aml *route, const char *link_name,
633 Aml *lnk_idx, int idx)
634 {
635 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
636 Aml *pkg = aml_package(4);
637
638 aml_append(pkg, aml_int(0));
639 aml_append(pkg, aml_int(0));
640 aml_append(pkg, aml_name("%s", link_name));
641 aml_append(pkg, aml_int(0));
642 aml_append(if_ctx, aml_store(pkg, route));
643
644 return if_ctx;
645 }
646
647 /*
648 * build_prt - Define interrupt rounting rules
649 *
650 * Returns an array of 128 routes, one for each device,
651 * based on device location.
652 * The main goal is to equaly distribute the interrupts
653 * over the 4 existing ACPI links (works only for i440fx).
654 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
655 *
656 */
657 static Aml *build_prt(void)
658 {
659 Aml *method, *while_ctx, *pin, *res;
660
661 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
662 res = aml_local(0);
663 pin = aml_local(1);
664 aml_append(method, aml_store(aml_package(128), res));
665 aml_append(method, aml_store(aml_int(0), pin));
666
667 /* while (pin < 128) */
668 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
669 {
670 Aml *slot = aml_local(2);
671 Aml *lnk_idx = aml_local(3);
672 Aml *route = aml_local(4);
673
674 /* slot = pin >> 2 */
675 aml_append(while_ctx,
676 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
677 /* lnk_idx = (slot + pin) & 3 */
678 aml_append(while_ctx,
679 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
680 lnk_idx));
681
682 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
683 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
684 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
685 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
686 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
687
688 /* route[0] = 0x[slot]FFFF */
689 aml_append(while_ctx,
690 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
691 NULL),
692 aml_index(route, aml_int(0))));
693 /* route[1] = pin & 3 */
694 aml_append(while_ctx,
695 aml_store(aml_and(pin, aml_int(3), NULL),
696 aml_index(route, aml_int(1))));
697 /* res[pin] = route */
698 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
699 /* pin++ */
700 aml_append(while_ctx, aml_increment(pin));
701 }
702 aml_append(method, while_ctx);
703 /* return res*/
704 aml_append(method, aml_return(res));
705
706 return method;
707 }
708
709 typedef struct CrsRangeEntry {
710 uint64_t base;
711 uint64_t limit;
712 } CrsRangeEntry;
713
714 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
715 {
716 CrsRangeEntry *entry;
717
718 entry = g_malloc(sizeof(*entry));
719 entry->base = base;
720 entry->limit = limit;
721
722 g_ptr_array_add(ranges, entry);
723 }
724
725 static void crs_range_free(gpointer data)
726 {
727 CrsRangeEntry *entry = (CrsRangeEntry *)data;
728 g_free(entry);
729 }
730
731 static gint crs_range_compare(gconstpointer a, gconstpointer b)
732 {
733 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
734 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
735
736 return (int64_t)entry_a->base - (int64_t)entry_b->base;
737 }
738
739 /*
740 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
741 * interval, computes the 'free' ranges from the same interval.
742 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
743 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
744 */
745 static void crs_replace_with_free_ranges(GPtrArray *ranges,
746 uint64_t start, uint64_t end)
747 {
748 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
749 uint64_t free_base = start;
750 int i;
751
752 g_ptr_array_sort(ranges, crs_range_compare);
753 for (i = 0; i < ranges->len; i++) {
754 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
755
756 if (free_base < used->base) {
757 crs_range_insert(free_ranges, free_base, used->base - 1);
758 }
759
760 free_base = used->limit + 1;
761 }
762
763 if (free_base < end) {
764 crs_range_insert(free_ranges, free_base, end);
765 }
766
767 g_ptr_array_set_size(ranges, 0);
768 for (i = 0; i < free_ranges->len; i++) {
769 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
770 }
771
772 g_ptr_array_free(free_ranges, false);
773 }
774
775 /*
776 * crs_range_merge - merges adjacent ranges in the given array.
777 * Array elements are deleted and replaced with the merged ranges.
778 */
779 static void crs_range_merge(GPtrArray *range)
780 {
781 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
782 CrsRangeEntry *entry;
783 uint64_t range_base, range_limit;
784 int i;
785
786 if (!range->len) {
787 return;
788 }
789
790 g_ptr_array_sort(range, crs_range_compare);
791
792 entry = g_ptr_array_index(range, 0);
793 range_base = entry->base;
794 range_limit = entry->limit;
795 for (i = 1; i < range->len; i++) {
796 entry = g_ptr_array_index(range, i);
797 if (entry->base - 1 == range_limit) {
798 range_limit = entry->limit;
799 } else {
800 crs_range_insert(tmp, range_base, range_limit);
801 range_base = entry->base;
802 range_limit = entry->limit;
803 }
804 }
805 crs_range_insert(tmp, range_base, range_limit);
806
807 g_ptr_array_set_size(range, 0);
808 for (i = 0; i < tmp->len; i++) {
809 entry = g_ptr_array_index(tmp, i);
810 crs_range_insert(range, entry->base, entry->limit);
811 }
812 g_ptr_array_free(tmp, true);
813 }
814
815 static Aml *build_crs(PCIHostState *host,
816 GPtrArray *io_ranges, GPtrArray *mem_ranges)
817 {
818 Aml *crs = aml_resource_template();
819 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
820 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
821 CrsRangeEntry *entry;
822 uint8_t max_bus = pci_bus_num(host->bus);
823 uint8_t type;
824 int devfn;
825 int i;
826
827 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
828 uint64_t range_base, range_limit;
829 PCIDevice *dev = host->bus->devices[devfn];
830
831 if (!dev) {
832 continue;
833 }
834
835 for (i = 0; i < PCI_NUM_REGIONS; i++) {
836 PCIIORegion *r = &dev->io_regions[i];
837
838 range_base = r->addr;
839 range_limit = r->addr + r->size - 1;
840
841 /*
842 * Work-around for old bioses
843 * that do not support multiple root buses
844 */
845 if (!range_base || range_base > range_limit) {
846 continue;
847 }
848
849 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
850 crs_range_insert(host_io_ranges, range_base, range_limit);
851 } else { /* "memory" */
852 crs_range_insert(host_mem_ranges, range_base, range_limit);
853 }
854 }
855
856 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
857 if (type == PCI_HEADER_TYPE_BRIDGE) {
858 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
859 if (subordinate > max_bus) {
860 max_bus = subordinate;
861 }
862
863 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
864 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
865
866 /*
867 * Work-around for old bioses
868 * that do not support multiple root buses
869 */
870 if (range_base && range_base <= range_limit) {
871 crs_range_insert(host_io_ranges, range_base, range_limit);
872 }
873
874 range_base =
875 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
876 range_limit =
877 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
878
879 /*
880 * Work-around for old bioses
881 * that do not support multiple root buses
882 */
883 if (range_base && range_base <= range_limit) {
884 crs_range_insert(host_mem_ranges, range_base, range_limit);
885 }
886
887 range_base =
888 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
889 range_limit =
890 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
891
892 /*
893 * Work-around for old bioses
894 * that do not support multiple root buses
895 */
896 if (range_base && range_base <= range_limit) {
897 crs_range_insert(host_mem_ranges, range_base, range_limit);
898 }
899 }
900 }
901
902 crs_range_merge(host_io_ranges);
903 for (i = 0; i < host_io_ranges->len; i++) {
904 entry = g_ptr_array_index(host_io_ranges, i);
905 aml_append(crs,
906 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
907 AML_POS_DECODE, AML_ENTIRE_RANGE,
908 0, entry->base, entry->limit, 0,
909 entry->limit - entry->base + 1));
910 crs_range_insert(io_ranges, entry->base, entry->limit);
911 }
912 g_ptr_array_free(host_io_ranges, true);
913
914 crs_range_merge(host_mem_ranges);
915 for (i = 0; i < host_mem_ranges->len; i++) {
916 entry = g_ptr_array_index(host_mem_ranges, i);
917 aml_append(crs,
918 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
919 AML_MAX_FIXED, AML_NON_CACHEABLE,
920 AML_READ_WRITE,
921 0, entry->base, entry->limit, 0,
922 entry->limit - entry->base + 1));
923 crs_range_insert(mem_ranges, entry->base, entry->limit);
924 }
925 g_ptr_array_free(host_mem_ranges, true);
926
927 aml_append(crs,
928 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
929 0,
930 pci_bus_num(host->bus),
931 max_bus,
932 0,
933 max_bus - pci_bus_num(host->bus) + 1));
934
935 return crs;
936 }
937
938 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
939 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
940 {
941 int i;
942 Aml *dev;
943 Aml *crs;
944 Aml *pkg;
945 Aml *field;
946 Aml *ifctx;
947 Aml *method;
948
949 /* The current AML generator can cover the APIC ID range [0..255],
950 * inclusive, for VCPU hotplug. */
951 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
952 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
953
954 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
955 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
956 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
957 aml_append(dev,
958 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
959 );
960 /* device present, functioning, decoding, not shown in UI */
961 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
962 crs = aml_resource_template();
963 aml_append(crs,
964 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
965 pm->cpu_hp_io_len)
966 );
967 aml_append(dev, aml_name_decl("_CRS", crs));
968 aml_append(sb_scope, dev);
969 /* declare CPU hotplug MMIO region and PRS field to access it */
970 aml_append(sb_scope, aml_operation_region(
971 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
972 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
973 aml_append(field, aml_named_field("PRS", 256));
974 aml_append(sb_scope, field);
975
976 /* build Processor object for each processor */
977 for (i = 0; i < acpi_cpus; i++) {
978 dev = aml_processor(i, 0, 0, "CP%.02X", i);
979
980 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
981 aml_append(method,
982 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
983 aml_append(dev, method);
984
985 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
986 aml_append(method,
987 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
988 aml_append(dev, method);
989
990 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
991 aml_append(method,
992 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
993 );
994 aml_append(dev, method);
995
996 aml_append(sb_scope, dev);
997 }
998
999 /* build this code:
1000 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1001 */
1002 /* Arg0 = Processor ID = APIC ID */
1003 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1004 for (i = 0; i < acpi_cpus; i++) {
1005 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1006 aml_append(ifctx,
1007 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1008 );
1009 aml_append(method, ifctx);
1010 }
1011 aml_append(sb_scope, method);
1012
1013 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1014 *
1015 * Note: The ability to create variable-sized packages was first
1016 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1017 * ith up to 255 elements. Windows guests up to win2k8 fail when
1018 * VarPackageOp is used.
1019 */
1020 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1021 aml_varpackage(acpi_cpus);
1022
1023 for (i = 0; i < acpi_cpus; i++) {
1024 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1025 aml_append(pkg, aml_int(b));
1026 }
1027 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1028 }
1029
1030 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1031 uint16_t io_base, uint16_t io_len)
1032 {
1033 int i;
1034 Aml *scope;
1035 Aml *crs;
1036 Aml *field;
1037 Aml *dev;
1038 Aml *method;
1039 Aml *ifctx;
1040
1041 /* build memory devices */
1042 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1043 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1044 aml_append(scope,
1045 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1046 );
1047
1048 crs = aml_resource_template();
1049 aml_append(crs,
1050 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1051 );
1052 aml_append(scope, aml_name_decl("_CRS", crs));
1053
1054 aml_append(scope, aml_operation_region(
1055 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1056 io_base, io_len)
1057 );
1058
1059 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1060 AML_NOLOCK, AML_PRESERVE);
1061 aml_append(field, /* read only */
1062 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1063 aml_append(field, /* read only */
1064 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1065 aml_append(field, /* read only */
1066 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1067 aml_append(field, /* read only */
1068 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1069 aml_append(field, /* read only */
1070 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1071 aml_append(scope, field);
1072
1073 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1074 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1075 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1076 aml_append(field, /* 1 if enabled, read only */
1077 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1078 aml_append(field,
1079 /*(read) 1 if has a insert event. (write) 1 to clear event */
1080 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1081 aml_append(field,
1082 /* (read) 1 if has a remove event. (write) 1 to clear event */
1083 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1084 aml_append(field,
1085 /* initiates device eject, write only */
1086 aml_named_field(MEMORY_SLOT_EJECT, 1));
1087 aml_append(scope, field);
1088
1089 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1090 AML_NOLOCK, AML_PRESERVE);
1091 aml_append(field, /* DIMM selector, write only */
1092 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1093 aml_append(field, /* _OST event code, write only */
1094 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1095 aml_append(field, /* _OST status code, write only */
1096 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1097 aml_append(scope, field);
1098 aml_append(sb_scope, scope);
1099
1100 for (i = 0; i < nr_mem; i++) {
1101 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1102 const char *s;
1103
1104 dev = aml_device("MP%02X", i);
1105 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1106 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1107
1108 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1109 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1110 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1111 aml_append(dev, method);
1112
1113 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1114 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1115 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1116 aml_append(dev, method);
1117
1118 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1119 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1120 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1121 aml_append(dev, method);
1122
1123 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1124 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1125
1126 aml_append(method, aml_return(aml_call4(
1127 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1128 )));
1129 aml_append(dev, method);
1130
1131 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1132 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1133 aml_append(method, aml_return(aml_call2(
1134 s, aml_name("_UID"), aml_arg(0))));
1135 aml_append(dev, method);
1136
1137 aml_append(sb_scope, dev);
1138 }
1139
1140 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1141 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1142 */
1143 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1144 for (i = 0; i < nr_mem; i++) {
1145 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1146 aml_append(ifctx,
1147 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1148 );
1149 aml_append(method, ifctx);
1150 }
1151 aml_append(sb_scope, method);
1152 }
1153
1154 static void build_hpet_aml(Aml *table)
1155 {
1156 Aml *crs;
1157 Aml *field;
1158 Aml *method;
1159 Aml *if_ctx;
1160 Aml *scope = aml_scope("_SB");
1161 Aml *dev = aml_device("HPET");
1162 Aml *zero = aml_int(0);
1163 Aml *id = aml_local(0);
1164 Aml *period = aml_local(1);
1165
1166 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1167 aml_append(dev, aml_name_decl("_UID", zero));
1168
1169 aml_append(dev,
1170 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN));
1171 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1172 aml_append(field, aml_named_field("VEND", 32));
1173 aml_append(field, aml_named_field("PRD", 32));
1174 aml_append(dev, field);
1175
1176 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1177 aml_append(method, aml_store(aml_name("VEND"), id));
1178 aml_append(method, aml_store(aml_name("PRD"), period));
1179 aml_append(method, aml_shiftright(id, aml_int(16), id));
1180 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1181 aml_equal(id, aml_int(0xffff))));
1182 {
1183 aml_append(if_ctx, aml_return(zero));
1184 }
1185 aml_append(method, if_ctx);
1186
1187 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1188 aml_lgreater(period, aml_int(100000000))));
1189 {
1190 aml_append(if_ctx, aml_return(zero));
1191 }
1192 aml_append(method, if_ctx);
1193
1194 aml_append(method, aml_return(aml_int(0x0F)));
1195 aml_append(dev, method);
1196
1197 crs = aml_resource_template();
1198 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1199 aml_append(dev, aml_name_decl("_CRS", crs));
1200
1201 aml_append(scope, dev);
1202 aml_append(table, scope);
1203 }
1204
1205 static Aml *build_fdc_device_aml(void)
1206 {
1207 Aml *dev;
1208 Aml *crs;
1209 Aml *method;
1210 Aml *if_ctx;
1211 Aml *else_ctx;
1212 Aml *zero = aml_int(0);
1213 Aml *is_present = aml_local(0);
1214
1215 dev = aml_device("FDC0");
1216 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1217
1218 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1219 aml_append(method, aml_store(aml_name("FDEN"), is_present));
1220 if_ctx = aml_if(aml_equal(is_present, zero));
1221 {
1222 aml_append(if_ctx, aml_return(aml_int(0x00)));
1223 }
1224 aml_append(method, if_ctx);
1225 else_ctx = aml_else();
1226 {
1227 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1228 }
1229 aml_append(method, else_ctx);
1230 aml_append(dev, method);
1231
1232 crs = aml_resource_template();
1233 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1234 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1235 aml_append(crs, aml_irq_no_flags(6));
1236 aml_append(crs,
1237 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1238 aml_append(dev, aml_name_decl("_CRS", crs));
1239
1240 return dev;
1241 }
1242
1243 static Aml *build_rtc_device_aml(void)
1244 {
1245 Aml *dev;
1246 Aml *crs;
1247
1248 dev = aml_device("RTC");
1249 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1250 crs = aml_resource_template();
1251 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1252 aml_append(crs, aml_irq_no_flags(8));
1253 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1254 aml_append(dev, aml_name_decl("_CRS", crs));
1255
1256 return dev;
1257 }
1258
1259 static Aml *build_kbd_device_aml(void)
1260 {
1261 Aml *dev;
1262 Aml *crs;
1263 Aml *method;
1264
1265 dev = aml_device("KBD");
1266 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1267
1268 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1269 aml_append(method, aml_return(aml_int(0x0f)));
1270 aml_append(dev, method);
1271
1272 crs = aml_resource_template();
1273 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1274 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1275 aml_append(crs, aml_irq_no_flags(1));
1276 aml_append(dev, aml_name_decl("_CRS", crs));
1277
1278 return dev;
1279 }
1280
1281 static Aml *build_mouse_device_aml(void)
1282 {
1283 Aml *dev;
1284 Aml *crs;
1285 Aml *method;
1286
1287 dev = aml_device("MOU");
1288 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1289
1290 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1291 aml_append(method, aml_return(aml_int(0x0f)));
1292 aml_append(dev, method);
1293
1294 crs = aml_resource_template();
1295 aml_append(crs, aml_irq_no_flags(12));
1296 aml_append(dev, aml_name_decl("_CRS", crs));
1297
1298 return dev;
1299 }
1300
1301 static Aml *build_lpt_device_aml(void)
1302 {
1303 Aml *dev;
1304 Aml *crs;
1305 Aml *method;
1306 Aml *if_ctx;
1307 Aml *else_ctx;
1308 Aml *zero = aml_int(0);
1309 Aml *is_present = aml_local(0);
1310
1311 dev = aml_device("LPT");
1312 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1313
1314 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1315 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1316 if_ctx = aml_if(aml_equal(is_present, zero));
1317 {
1318 aml_append(if_ctx, aml_return(aml_int(0x00)));
1319 }
1320 aml_append(method, if_ctx);
1321 else_ctx = aml_else();
1322 {
1323 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1324 }
1325 aml_append(method, else_ctx);
1326 aml_append(dev, method);
1327
1328 crs = aml_resource_template();
1329 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1330 aml_append(crs, aml_irq_no_flags(7));
1331 aml_append(dev, aml_name_decl("_CRS", crs));
1332
1333 return dev;
1334 }
1335
1336 static Aml *build_com_device_aml(uint8_t uid)
1337 {
1338 Aml *dev;
1339 Aml *crs;
1340 Aml *method;
1341 Aml *if_ctx;
1342 Aml *else_ctx;
1343 Aml *zero = aml_int(0);
1344 Aml *is_present = aml_local(0);
1345 const char *enabled_field = "CAEN";
1346 uint8_t irq = 4;
1347 uint16_t io_port = 0x03F8;
1348
1349 assert(uid == 1 || uid == 2);
1350 if (uid == 2) {
1351 enabled_field = "CBEN";
1352 irq = 3;
1353 io_port = 0x02F8;
1354 }
1355
1356 dev = aml_device("COM%d", uid);
1357 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1358 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1359
1360 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1361 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1362 if_ctx = aml_if(aml_equal(is_present, zero));
1363 {
1364 aml_append(if_ctx, aml_return(aml_int(0x00)));
1365 }
1366 aml_append(method, if_ctx);
1367 else_ctx = aml_else();
1368 {
1369 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1370 }
1371 aml_append(method, else_ctx);
1372 aml_append(dev, method);
1373
1374 crs = aml_resource_template();
1375 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1376 aml_append(crs, aml_irq_no_flags(irq));
1377 aml_append(dev, aml_name_decl("_CRS", crs));
1378
1379 return dev;
1380 }
1381
1382 static void build_isa_devices_aml(Aml *table)
1383 {
1384 Aml *scope = aml_scope("_SB.PCI0.ISA");
1385
1386 aml_append(scope, build_rtc_device_aml());
1387 aml_append(scope, build_kbd_device_aml());
1388 aml_append(scope, build_mouse_device_aml());
1389 aml_append(scope, build_fdc_device_aml());
1390 aml_append(scope, build_lpt_device_aml());
1391 aml_append(scope, build_com_device_aml(1));
1392 aml_append(scope, build_com_device_aml(2));
1393
1394 aml_append(table, scope);
1395 }
1396
1397 static void build_dbg_aml(Aml *table)
1398 {
1399 Aml *field;
1400 Aml *method;
1401 Aml *while_ctx;
1402 Aml *scope = aml_scope("\\");
1403 Aml *buf = aml_local(0);
1404 Aml *len = aml_local(1);
1405 Aml *idx = aml_local(2);
1406
1407 aml_append(scope,
1408 aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01));
1409 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1410 aml_append(field, aml_named_field("DBGB", 8));
1411 aml_append(scope, field);
1412
1413 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1414
1415 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1416 aml_append(method, aml_to_buffer(buf, buf));
1417 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1418 aml_append(method, aml_store(aml_int(0), idx));
1419
1420 while_ctx = aml_while(aml_lless(idx, len));
1421 aml_append(while_ctx,
1422 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1423 aml_append(while_ctx, aml_increment(idx));
1424 aml_append(method, while_ctx);
1425
1426 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1427 aml_append(scope, method);
1428
1429 aml_append(table, scope);
1430 }
1431
1432 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1433 {
1434 Aml *dev;
1435 Aml *crs;
1436 Aml *method;
1437 uint32_t irqs[] = {5, 10, 11};
1438
1439 dev = aml_device("%s", name);
1440 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1441 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1442
1443 crs = aml_resource_template();
1444 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1445 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1446 aml_append(dev, aml_name_decl("_PRS", crs));
1447
1448 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1449 aml_append(method, aml_return(aml_call1("IQST", reg)));
1450 aml_append(dev, method);
1451
1452 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1453 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1454 aml_append(dev, method);
1455
1456 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1457 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1458 aml_append(dev, method);
1459
1460 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1461 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1462 aml_append(method, aml_store(aml_name("PRRI"), reg));
1463 aml_append(dev, method);
1464
1465 return dev;
1466 }
1467
1468 static void build_piix4_pci0_int(Aml *table)
1469 {
1470 Aml *dev;
1471 Aml *crs;
1472 Aml *field;
1473 Aml *method;
1474 uint32_t irqs;
1475 Aml *sb_scope = aml_scope("_SB");
1476
1477 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1478 aml_append(field, aml_named_field("PRQ0", 8));
1479 aml_append(field, aml_named_field("PRQ1", 8));
1480 aml_append(field, aml_named_field("PRQ2", 8));
1481 aml_append(field, aml_named_field("PRQ3", 8));
1482 aml_append(sb_scope, field);
1483
1484 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1485 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1486 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1487 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1488
1489 dev = aml_device("LNKS");
1490 {
1491 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1492 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1493
1494 crs = aml_resource_template();
1495 irqs = 9;
1496 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1497 AML_ACTIVE_HIGH, AML_SHARED,
1498 &irqs, 1));
1499 aml_append(dev, aml_name_decl("_PRS", crs));
1500
1501 /* The SCI cannot be disabled and is always attached to GSI 9,
1502 * so these are no-ops. We only need this link to override the
1503 * polarity to active high and match the content of the MADT.
1504 */
1505 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1506 aml_append(method, aml_return(aml_int(0x0b)));
1507 aml_append(dev, method);
1508
1509 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1510 aml_append(dev, method);
1511
1512 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1513 aml_append(method, aml_return(aml_name("_PRS")));
1514 aml_append(dev, method);
1515
1516 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1517 aml_append(dev, method);
1518 }
1519 aml_append(sb_scope, dev);
1520
1521 aml_append(table, sb_scope);
1522 }
1523
1524 static void build_piix4_pm(Aml *table)
1525 {
1526 Aml *dev;
1527 Aml *scope;
1528
1529 scope = aml_scope("_SB.PCI0");
1530 dev = aml_device("PX13");
1531 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1532
1533 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1534 0x00, 0xff));
1535 aml_append(scope, dev);
1536 aml_append(table, scope);
1537 }
1538
1539 static void build_piix4_isa_bridge(Aml *table)
1540 {
1541 Aml *dev;
1542 Aml *scope;
1543 Aml *field;
1544
1545 scope = aml_scope("_SB.PCI0");
1546 dev = aml_device("ISA");
1547 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1548
1549 /* PIIX PCI to ISA irq remapping */
1550 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1551 0x60, 0x04));
1552 /* enable bits */
1553 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1554 /* Offset(0x5f),, 7, */
1555 aml_append(field, aml_reserved_field(0x2f8));
1556 aml_append(field, aml_reserved_field(7));
1557 aml_append(field, aml_named_field("LPEN", 1));
1558 /* Offset(0x67),, 3, */
1559 aml_append(field, aml_reserved_field(0x38));
1560 aml_append(field, aml_reserved_field(3));
1561 aml_append(field, aml_named_field("CAEN", 1));
1562 aml_append(field, aml_reserved_field(3));
1563 aml_append(field, aml_named_field("CBEN", 1));
1564 aml_append(dev, field);
1565 aml_append(dev, aml_name_decl("FDEN", aml_int(1)));
1566
1567 aml_append(scope, dev);
1568 aml_append(table, scope);
1569 }
1570
1571 static void
1572 build_ssdt(GArray *table_data, GArray *linker,
1573 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1574 PcPciInfo *pci, PcGuestInfo *guest_info)
1575 {
1576 MachineState *machine = MACHINE(qdev_get_machine());
1577 uint32_t nr_mem = machine->ram_slots;
1578 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field;
1579 PCIBus *bus = NULL;
1580 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1581 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1582 CrsRangeEntry *entry;
1583 int root_bus_limit = 0xFF;
1584 int i;
1585
1586 ssdt = init_aml_allocator();
1587
1588 /* Reserve space for header */
1589 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
1590
1591 build_dbg_aml(ssdt);
1592 if (misc->is_piix4) {
1593 build_hpet_aml(ssdt);
1594 build_piix4_pm(ssdt);
1595 build_piix4_isa_bridge(ssdt);
1596 build_isa_devices_aml(ssdt);
1597 build_piix4_pci0_int(ssdt);
1598 } else {
1599 build_hpet_aml(ssdt);
1600 build_isa_devices_aml(ssdt);
1601 }
1602 build_cpu_hotplug_aml(ssdt);
1603 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
1604 pm->mem_hp_io_len);
1605
1606 scope = aml_scope("_GPE");
1607 {
1608 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1609
1610 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
1611
1612 if (misc->is_piix4) {
1613 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1614 aml_append(method,
1615 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1616 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1617 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1618 aml_append(scope, method);
1619 } else {
1620 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
1621 }
1622
1623 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
1624 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
1625 aml_append(scope, method);
1626
1627 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1628 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1629 aml_append(scope, method);
1630
1631 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
1632 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
1633 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
1634 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
1635 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
1636 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
1637 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
1638 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
1639 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
1640 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
1641 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
1642 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
1643 }
1644 aml_append(ssdt, scope);
1645
1646 bus = PC_MACHINE(machine)->bus;
1647 if (bus) {
1648 QLIST_FOREACH(bus, &bus->child, sibling) {
1649 uint8_t bus_num = pci_bus_num(bus);
1650 uint8_t numa_node = pci_bus_numa_node(bus);
1651
1652 /* look only for expander root buses */
1653 if (!pci_bus_is_root(bus)) {
1654 continue;
1655 }
1656
1657 if (bus_num < root_bus_limit) {
1658 root_bus_limit = bus_num - 1;
1659 }
1660
1661 scope = aml_scope("\\_SB");
1662 dev = aml_device("PC%.02X", bus_num);
1663 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1664 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1665 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1666
1667 if (numa_node != NUMA_NODE_UNASSIGNED) {
1668 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1669 }
1670
1671 aml_append(dev, build_prt());
1672 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1673 io_ranges, mem_ranges);
1674 aml_append(dev, aml_name_decl("_CRS", crs));
1675 aml_append(scope, dev);
1676 aml_append(ssdt, scope);
1677 }
1678 }
1679
1680 scope = aml_scope("\\_SB.PCI0");
1681 /* build PCI0._CRS */
1682 crs = aml_resource_template();
1683 aml_append(crs,
1684 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1685 0x0000, 0x0, root_bus_limit,
1686 0x0000, root_bus_limit + 1));
1687 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1688
1689 aml_append(crs,
1690 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1691 AML_POS_DECODE, AML_ENTIRE_RANGE,
1692 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1693
1694 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
1695 for (i = 0; i < io_ranges->len; i++) {
1696 entry = g_ptr_array_index(io_ranges, i);
1697 aml_append(crs,
1698 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1699 AML_POS_DECODE, AML_ENTIRE_RANGE,
1700 0x0000, entry->base, entry->limit,
1701 0x0000, entry->limit - entry->base + 1));
1702 }
1703
1704 aml_append(crs,
1705 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1706 AML_CACHEABLE, AML_READ_WRITE,
1707 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1708
1709 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
1710 for (i = 0; i < mem_ranges->len; i++) {
1711 entry = g_ptr_array_index(mem_ranges, i);
1712 aml_append(crs,
1713 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1714 AML_NON_CACHEABLE, AML_READ_WRITE,
1715 0, entry->base, entry->limit,
1716 0, entry->limit - entry->base + 1));
1717 }
1718
1719 if (pci->w64.begin) {
1720 aml_append(crs,
1721 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1722 AML_CACHEABLE, AML_READ_WRITE,
1723 0, pci->w64.begin, pci->w64.end - 1, 0,
1724 pci->w64.end - pci->w64.begin));
1725 }
1726 aml_append(scope, aml_name_decl("_CRS", crs));
1727
1728 /* reserve GPE0 block resources */
1729 dev = aml_device("GPE0");
1730 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1731 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1732 /* device present, functioning, decoding, not shown in UI */
1733 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1734 crs = aml_resource_template();
1735 aml_append(crs,
1736 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1737 );
1738 aml_append(dev, aml_name_decl("_CRS", crs));
1739 aml_append(scope, dev);
1740
1741 g_ptr_array_free(io_ranges, true);
1742 g_ptr_array_free(mem_ranges, true);
1743
1744 /* reserve PCIHP resources */
1745 if (pm->pcihp_io_len) {
1746 dev = aml_device("PHPR");
1747 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1748 aml_append(dev,
1749 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1750 /* device present, functioning, decoding, not shown in UI */
1751 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1752 crs = aml_resource_template();
1753 aml_append(crs,
1754 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1755 pm->pcihp_io_len)
1756 );
1757 aml_append(dev, aml_name_decl("_CRS", crs));
1758 aml_append(scope, dev);
1759 }
1760 aml_append(ssdt, scope);
1761
1762 /* create S3_ / S4_ / S5_ packages if necessary */
1763 scope = aml_scope("\\");
1764 if (!pm->s3_disabled) {
1765 pkg = aml_package(4);
1766 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1767 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1768 aml_append(pkg, aml_int(0)); /* reserved */
1769 aml_append(pkg, aml_int(0)); /* reserved */
1770 aml_append(scope, aml_name_decl("_S3", pkg));
1771 }
1772
1773 if (!pm->s4_disabled) {
1774 pkg = aml_package(4);
1775 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1776 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1777 aml_append(pkg, aml_int(pm->s4_val));
1778 aml_append(pkg, aml_int(0)); /* reserved */
1779 aml_append(pkg, aml_int(0)); /* reserved */
1780 aml_append(scope, aml_name_decl("_S4", pkg));
1781 }
1782
1783 pkg = aml_package(4);
1784 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1785 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1786 aml_append(pkg, aml_int(0)); /* reserved */
1787 aml_append(pkg, aml_int(0)); /* reserved */
1788 aml_append(scope, aml_name_decl("_S5", pkg));
1789 aml_append(ssdt, scope);
1790
1791 if (misc->applesmc_io_base) {
1792 scope = aml_scope("\\_SB.PCI0.ISA");
1793 dev = aml_device("SMC");
1794
1795 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1796 /* device present, functioning, decoding, not shown in UI */
1797 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1798
1799 crs = aml_resource_template();
1800 aml_append(crs,
1801 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1802 0x01, APPLESMC_MAX_DATA_LENGTH)
1803 );
1804 aml_append(crs, aml_irq_no_flags(6));
1805 aml_append(dev, aml_name_decl("_CRS", crs));
1806
1807 aml_append(scope, dev);
1808 aml_append(ssdt, scope);
1809 }
1810
1811 if (misc->pvpanic_port) {
1812 scope = aml_scope("\\_SB.PCI0.ISA");
1813
1814 dev = aml_device("PEVT");
1815 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1816
1817 crs = aml_resource_template();
1818 aml_append(crs,
1819 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1820 );
1821 aml_append(dev, aml_name_decl("_CRS", crs));
1822
1823 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1824 misc->pvpanic_port, 1));
1825 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1826 aml_append(field, aml_named_field("PEPT", 8));
1827 aml_append(dev, field);
1828
1829 /* device present, functioning, decoding, shown in UI */
1830 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1831
1832 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1833 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1834 aml_append(method, aml_return(aml_local(0)));
1835 aml_append(dev, method);
1836
1837 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1838 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1839 aml_append(dev, method);
1840
1841 aml_append(scope, dev);
1842 aml_append(ssdt, scope);
1843 }
1844
1845 sb_scope = aml_scope("\\_SB");
1846 {
1847 build_processor_devices(sb_scope, guest_info->apic_id_limit, cpu, pm);
1848
1849 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
1850 pm->mem_hp_io_len);
1851
1852 {
1853 Object *pci_host;
1854 PCIBus *bus = NULL;
1855
1856 pci_host = acpi_get_i386_pci_host();
1857 if (pci_host) {
1858 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1859 }
1860
1861 if (bus) {
1862 Aml *scope = aml_scope("PCI0");
1863 /* Scan all PCI buses. Generate tables to support hotplug. */
1864 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1865
1866 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1867 dev = aml_device("ISA.TPM");
1868 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1869 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1870 crs = aml_resource_template();
1871 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1872 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1873 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1874 aml_append(dev, aml_name_decl("_CRS", crs));
1875 aml_append(scope, dev);
1876 }
1877
1878 aml_append(sb_scope, scope);
1879 }
1880 }
1881 aml_append(ssdt, sb_scope);
1882 }
1883
1884 /* copy AML table into ACPI tables blob and patch header there */
1885 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1886 build_header(linker, table_data,
1887 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1888 "SSDT", ssdt->buf->len, 1, NULL);
1889 free_aml_allocator();
1890 }
1891
1892 static void
1893 build_hpet(GArray *table_data, GArray *linker)
1894 {
1895 Acpi20Hpet *hpet;
1896
1897 hpet = acpi_data_push(table_data, sizeof(*hpet));
1898 /* Note timer_block_id value must be kept in sync with value advertised by
1899 * emulated hpet
1900 */
1901 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1902 hpet->addr.address = cpu_to_le64(HPET_BASE);
1903 build_header(linker, table_data,
1904 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
1905 }
1906
1907 static void
1908 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1909 {
1910 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1911 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1912
1913 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1914 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1915 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1916
1917 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1918 false /* high memory */);
1919
1920 /* log area start address to be filled by Guest linker */
1921 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1922 ACPI_BUILD_TPMLOG_FILE,
1923 table_data, &tcpa->log_area_start_address,
1924 sizeof(tcpa->log_area_start_address));
1925
1926 build_header(linker, table_data,
1927 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
1928
1929 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1930 }
1931
1932 static void
1933 build_tpm2(GArray *table_data, GArray *linker)
1934 {
1935 Acpi20TPM2 *tpm2_ptr;
1936
1937 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1938
1939 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1940 tpm2_ptr->control_area_address = cpu_to_le64(0);
1941 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1942
1943 build_header(linker, table_data,
1944 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
1945 }
1946
1947 typedef enum {
1948 MEM_AFFINITY_NOFLAGS = 0,
1949 MEM_AFFINITY_ENABLED = (1 << 0),
1950 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1951 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1952 } MemoryAffinityFlags;
1953
1954 static void
1955 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1956 uint64_t len, int node, MemoryAffinityFlags flags)
1957 {
1958 numamem->type = ACPI_SRAT_MEMORY;
1959 numamem->length = sizeof(*numamem);
1960 memset(numamem->proximity, 0, 4);
1961 numamem->proximity[0] = node;
1962 numamem->flags = cpu_to_le32(flags);
1963 numamem->base_addr = cpu_to_le64(base);
1964 numamem->range_length = cpu_to_le64(len);
1965 }
1966
1967 static void
1968 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1969 {
1970 AcpiSystemResourceAffinityTable *srat;
1971 AcpiSratProcessorAffinity *core;
1972 AcpiSratMemoryAffinity *numamem;
1973
1974 int i;
1975 uint64_t curnode;
1976 int srat_start, numa_start, slots;
1977 uint64_t mem_len, mem_base, next_base;
1978 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1979 ram_addr_t hotplugabble_address_space_size =
1980 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1981 NULL);
1982
1983 srat_start = table_data->len;
1984
1985 srat = acpi_data_push(table_data, sizeof *srat);
1986 srat->reserved1 = cpu_to_le32(1);
1987 core = (void *)(srat + 1);
1988
1989 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1990 core = acpi_data_push(table_data, sizeof *core);
1991 core->type = ACPI_SRAT_PROCESSOR;
1992 core->length = sizeof(*core);
1993 core->local_apic_id = i;
1994 curnode = guest_info->node_cpu[i];
1995 core->proximity_lo = curnode;
1996 memset(core->proximity_hi, 0, 3);
1997 core->local_sapic_eid = 0;
1998 core->flags = cpu_to_le32(1);
1999 }
2000
2001
2002 /* the memory map is a bit tricky, it contains at least one hole
2003 * from 640k-1M and possibly another one from 3.5G-4G.
2004 */
2005 next_base = 0;
2006 numa_start = table_data->len;
2007
2008 numamem = acpi_data_push(table_data, sizeof *numamem);
2009 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2010 next_base = 1024 * 1024;
2011 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
2012 mem_base = next_base;
2013 mem_len = guest_info->node_mem[i - 1];
2014 if (i == 1) {
2015 mem_len -= 1024 * 1024;
2016 }
2017 next_base = mem_base + mem_len;
2018
2019 /* Cut out the ACPI_PCI hole */
2020 if (mem_base <= guest_info->ram_size_below_4g &&
2021 next_base > guest_info->ram_size_below_4g) {
2022 mem_len -= next_base - guest_info->ram_size_below_4g;
2023 if (mem_len > 0) {
2024 numamem = acpi_data_push(table_data, sizeof *numamem);
2025 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2026 MEM_AFFINITY_ENABLED);
2027 }
2028 mem_base = 1ULL << 32;
2029 mem_len = next_base - guest_info->ram_size_below_4g;
2030 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
2031 }
2032 numamem = acpi_data_push(table_data, sizeof *numamem);
2033 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2034 MEM_AFFINITY_ENABLED);
2035 }
2036 slots = (table_data->len - numa_start) / sizeof *numamem;
2037 for (; slots < guest_info->numa_nodes + 2; slots++) {
2038 numamem = acpi_data_push(table_data, sizeof *numamem);
2039 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2040 }
2041
2042 /*
2043 * Entry is required for Windows to enable memory hotplug in OS.
2044 * Memory devices may override proximity set by this entry,
2045 * providing _PXM method if necessary.
2046 */
2047 if (hotplugabble_address_space_size) {
2048 numamem = acpi_data_push(table_data, sizeof *numamem);
2049 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2050 hotplugabble_address_space_size, 0,
2051 MEM_AFFINITY_HOTPLUGGABLE |
2052 MEM_AFFINITY_ENABLED);
2053 }
2054
2055 build_header(linker, table_data,
2056 (void *)(table_data->data + srat_start),
2057 "SRAT",
2058 table_data->len - srat_start, 1, NULL);
2059 }
2060
2061 static void
2062 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2063 {
2064 AcpiTableMcfg *mcfg;
2065 const char *sig;
2066 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2067
2068 mcfg = acpi_data_push(table_data, len);
2069 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2070 /* Only a single allocation so no need to play with segments */
2071 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2072 mcfg->allocation[0].start_bus_number = 0;
2073 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2074
2075 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2076 * To avoid table size changes (which create migration issues),
2077 * always create the table even if there are no allocations,
2078 * but set the signature to a reserved value in this case.
2079 * ACPI spec requires OSPMs to ignore such tables.
2080 */
2081 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2082 /* Reserved signature: ignored by OSPM */
2083 sig = "QEMU";
2084 } else {
2085 sig = "MCFG";
2086 }
2087 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
2088 }
2089
2090 static void
2091 build_dmar_q35(GArray *table_data, GArray *linker)
2092 {
2093 int dmar_start = table_data->len;
2094
2095 AcpiTableDmar *dmar;
2096 AcpiDmarHardwareUnit *drhd;
2097
2098 dmar = acpi_data_push(table_data, sizeof(*dmar));
2099 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2100 dmar->flags = 0; /* No intr_remap for now */
2101
2102 /* DMAR Remapping Hardware Unit Definition structure */
2103 drhd = acpi_data_push(table_data, sizeof(*drhd));
2104 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2105 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2106 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2107 drhd->pci_segment = cpu_to_le16(0);
2108 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2109
2110 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2111 "DMAR", table_data->len - dmar_start, 1, NULL);
2112 }
2113
2114 static void
2115 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
2116 {
2117 AcpiTableHeader *dsdt;
2118
2119 assert(misc->dsdt_code && misc->dsdt_size);
2120
2121 dsdt = acpi_data_push(table_data, misc->dsdt_size);
2122 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
2123
2124 memset(dsdt, 0, sizeof *dsdt);
2125 build_header(linker, table_data, dsdt, "DSDT",
2126 misc->dsdt_size, 1, NULL);
2127 }
2128
2129 static GArray *
2130 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2131 {
2132 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2133
2134 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2135 true /* fseg memory */);
2136
2137 memcpy(&rsdp->signature, "RSD PTR ", 8);
2138 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2139 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2140 /* Address to be filled by Guest linker */
2141 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2142 ACPI_BUILD_TABLE_FILE,
2143 rsdp_table, &rsdp->rsdt_physical_address,
2144 sizeof rsdp->rsdt_physical_address);
2145 rsdp->checksum = 0;
2146 /* Checksum to be filled by Guest linker */
2147 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2148 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
2149
2150 return rsdp_table;
2151 }
2152
2153 typedef
2154 struct AcpiBuildState {
2155 /* Copy of table in RAM (for patching). */
2156 MemoryRegion *table_mr;
2157 /* Is table patched? */
2158 uint8_t patched;
2159 PcGuestInfo *guest_info;
2160 void *rsdp;
2161 MemoryRegion *rsdp_mr;
2162 MemoryRegion *linker_mr;
2163 } AcpiBuildState;
2164
2165 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2166 {
2167 Object *pci_host;
2168 QObject *o;
2169
2170 pci_host = acpi_get_i386_pci_host();
2171 g_assert(pci_host);
2172
2173 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2174 if (!o) {
2175 return false;
2176 }
2177 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2178 qobject_decref(o);
2179
2180 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2181 assert(o);
2182 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2183 qobject_decref(o);
2184 return true;
2185 }
2186
2187 static bool acpi_has_iommu(void)
2188 {
2189 bool ambiguous;
2190 Object *intel_iommu;
2191
2192 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2193 &ambiguous);
2194 return intel_iommu && !ambiguous;
2195 }
2196
2197 static bool acpi_has_nvdimm(void)
2198 {
2199 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2200
2201 return pcms->nvdimm;
2202 }
2203
2204 static
2205 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
2206 {
2207 GArray *table_offsets;
2208 unsigned facs, ssdt, dsdt, rsdt;
2209 AcpiCpuInfo cpu;
2210 AcpiPmInfo pm;
2211 AcpiMiscInfo misc;
2212 AcpiMcfgInfo mcfg;
2213 PcPciInfo pci;
2214 uint8_t *u;
2215 size_t aml_len = 0;
2216 GArray *tables_blob = tables->table_data;
2217
2218 acpi_get_cpu_info(&cpu);
2219 acpi_get_pm_info(&pm);
2220 acpi_get_dsdt(&misc);
2221 acpi_get_misc_info(&misc);
2222 acpi_get_pci_info(&pci);
2223
2224 table_offsets = g_array_new(false, true /* clear */,
2225 sizeof(uint32_t));
2226 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2227
2228 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2229 64 /* Ensure FACS is aligned */,
2230 false /* high memory */);
2231
2232 /*
2233 * FACS is pointed to by FADT.
2234 * We place it first since it's the only table that has alignment
2235 * requirements.
2236 */
2237 facs = tables_blob->len;
2238 build_facs(tables_blob, tables->linker, guest_info);
2239
2240 /* DSDT is pointed to by FADT */
2241 dsdt = tables_blob->len;
2242 build_dsdt(tables_blob, tables->linker, &misc);
2243
2244 /* Count the size of the DSDT and SSDT, we will need it for legacy
2245 * sizing of ACPI tables.
2246 */
2247 aml_len += tables_blob->len - dsdt;
2248
2249 /* ACPI tables pointed to by RSDT */
2250 acpi_add_table(table_offsets, tables_blob);
2251 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
2252
2253 ssdt = tables_blob->len;
2254 acpi_add_table(table_offsets, tables_blob);
2255 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
2256 guest_info);
2257 aml_len += tables_blob->len - ssdt;
2258
2259 acpi_add_table(table_offsets, tables_blob);
2260 build_madt(tables_blob, tables->linker, &cpu, guest_info);
2261
2262 if (misc.has_hpet) {
2263 acpi_add_table(table_offsets, tables_blob);
2264 build_hpet(tables_blob, tables->linker);
2265 }
2266 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2267 acpi_add_table(table_offsets, tables_blob);
2268 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2269
2270 if (misc.tpm_version == TPM_VERSION_2_0) {
2271 acpi_add_table(table_offsets, tables_blob);
2272 build_tpm2(tables_blob, tables->linker);
2273 }
2274 }
2275 if (guest_info->numa_nodes) {
2276 acpi_add_table(table_offsets, tables_blob);
2277 build_srat(tables_blob, tables->linker, guest_info);
2278 }
2279 if (acpi_get_mcfg(&mcfg)) {
2280 acpi_add_table(table_offsets, tables_blob);
2281 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2282 }
2283 if (acpi_has_iommu()) {
2284 acpi_add_table(table_offsets, tables_blob);
2285 build_dmar_q35(tables_blob, tables->linker);
2286 }
2287
2288 if (acpi_has_nvdimm()) {
2289 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2290 }
2291
2292 /* Add tables supplied by user (if any) */
2293 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2294 unsigned len = acpi_table_len(u);
2295
2296 acpi_add_table(table_offsets, tables_blob);
2297 g_array_append_vals(tables_blob, u, len);
2298 }
2299
2300 /* RSDT is pointed to by RSDP */
2301 rsdt = tables_blob->len;
2302 build_rsdt(tables_blob, tables->linker, table_offsets);
2303
2304 /* RSDP is in FSEG memory, so allocate it separately */
2305 build_rsdp(tables->rsdp, tables->linker, rsdt);
2306
2307 /* We'll expose it all to Guest so we want to reduce
2308 * chance of size changes.
2309 *
2310 * We used to align the tables to 4k, but of course this would
2311 * too simple to be enough. 4k turned out to be too small an
2312 * alignment very soon, and in fact it is almost impossible to
2313 * keep the table size stable for all (max_cpus, max_memory_slots)
2314 * combinations. So the table size is always 64k for pc-i440fx-2.1
2315 * and we give an error if the table grows beyond that limit.
2316 *
2317 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2318 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2319 * than 2.0 and we can always pad the smaller tables with zeros. We can
2320 * then use the exact size of the 2.0 tables.
2321 *
2322 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2323 */
2324 if (guest_info->legacy_acpi_table_size) {
2325 /* Subtracting aml_len gives the size of fixed tables. Then add the
2326 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2327 */
2328 int legacy_aml_len =
2329 guest_info->legacy_acpi_table_size +
2330 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2331 int legacy_table_size =
2332 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2333 ACPI_BUILD_ALIGN_SIZE);
2334 if (tables_blob->len > legacy_table_size) {
2335 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2336 error_report("Warning: migration may not work.");
2337 }
2338 g_array_set_size(tables_blob, legacy_table_size);
2339 } else {
2340 /* Make sure we have a buffer in case we need to resize the tables. */
2341 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2342 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2343 error_report("Warning: ACPI tables are larger than 64k.");
2344 error_report("Warning: migration may not work.");
2345 error_report("Warning: please remove CPUs, NUMA nodes, "
2346 "memory slots or PCI bridges.");
2347 }
2348 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2349 }
2350
2351 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2352
2353 /* Cleanup memory that's no longer used. */
2354 g_array_free(table_offsets, true);
2355 }
2356
2357 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2358 {
2359 uint32_t size = acpi_data_len(data);
2360
2361 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2362 memory_region_ram_resize(mr, size, &error_abort);
2363
2364 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2365 memory_region_set_dirty(mr, 0, size);
2366 }
2367
2368 static void acpi_build_update(void *build_opaque)
2369 {
2370 AcpiBuildState *build_state = build_opaque;
2371 AcpiBuildTables tables;
2372
2373 /* No state to update or already patched? Nothing to do. */
2374 if (!build_state || build_state->patched) {
2375 return;
2376 }
2377 build_state->patched = 1;
2378
2379 acpi_build_tables_init(&tables);
2380
2381 acpi_build(build_state->guest_info, &tables);
2382
2383 acpi_ram_update(build_state->table_mr, tables.table_data);
2384
2385 if (build_state->rsdp) {
2386 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2387 } else {
2388 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2389 }
2390
2391 acpi_ram_update(build_state->linker_mr, tables.linker);
2392 acpi_build_tables_cleanup(&tables, true);
2393 }
2394
2395 static void acpi_build_reset(void *build_opaque)
2396 {
2397 AcpiBuildState *build_state = build_opaque;
2398 build_state->patched = 0;
2399 }
2400
2401 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2402 GArray *blob, const char *name,
2403 uint64_t max_size)
2404 {
2405 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2406 name, acpi_build_update, build_state);
2407 }
2408
2409 static const VMStateDescription vmstate_acpi_build = {
2410 .name = "acpi_build",
2411 .version_id = 1,
2412 .minimum_version_id = 1,
2413 .fields = (VMStateField[]) {
2414 VMSTATE_UINT8(patched, AcpiBuildState),
2415 VMSTATE_END_OF_LIST()
2416 },
2417 };
2418
2419 void acpi_setup(PcGuestInfo *guest_info)
2420 {
2421 AcpiBuildTables tables;
2422 AcpiBuildState *build_state;
2423
2424 if (!guest_info->fw_cfg) {
2425 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2426 return;
2427 }
2428
2429 if (!guest_info->has_acpi_build) {
2430 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2431 return;
2432 }
2433
2434 if (!acpi_enabled) {
2435 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2436 return;
2437 }
2438
2439 build_state = g_malloc0(sizeof *build_state);
2440
2441 build_state->guest_info = guest_info;
2442
2443 acpi_set_pci_info();
2444
2445 acpi_build_tables_init(&tables);
2446 acpi_build(build_state->guest_info, &tables);
2447
2448 /* Now expose it all to Guest */
2449 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2450 ACPI_BUILD_TABLE_FILE,
2451 ACPI_BUILD_TABLE_MAX_SIZE);
2452 assert(build_state->table_mr != NULL);
2453
2454 build_state->linker_mr =
2455 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2456
2457 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2458 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2459
2460 if (!guest_info->rsdp_in_ram) {
2461 /*
2462 * Keep for compatibility with old machine types.
2463 * Though RSDP is small, its contents isn't immutable, so
2464 * we'll update it along with the rest of tables on guest access.
2465 */
2466 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2467
2468 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2469 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
2470 acpi_build_update, build_state,
2471 build_state->rsdp, rsdp_size);
2472 build_state->rsdp_mr = NULL;
2473 } else {
2474 build_state->rsdp = NULL;
2475 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2476 ACPI_BUILD_RSDP_FILE, 0);
2477 }
2478
2479 qemu_register_reset(acpi_build_reset, build_state);
2480 acpi_build_reset(build_state);
2481 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2482
2483 /* Cleanup tables but don't free the memory: we track it
2484 * in build_state.
2485 */
2486 acpi_build_tables_cleanup(&tables, false);
2487 }
AR7 emulation for QEMU