2 * Channel subsystem base support.
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
13 #include "qemu/bitops.h"
14 #include "exec/address-spaces.h"
20 typedef struct CrwContainer
{
22 QTAILQ_ENTRY(CrwContainer
) sibling
;
25 typedef struct ChpInfo
{
31 typedef struct SubchSet
{
32 SubchDev
*sch
[MAX_SCHID
+ 1];
33 unsigned long schids_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
34 unsigned long devnos_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
37 typedef struct CssImage
{
38 SubchSet
*sch_set
[MAX_SSID
+ 1];
39 ChpInfo chpids
[MAX_CHPID
+ 1];
42 typedef struct ChannelSubSys
{
43 QTAILQ_HEAD(, CrwContainer
) pending_crws
;
50 CssImage
*css
[MAX_CSSID
+ 1];
51 uint8_t default_cssid
;
54 static ChannelSubSys
*channel_subsys
;
56 int css_create_css_image(uint8_t cssid
, bool default_image
)
58 trace_css_new_image(cssid
, default_image
? "(default)" : "");
59 if (cssid
> MAX_CSSID
) {
62 if (channel_subsys
->css
[cssid
]) {
65 channel_subsys
->css
[cssid
] = g_malloc0(sizeof(CssImage
));
67 channel_subsys
->default_cssid
= cssid
;
72 uint16_t css_build_subchannel_id(SubchDev
*sch
)
74 if (channel_subsys
->max_cssid
> 0) {
75 return (sch
->cssid
<< 8) | (1 << 3) | (sch
->ssid
<< 1) | 1;
77 return (sch
->ssid
<< 1) | 1;
80 static void css_inject_io_interrupt(SubchDev
*sch
)
82 S390CPU
*cpu
= s390_cpu_addr2state(0);
83 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
85 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
86 sch
->curr_status
.pmcw
.intparm
, isc
, "");
87 s390_io_interrupt(cpu
,
88 css_build_subchannel_id(sch
),
90 sch
->curr_status
.pmcw
.intparm
,
94 void css_conditional_io_interrupt(SubchDev
*sch
)
97 * If the subchannel is not currently status pending, make it pending
100 if (!(sch
->curr_status
.scsw
.ctrl
& SCSW_STCTL_STATUS_PEND
)) {
101 S390CPU
*cpu
= s390_cpu_addr2state(0);
102 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
104 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
105 sch
->curr_status
.pmcw
.intparm
, isc
,
107 sch
->curr_status
.scsw
.ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
108 sch
->curr_status
.scsw
.ctrl
|=
109 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
110 /* Inject an I/O interrupt. */
111 s390_io_interrupt(cpu
,
112 css_build_subchannel_id(sch
),
114 sch
->curr_status
.pmcw
.intparm
,
119 void css_adapter_interrupt(uint8_t isc
)
121 S390CPU
*cpu
= s390_cpu_addr2state(0);
122 uint32_t io_int_word
= (isc
<< 27) | IO_INT_WORD_AI
;
124 trace_css_adapter_interrupt(isc
);
125 s390_io_interrupt(cpu
, 0, 0, 0, io_int_word
);
128 static void sch_handle_clear_func(SubchDev
*sch
)
130 PMCW
*p
= &sch
->curr_status
.pmcw
;
131 SCSW
*s
= &sch
->curr_status
.scsw
;
134 /* Path management: In our simple css, we always choose the only path. */
137 /* Reset values prior to 'issuing the clear signal'. */
140 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
142 /* We always 'attempt to issue the clear signal', and we always succeed. */
144 sch
->channel_prog
= 0x0;
145 sch
->last_cmd_valid
= false;
146 s
->ctrl
&= ~SCSW_ACTL_CLEAR_PEND
;
147 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
155 static void sch_handle_halt_func(SubchDev
*sch
)
158 PMCW
*p
= &sch
->curr_status
.pmcw
;
159 SCSW
*s
= &sch
->curr_status
.scsw
;
162 /* Path management: In our simple css, we always choose the only path. */
165 /* We always 'attempt to issue the halt signal', and we always succeed. */
167 sch
->channel_prog
= 0x0;
168 sch
->last_cmd_valid
= false;
169 s
->ctrl
&= ~SCSW_ACTL_HALT_PEND
;
170 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
172 if ((s
->ctrl
& (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) ||
173 !((s
->ctrl
& SCSW_ACTL_START_PEND
) ||
174 (s
->ctrl
& SCSW_ACTL_SUSP
))) {
175 s
->dstat
= SCSW_DSTAT_DEVICE_END
;
182 static void copy_sense_id_to_guest(SenseId
*dest
, SenseId
*src
)
186 dest
->reserved
= src
->reserved
;
187 dest
->cu_type
= cpu_to_be16(src
->cu_type
);
188 dest
->cu_model
= src
->cu_model
;
189 dest
->dev_type
= cpu_to_be16(src
->dev_type
);
190 dest
->dev_model
= src
->dev_model
;
191 dest
->unused
= src
->unused
;
192 for (i
= 0; i
< ARRAY_SIZE(dest
->ciw
); i
++) {
193 dest
->ciw
[i
].type
= src
->ciw
[i
].type
;
194 dest
->ciw
[i
].command
= src
->ciw
[i
].command
;
195 dest
->ciw
[i
].count
= cpu_to_be16(src
->ciw
[i
].count
);
199 static CCW1
copy_ccw_from_guest(hwaddr addr
)
204 cpu_physical_memory_read(addr
, &tmp
, sizeof(tmp
));
205 ret
.cmd_code
= tmp
.cmd_code
;
206 ret
.flags
= tmp
.flags
;
207 ret
.count
= be16_to_cpu(tmp
.count
);
208 ret
.cda
= be32_to_cpu(tmp
.cda
);
213 static int css_interpret_ccw(SubchDev
*sch
, hwaddr ccw_addr
)
224 ccw
= copy_ccw_from_guest(ccw_addr
);
226 /* Check for invalid command codes. */
227 if ((ccw
.cmd_code
& 0x0f) == 0) {
230 if (((ccw
.cmd_code
& 0x0f) == CCW_CMD_TIC
) &&
231 ((ccw
.cmd_code
& 0xf0) != 0)) {
235 if (ccw
.flags
& CCW_FLAG_SUSPEND
) {
239 check_len
= !((ccw
.flags
& CCW_FLAG_SLI
) && !(ccw
.flags
& CCW_FLAG_DC
));
241 /* Look at the command. */
242 switch (ccw
.cmd_code
) {
247 case CCW_CMD_BASIC_SENSE
:
249 if (ccw
.count
!= sizeof(sch
->sense_data
)) {
254 len
= MIN(ccw
.count
, sizeof(sch
->sense_data
));
255 cpu_physical_memory_write(ccw
.cda
, sch
->sense_data
, len
);
256 sch
->curr_status
.scsw
.count
= ccw
.count
- len
;
257 memset(sch
->sense_data
, 0, sizeof(sch
->sense_data
));
260 case CCW_CMD_SENSE_ID
:
264 copy_sense_id_to_guest(&sense_id
, &sch
->id
);
265 /* Sense ID information is device specific. */
267 if (ccw
.count
!= sizeof(sense_id
)) {
272 len
= MIN(ccw
.count
, sizeof(sense_id
));
274 * Only indicate 0xff in the first sense byte if we actually
275 * have enough place to store at least bytes 0-3.
278 sense_id
.reserved
= 0xff;
280 sense_id
.reserved
= 0;
282 cpu_physical_memory_write(ccw
.cda
, &sense_id
, len
);
283 sch
->curr_status
.scsw
.count
= ccw
.count
- len
;
288 if (sch
->last_cmd_valid
&& (sch
->last_cmd
.cmd_code
== CCW_CMD_TIC
)) {
292 if (ccw
.flags
& (CCW_FLAG_CC
| CCW_FLAG_DC
)) {
296 sch
->channel_prog
= ccw
.cda
;
301 /* Handle device specific commands. */
302 ret
= sch
->ccw_cb(sch
, ccw
);
309 sch
->last_cmd_valid
= true;
311 if (ccw
.flags
& CCW_FLAG_CC
) {
312 sch
->channel_prog
+= 8;
320 static void sch_handle_start_func(SubchDev
*sch
)
323 PMCW
*p
= &sch
->curr_status
.pmcw
;
324 SCSW
*s
= &sch
->curr_status
.scsw
;
329 /* Path management: In our simple css, we always choose the only path. */
332 if (!(s
->ctrl
& SCSW_ACTL_SUSP
)) {
333 /* Look at the orb and try to execute the channel program. */
334 p
->intparm
= orb
->intparm
;
335 if (!(orb
->lpm
& path
)) {
336 /* Generate a deferred cc 3 condition. */
337 s
->flags
|= SCSW_FLAGS_MASK_CC
;
338 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
339 s
->ctrl
|= (SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
);
343 s
->ctrl
&= ~(SCSW_ACTL_SUSP
| SCSW_ACTL_RESUME_PEND
);
345 sch
->last_cmd_valid
= false;
347 ret
= css_interpret_ccw(sch
, sch
->channel_prog
);
350 /* ccw chain, continue processing */
354 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
355 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
356 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
357 SCSW_STCTL_STATUS_PEND
;
358 s
->dstat
= SCSW_DSTAT_CHANNEL_END
| SCSW_DSTAT_DEVICE_END
;
361 /* unsupported command, generate unit check (command reject) */
362 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
363 s
->dstat
= SCSW_DSTAT_UNIT_CHECK
;
364 /* Set sense bit 0 in ecw0. */
365 sch
->sense_data
[0] = 0x80;
366 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
367 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
368 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
371 /* memory problem, generate channel data check */
372 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
373 s
->cstat
= SCSW_CSTAT_DATA_CHECK
;
374 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
375 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
376 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
379 /* subchannel busy, generate deferred cc 1 */
380 s
->flags
&= ~SCSW_FLAGS_MASK_CC
;
381 s
->flags
|= (1 << 8);
382 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
383 s
->ctrl
|= SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
386 /* channel program has been suspended */
387 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
388 s
->ctrl
|= SCSW_ACTL_SUSP
;
391 /* error, generate channel program check */
392 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
393 s
->cstat
= SCSW_CSTAT_PROG_CHECK
;
394 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
395 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
396 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
399 } while (ret
== -EAGAIN
);
404 * On real machines, this would run asynchronously to the main vcpus.
405 * We might want to make some parts of the ssch handling (interpreting
406 * read/writes) asynchronous later on if we start supporting more than
407 * our current very simple devices.
409 static void do_subchannel_work(SubchDev
*sch
)
412 SCSW
*s
= &sch
->curr_status
.scsw
;
414 if (s
->ctrl
& SCSW_FCTL_CLEAR_FUNC
) {
415 sch_handle_clear_func(sch
);
416 } else if (s
->ctrl
& SCSW_FCTL_HALT_FUNC
) {
417 sch_handle_halt_func(sch
);
418 } else if (s
->ctrl
& SCSW_FCTL_START_FUNC
) {
419 sch_handle_start_func(sch
);
424 css_inject_io_interrupt(sch
);
427 static void copy_pmcw_to_guest(PMCW
*dest
, const PMCW
*src
)
431 dest
->intparm
= cpu_to_be32(src
->intparm
);
432 dest
->flags
= cpu_to_be16(src
->flags
);
433 dest
->devno
= cpu_to_be16(src
->devno
);
434 dest
->lpm
= src
->lpm
;
435 dest
->pnom
= src
->pnom
;
436 dest
->lpum
= src
->lpum
;
437 dest
->pim
= src
->pim
;
438 dest
->mbi
= cpu_to_be16(src
->mbi
);
439 dest
->pom
= src
->pom
;
440 dest
->pam
= src
->pam
;
441 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
442 dest
->chpid
[i
] = src
->chpid
[i
];
444 dest
->chars
= cpu_to_be32(src
->chars
);
447 static void copy_scsw_to_guest(SCSW
*dest
, const SCSW
*src
)
449 dest
->flags
= cpu_to_be16(src
->flags
);
450 dest
->ctrl
= cpu_to_be16(src
->ctrl
);
451 dest
->cpa
= cpu_to_be32(src
->cpa
);
452 dest
->dstat
= src
->dstat
;
453 dest
->cstat
= src
->cstat
;
454 dest
->count
= cpu_to_be16(src
->count
);
457 static void copy_schib_to_guest(SCHIB
*dest
, const SCHIB
*src
)
461 copy_pmcw_to_guest(&dest
->pmcw
, &src
->pmcw
);
462 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
463 dest
->mba
= cpu_to_be64(src
->mba
);
464 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
465 dest
->mda
[i
] = src
->mda
[i
];
469 int css_do_stsch(SubchDev
*sch
, SCHIB
*schib
)
471 /* Use current status. */
472 copy_schib_to_guest(schib
, &sch
->curr_status
);
476 static void copy_pmcw_from_guest(PMCW
*dest
, const PMCW
*src
)
480 dest
->intparm
= be32_to_cpu(src
->intparm
);
481 dest
->flags
= be16_to_cpu(src
->flags
);
482 dest
->devno
= be16_to_cpu(src
->devno
);
483 dest
->lpm
= src
->lpm
;
484 dest
->pnom
= src
->pnom
;
485 dest
->lpum
= src
->lpum
;
486 dest
->pim
= src
->pim
;
487 dest
->mbi
= be16_to_cpu(src
->mbi
);
488 dest
->pom
= src
->pom
;
489 dest
->pam
= src
->pam
;
490 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
491 dest
->chpid
[i
] = src
->chpid
[i
];
493 dest
->chars
= be32_to_cpu(src
->chars
);
496 static void copy_scsw_from_guest(SCSW
*dest
, const SCSW
*src
)
498 dest
->flags
= be16_to_cpu(src
->flags
);
499 dest
->ctrl
= be16_to_cpu(src
->ctrl
);
500 dest
->cpa
= be32_to_cpu(src
->cpa
);
501 dest
->dstat
= src
->dstat
;
502 dest
->cstat
= src
->cstat
;
503 dest
->count
= be16_to_cpu(src
->count
);
506 static void copy_schib_from_guest(SCHIB
*dest
, const SCHIB
*src
)
510 copy_pmcw_from_guest(&dest
->pmcw
, &src
->pmcw
);
511 copy_scsw_from_guest(&dest
->scsw
, &src
->scsw
);
512 dest
->mba
= be64_to_cpu(src
->mba
);
513 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
514 dest
->mda
[i
] = src
->mda
[i
];
518 int css_do_msch(SubchDev
*sch
, SCHIB
*orig_schib
)
520 SCSW
*s
= &sch
->curr_status
.scsw
;
521 PMCW
*p
= &sch
->curr_status
.pmcw
;
525 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_DNV
)) {
530 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
536 (SCSW_FCTL_START_FUNC
|SCSW_FCTL_HALT_FUNC
|SCSW_FCTL_CLEAR_FUNC
)) {
541 copy_schib_from_guest(&schib
, orig_schib
);
542 /* Only update the program-modifiable fields. */
543 p
->intparm
= schib
.pmcw
.intparm
;
544 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
545 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
547 p
->flags
|= schib
.pmcw
.flags
&
548 (PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
549 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
551 p
->lpm
= schib
.pmcw
.lpm
;
552 p
->mbi
= schib
.pmcw
.mbi
;
553 p
->pom
= schib
.pmcw
.pom
;
554 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
555 p
->chars
|= schib
.pmcw
.chars
&
556 (PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
557 sch
->curr_status
.mba
= schib
.mba
;
565 int css_do_xsch(SubchDev
*sch
)
567 SCSW
*s
= &sch
->curr_status
.scsw
;
568 PMCW
*p
= &sch
->curr_status
.pmcw
;
571 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
576 if (!(s
->ctrl
& SCSW_CTRL_MASK_FCTL
) ||
577 ((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
579 (SCSW_ACTL_RESUME_PEND
| SCSW_ACTL_START_PEND
| SCSW_ACTL_SUSP
))) ||
580 (s
->ctrl
& SCSW_ACTL_SUBCH_ACTIVE
)) {
585 if (s
->ctrl
& SCSW_CTRL_MASK_STCTL
) {
590 /* Cancel the current operation. */
591 s
->ctrl
&= ~(SCSW_FCTL_START_FUNC
|
592 SCSW_ACTL_RESUME_PEND
|
593 SCSW_ACTL_START_PEND
|
595 sch
->channel_prog
= 0x0;
596 sch
->last_cmd_valid
= false;
606 int css_do_csch(SubchDev
*sch
)
608 SCSW
*s
= &sch
->curr_status
.scsw
;
609 PMCW
*p
= &sch
->curr_status
.pmcw
;
612 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
617 /* Trigger the clear function. */
618 s
->ctrl
&= ~(SCSW_CTRL_MASK_FCTL
| SCSW_CTRL_MASK_ACTL
);
619 s
->ctrl
|= SCSW_FCTL_CLEAR_FUNC
| SCSW_FCTL_CLEAR_FUNC
;
621 do_subchannel_work(sch
);
628 int css_do_hsch(SubchDev
*sch
)
630 SCSW
*s
= &sch
->curr_status
.scsw
;
631 PMCW
*p
= &sch
->curr_status
.pmcw
;
634 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
639 if (((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_STATUS_PEND
) ||
640 (s
->ctrl
& (SCSW_STCTL_PRIMARY
|
641 SCSW_STCTL_SECONDARY
|
642 SCSW_STCTL_ALERT
))) {
647 if (s
->ctrl
& (SCSW_FCTL_HALT_FUNC
| SCSW_FCTL_CLEAR_FUNC
)) {
652 /* Trigger the halt function. */
653 s
->ctrl
|= SCSW_FCTL_HALT_FUNC
;
654 s
->ctrl
&= ~SCSW_FCTL_START_FUNC
;
655 if (((s
->ctrl
& SCSW_CTRL_MASK_ACTL
) ==
656 (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) &&
657 ((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_INTERMEDIATE
)) {
658 s
->ctrl
&= ~SCSW_STCTL_STATUS_PEND
;
660 s
->ctrl
|= SCSW_ACTL_HALT_PEND
;
662 do_subchannel_work(sch
);
669 static void css_update_chnmon(SubchDev
*sch
)
671 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_MME
)) {
675 /* The counter is conveniently located at the beginning of the struct. */
676 if (sch
->curr_status
.pmcw
.chars
& PMCW_CHARS_MASK_MBFC
) {
677 /* Format 1, per-subchannel area. */
680 count
= ldl_phys(&address_space_memory
, sch
->curr_status
.mba
);
682 stl_phys(&address_space_memory
, sch
->curr_status
.mba
, count
);
684 /* Format 0, global area. */
688 offset
= sch
->curr_status
.pmcw
.mbi
<< 5;
689 count
= lduw_phys(&address_space_memory
,
690 channel_subsys
->chnmon_area
+ offset
);
692 stw_phys(&address_space_memory
,
693 channel_subsys
->chnmon_area
+ offset
, count
);
697 int css_do_ssch(SubchDev
*sch
, ORB
*orb
)
699 SCSW
*s
= &sch
->curr_status
.scsw
;
700 PMCW
*p
= &sch
->curr_status
.pmcw
;
703 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
708 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
713 if (s
->ctrl
& (SCSW_FCTL_START_FUNC
|
714 SCSW_FCTL_HALT_FUNC
|
715 SCSW_FCTL_CLEAR_FUNC
)) {
720 /* If monitoring is active, update counter. */
721 if (channel_subsys
->chnmon_active
) {
722 css_update_chnmon(sch
);
725 sch
->channel_prog
= orb
->cpa
;
726 /* Trigger the start function. */
727 s
->ctrl
|= (SCSW_FCTL_START_FUNC
| SCSW_ACTL_START_PEND
);
728 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
730 do_subchannel_work(sch
);
737 static void copy_irb_to_guest(IRB
*dest
, const IRB
*src
)
741 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
743 for (i
= 0; i
< ARRAY_SIZE(dest
->esw
); i
++) {
744 dest
->esw
[i
] = cpu_to_be32(src
->esw
[i
]);
746 for (i
= 0; i
< ARRAY_SIZE(dest
->ecw
); i
++) {
747 dest
->ecw
[i
] = cpu_to_be32(src
->ecw
[i
]);
749 for (i
= 0; i
< ARRAY_SIZE(dest
->emw
); i
++) {
750 dest
->emw
[i
] = cpu_to_be32(src
->emw
[i
]);
754 int css_do_tsch(SubchDev
*sch
, IRB
*target_irb
)
756 SCSW
*s
= &sch
->curr_status
.scsw
;
757 PMCW
*p
= &sch
->curr_status
.pmcw
;
764 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
769 stctl
= s
->ctrl
& SCSW_CTRL_MASK_STCTL
;
770 fctl
= s
->ctrl
& SCSW_CTRL_MASK_FCTL
;
771 actl
= s
->ctrl
& SCSW_CTRL_MASK_ACTL
;
773 /* Prepare the irb for the guest. */
774 memset(&irb
, 0, sizeof(IRB
));
776 /* Copy scsw from current status. */
777 memcpy(&irb
.scsw
, s
, sizeof(SCSW
));
778 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
779 if (s
->cstat
& (SCSW_CSTAT_DATA_CHECK
|
780 SCSW_CSTAT_CHN_CTRL_CHK
|
781 SCSW_CSTAT_INTF_CTRL_CHK
)) {
782 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
;
783 irb
.esw
[0] = 0x04804000;
785 irb
.esw
[0] = 0x00800000;
787 /* If a unit check is pending, copy sense data. */
788 if ((s
->dstat
& SCSW_DSTAT_UNIT_CHECK
) &&
789 (p
->chars
& PMCW_CHARS_MASK_CSENSE
)) {
790 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
| SCSW_FLAGS_MASK_ECTL
;
791 memcpy(irb
.ecw
, sch
->sense_data
, sizeof(sch
->sense_data
));
792 irb
.esw
[1] = 0x01000000 | (sizeof(sch
->sense_data
) << 8);
795 /* Store the irb to the guest. */
796 copy_irb_to_guest(target_irb
, &irb
);
798 /* Clear conditions on subchannel, if applicable. */
799 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
800 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
801 if ((stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) ||
802 ((fctl
& SCSW_FCTL_HALT_FUNC
) &&
803 (actl
& SCSW_ACTL_SUSP
))) {
804 s
->ctrl
&= ~SCSW_CTRL_MASK_FCTL
;
806 if (stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) {
807 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
808 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
809 SCSW_ACTL_START_PEND
|
810 SCSW_ACTL_HALT_PEND
|
811 SCSW_ACTL_CLEAR_PEND
|
814 if ((actl
& SCSW_ACTL_SUSP
) &&
815 (fctl
& SCSW_FCTL_START_FUNC
)) {
816 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
817 if (fctl
& SCSW_FCTL_HALT_FUNC
) {
818 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
819 SCSW_ACTL_START_PEND
|
820 SCSW_ACTL_HALT_PEND
|
821 SCSW_ACTL_CLEAR_PEND
|
824 s
->ctrl
&= ~SCSW_ACTL_RESUME_PEND
;
828 /* Clear pending sense data. */
829 if (p
->chars
& PMCW_CHARS_MASK_CSENSE
) {
830 memset(sch
->sense_data
, 0 , sizeof(sch
->sense_data
));
834 ret
= ((stctl
& SCSW_STCTL_STATUS_PEND
) == 0);
840 static void copy_crw_to_guest(CRW
*dest
, const CRW
*src
)
842 dest
->flags
= cpu_to_be16(src
->flags
);
843 dest
->rsid
= cpu_to_be16(src
->rsid
);
846 int css_do_stcrw(CRW
*crw
)
848 CrwContainer
*crw_cont
;
851 crw_cont
= QTAILQ_FIRST(&channel_subsys
->pending_crws
);
853 QTAILQ_REMOVE(&channel_subsys
->pending_crws
, crw_cont
, sibling
);
854 copy_crw_to_guest(crw
, &crw_cont
->crw
);
858 /* List was empty, turn crw machine checks on again. */
859 memset(crw
, 0, sizeof(*crw
));
860 channel_subsys
->do_crw_mchk
= true;
867 int css_do_tpi(IOIntCode
*int_code
, int lowcore
)
869 /* No pending interrupts for !KVM. */
873 int css_collect_chp_desc(int m
, uint8_t cssid
, uint8_t f_chpid
, uint8_t l_chpid
,
878 uint32_t chpid_type_word
;
882 css
= channel_subsys
->css
[channel_subsys
->default_cssid
];
884 css
= channel_subsys
->css
[cssid
];
890 for (i
= f_chpid
; i
<= l_chpid
; i
++) {
891 if (css
->chpids
[i
].in_use
) {
892 chpid_type_word
= 0x80000000 | (css
->chpids
[i
].type
<< 8) | i
;
894 words
[0] = cpu_to_be32(chpid_type_word
);
896 memcpy(buf
+ desc_size
, words
, 8);
898 } else if (rfmt
== 1) {
899 words
[0] = cpu_to_be32(chpid_type_word
);
907 memcpy(buf
+ desc_size
, words
, 32);
915 void css_do_schm(uint8_t mbk
, int update
, int dct
, uint64_t mbo
)
917 /* dct is currently ignored (not really meaningful for our devices) */
918 /* TODO: Don't ignore mbk. */
919 if (update
&& !channel_subsys
->chnmon_active
) {
920 /* Enable measuring. */
921 channel_subsys
->chnmon_area
= mbo
;
922 channel_subsys
->chnmon_active
= true;
924 if (!update
&& channel_subsys
->chnmon_active
) {
925 /* Disable measuring. */
926 channel_subsys
->chnmon_area
= 0;
927 channel_subsys
->chnmon_active
= false;
931 int css_do_rsch(SubchDev
*sch
)
933 SCSW
*s
= &sch
->curr_status
.scsw
;
934 PMCW
*p
= &sch
->curr_status
.pmcw
;
937 if (!(p
->flags
& (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
))) {
942 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
947 if (((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
948 (s
->ctrl
& SCSW_ACTL_RESUME_PEND
) ||
949 (!(s
->ctrl
& SCSW_ACTL_SUSP
))) {
954 /* If monitoring is active, update counter. */
955 if (channel_subsys
->chnmon_active
) {
956 css_update_chnmon(sch
);
959 s
->ctrl
|= SCSW_ACTL_RESUME_PEND
;
960 do_subchannel_work(sch
);
967 int css_do_rchp(uint8_t cssid
, uint8_t chpid
)
971 if (cssid
> channel_subsys
->max_cssid
) {
974 if (channel_subsys
->max_cssid
== 0) {
975 real_cssid
= channel_subsys
->default_cssid
;
979 if (!channel_subsys
->css
[real_cssid
]) {
983 if (!channel_subsys
->css
[real_cssid
]->chpids
[chpid
].in_use
) {
987 if (!channel_subsys
->css
[real_cssid
]->chpids
[chpid
].is_virtual
) {
989 "rchp unsupported for non-virtual chpid %x.%02x!\n",
994 /* We don't really use a channel path, so we're done here. */
995 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
,
996 channel_subsys
->max_cssid
> 0 ? 1 : 0, chpid
);
997 if (channel_subsys
->max_cssid
> 0) {
998 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
, 0, real_cssid
<< 8);
1003 bool css_schid_final(int m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1008 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
->default_cssid
: cssid
;
1009 if (real_cssid
> MAX_CSSID
|| ssid
> MAX_SSID
||
1010 !channel_subsys
->css
[real_cssid
] ||
1011 !channel_subsys
->css
[real_cssid
]->sch_set
[ssid
]) {
1014 set
= channel_subsys
->css
[real_cssid
]->sch_set
[ssid
];
1015 return schid
> find_last_bit(set
->schids_used
,
1016 (MAX_SCHID
+ 1) / sizeof(unsigned long));
1019 static int css_add_virtual_chpid(uint8_t cssid
, uint8_t chpid
, uint8_t type
)
1023 trace_css_chpid_add(cssid
, chpid
, type
);
1024 if (cssid
> MAX_CSSID
) {
1027 css
= channel_subsys
->css
[cssid
];
1031 if (css
->chpids
[chpid
].in_use
) {
1034 css
->chpids
[chpid
].in_use
= 1;
1035 css
->chpids
[chpid
].type
= type
;
1036 css
->chpids
[chpid
].is_virtual
= 1;
1038 css_generate_chp_crws(cssid
, chpid
);
1043 void css_sch_build_virtual_schib(SubchDev
*sch
, uint8_t chpid
, uint8_t type
)
1045 PMCW
*p
= &sch
->curr_status
.pmcw
;
1046 SCSW
*s
= &sch
->curr_status
.scsw
;
1048 CssImage
*css
= channel_subsys
->css
[sch
->cssid
];
1050 assert(css
!= NULL
);
1051 memset(p
, 0, sizeof(PMCW
));
1052 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
1053 p
->devno
= sch
->devno
;
1058 p
->chpid
[0] = chpid
;
1059 if (!css
->chpids
[chpid
].in_use
) {
1060 css_add_virtual_chpid(sch
->cssid
, chpid
, type
);
1063 memset(s
, 0, sizeof(SCSW
));
1064 sch
->curr_status
.mba
= 0;
1065 for (i
= 0; i
< ARRAY_SIZE(sch
->curr_status
.mda
); i
++) {
1066 sch
->curr_status
.mda
[i
] = 0;
1070 SubchDev
*css_find_subch(uint8_t m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1074 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
->default_cssid
: cssid
;
1076 if (!channel_subsys
->css
[real_cssid
]) {
1080 if (!channel_subsys
->css
[real_cssid
]->sch_set
[ssid
]) {
1084 return channel_subsys
->css
[real_cssid
]->sch_set
[ssid
]->sch
[schid
];
1087 bool css_subch_visible(SubchDev
*sch
)
1089 if (sch
->ssid
> channel_subsys
->max_ssid
) {
1093 if (sch
->cssid
!= channel_subsys
->default_cssid
) {
1094 return (channel_subsys
->max_cssid
> 0);
1100 bool css_present(uint8_t cssid
)
1102 return (channel_subsys
->css
[cssid
] != NULL
);
1105 bool css_devno_used(uint8_t cssid
, uint8_t ssid
, uint16_t devno
)
1107 if (!channel_subsys
->css
[cssid
]) {
1110 if (!channel_subsys
->css
[cssid
]->sch_set
[ssid
]) {
1114 return !!test_bit(devno
,
1115 channel_subsys
->css
[cssid
]->sch_set
[ssid
]->devnos_used
);
1118 void css_subch_assign(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
1119 uint16_t devno
, SubchDev
*sch
)
1124 trace_css_assign_subch(sch
? "assign" : "deassign", cssid
, ssid
, schid
,
1126 if (!channel_subsys
->css
[cssid
]) {
1128 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
1129 __func__
, cssid
, ssid
, schid
);
1132 css
= channel_subsys
->css
[cssid
];
1134 if (!css
->sch_set
[ssid
]) {
1135 css
->sch_set
[ssid
] = g_malloc0(sizeof(SubchSet
));
1137 s_set
= css
->sch_set
[ssid
];
1139 s_set
->sch
[schid
] = sch
;
1141 set_bit(schid
, s_set
->schids_used
);
1142 set_bit(devno
, s_set
->devnos_used
);
1144 clear_bit(schid
, s_set
->schids_used
);
1145 clear_bit(devno
, s_set
->devnos_used
);
1149 void css_queue_crw(uint8_t rsc
, uint8_t erc
, int chain
, uint16_t rsid
)
1151 CrwContainer
*crw_cont
;
1153 trace_css_crw(rsc
, erc
, rsid
, chain
? "(chained)" : "");
1154 /* TODO: Maybe use a static crw pool? */
1155 crw_cont
= g_try_malloc0(sizeof(CrwContainer
));
1157 channel_subsys
->crws_lost
= true;
1160 crw_cont
->crw
.flags
= (rsc
<< 8) | erc
;
1162 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_C
;
1164 crw_cont
->crw
.rsid
= rsid
;
1165 if (channel_subsys
->crws_lost
) {
1166 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_R
;
1167 channel_subsys
->crws_lost
= false;
1170 QTAILQ_INSERT_TAIL(&channel_subsys
->pending_crws
, crw_cont
, sibling
);
1172 if (channel_subsys
->do_crw_mchk
) {
1173 S390CPU
*cpu
= s390_cpu_addr2state(0);
1175 channel_subsys
->do_crw_mchk
= false;
1176 /* Inject crw pending machine check. */
1181 void css_generate_sch_crws(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
1182 int hotplugged
, int add
)
1184 uint8_t guest_cssid
;
1187 if (add
&& !hotplugged
) {
1190 if (channel_subsys
->max_cssid
== 0) {
1191 /* Default cssid shows up as 0. */
1192 guest_cssid
= (cssid
== channel_subsys
->default_cssid
) ? 0 : cssid
;
1194 /* Show real cssid to the guest. */
1195 guest_cssid
= cssid
;
1198 * Only notify for higher subchannel sets/channel subsystems if the
1199 * guest has enabled it.
1201 if ((ssid
> channel_subsys
->max_ssid
) ||
1202 (guest_cssid
> channel_subsys
->max_cssid
) ||
1203 ((channel_subsys
->max_cssid
== 0) &&
1204 (cssid
!= channel_subsys
->default_cssid
))) {
1207 chain_crw
= (channel_subsys
->max_ssid
> 0) ||
1208 (channel_subsys
->max_cssid
> 0);
1209 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, chain_crw
? 1 : 0, schid
);
1211 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, 0,
1212 (guest_cssid
<< 8) | (ssid
<< 4));
1216 void css_generate_chp_crws(uint8_t cssid
, uint8_t chpid
)
1221 int css_enable_mcsse(void)
1223 trace_css_enable_facility("mcsse");
1224 channel_subsys
->max_cssid
= MAX_CSSID
;
1228 int css_enable_mss(void)
1230 trace_css_enable_facility("mss");
1231 channel_subsys
->max_ssid
= MAX_SSID
;
1235 static void css_init(void)
1237 channel_subsys
= g_malloc0(sizeof(*channel_subsys
));
1238 QTAILQ_INIT(&channel_subsys
->pending_crws
);
1239 channel_subsys
->do_crw_mchk
= true;
1240 channel_subsys
->crws_lost
= false;
1241 channel_subsys
->chnmon_active
= false;
1243 machine_init(css_init
);
1245 void css_reset_sch(SubchDev
*sch
)
1247 PMCW
*p
= &sch
->curr_status
.pmcw
;
1250 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
1251 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
1252 PMCW_FLAGS_MASK_MP
| PMCW_FLAGS_MASK_TF
);
1253 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
1254 p
->devno
= sch
->devno
;
1262 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_XMWME
|
1263 PMCW_CHARS_MASK_CSENSE
);
1265 memset(&sch
->curr_status
.scsw
, 0, sizeof(sch
->curr_status
.scsw
));
1266 sch
->curr_status
.mba
= 0;
1268 sch
->channel_prog
= 0x0;
1269 sch
->last_cmd_valid
= false;
1271 sch
->thinint_active
= false;
1274 void css_reset(void)
1276 CrwContainer
*crw_cont
;
1278 /* Clean up monitoring. */
1279 channel_subsys
->chnmon_active
= false;
1280 channel_subsys
->chnmon_area
= 0;
1282 /* Clear pending CRWs. */
1283 while ((crw_cont
= QTAILQ_FIRST(&channel_subsys
->pending_crws
))) {
1284 QTAILQ_REMOVE(&channel_subsys
->pending_crws
, crw_cont
, sibling
);
1287 channel_subsys
->do_crw_mchk
= true;
1288 channel_subsys
->crws_lost
= false;
1290 /* Reset maximum ids. */
1291 channel_subsys
->max_cssid
= 0;
1292 channel_subsys
->max_ssid
= 0;