?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
[qemu/ar7.git] / hw / ide / core.c
blobe1dfe54df62589c5322e698f4e178f9cf0b4ba28
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/blockdev.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify(IDEState *s)
79 {
80 uint16_t *p;
81 unsigned int oldsize;
82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
83
84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
91 put_le16(p + 0, 0x0040);
92 put_le16(p + 1, s->cylinders);
93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
96 put_le16(p + 6, s->sectors);
97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
103 #if MAX_MULT_SECTORS > 1
104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
105 #endif
106 put_le16(p + 48, 1); /* dword I/O */
107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
114 oldsize = s->cylinders * s->heads * s->sectors;
115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
117 if (s->mult_sectors)
118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
123 put_le16(p + 64, 0x03); /* pio3-4 supported */
124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
169
170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
185 }
186
187 static void ide_atapi_identify(IDEState *s)
188 {
189 uint16_t *p;
190
191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
207 #ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
210 put_le16(p + 62, 7); /* single word dma0-2 supported */
211 put_le16(p + 63, 7); /* mdma0-2 supported */
212 #else
213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
216 #endif
217 put_le16(p + 64, 3); /* pio3-4 supported */
218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
222
223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
225
226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
233 #ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235 #endif
236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
238 }
239
240 static void ide_cfata_identify(IDEState *s)
241 {
242 uint16_t *p;
243 uint32_t cur_sec;
244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
260 put_le16(p + 22, 0x0004); /* ECC bytes */
261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
263 #if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265 #else
266 put_le16(p + 47, 0x0000);
267 #endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302 fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304 }
305
306 static void ide_set_signature(IDEState *s)
307 {
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
312 if (s->drive_kind == IDE_CD) {
313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322 }
323
324 typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
328 QEMUIOVector *qiov;
329 BlockDriverAIOCB *aiocb;
330 int i, j;
331 } TrimAIOCB;
332
333 static void trim_aio_cancel(BlockDriverAIOCB *acb)
334 {
335 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
336
337 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
338 iocb->j = iocb->qiov->niov - 1;
339 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
340
341 /* Tell ide_issue_trim_cb not to trigger the completion, too. */
342 qemu_bh_delete(iocb->bh);
343 iocb->bh = NULL;
344
345 if (iocb->aiocb) {
346 bdrv_aio_cancel(iocb->aiocb);
347 }
348 qemu_aio_release(iocb);
349 }
350
351 static const AIOCBInfo trim_aiocb_info = {
352 .aiocb_size = sizeof(TrimAIOCB),
353 .cancel = trim_aio_cancel,
354 };
355
356 static void ide_trim_bh_cb(void *opaque)
357 {
358 TrimAIOCB *iocb = opaque;
359
360 iocb->common.cb(iocb->common.opaque, iocb->ret);
361
362 qemu_bh_delete(iocb->bh);
363 iocb->bh = NULL;
364 qemu_aio_release(iocb);
365 }
366
367 static void ide_issue_trim_cb(void *opaque, int ret)
368 {
369 TrimAIOCB *iocb = opaque;
370 if (ret >= 0) {
371 while (iocb->j < iocb->qiov->niov) {
372 int j = iocb->j;
373 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
374 int i = iocb->i;
375 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
376
377 /* 6-byte LBA + 2-byte range per entry */
378 uint64_t entry = le64_to_cpu(buffer[i]);
379 uint64_t sector = entry & 0x0000ffffffffffffULL;
380 uint16_t count = entry >> 48;
381
382 if (count == 0) {
383 continue;
384 }
385
386 /* Got an entry! Submit and exit. */
387 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
388 ide_issue_trim_cb, opaque);
389 return;
390 }
391
392 iocb->j++;
393 iocb->i = -1;
394 }
395 } else {
396 iocb->ret = ret;
397 }
398
399 iocb->aiocb = NULL;
400 if (iocb->bh) {
401 qemu_bh_schedule(iocb->bh);
402 }
403 }
404
405 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
406 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
407 BlockDriverCompletionFunc *cb, void *opaque)
408 {
409 TrimAIOCB *iocb;
410
411 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
412 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
413 iocb->ret = 0;
414 iocb->qiov = qiov;
415 iocb->i = -1;
416 iocb->j = 0;
417 ide_issue_trim_cb(iocb, 0);
418 return &iocb->common;
419 }
420
421 static inline void ide_abort_command(IDEState *s)
422 {
423 s->status = READY_STAT | ERR_STAT;
424 s->error = ABRT_ERR;
425 }
426
427 /* prepare data transfer and tell what to do after */
428 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
429 EndTransferFunc *end_transfer_func)
430 {
431 s->end_transfer_func = end_transfer_func;
432 s->data_ptr = buf;
433 s->data_end = buf + size;
434 if (!(s->status & ERR_STAT)) {
435 s->status |= DRQ_STAT;
436 }
437 s->bus->dma->ops->start_transfer(s->bus->dma);
438 }
439
440 void ide_transfer_stop(IDEState *s)
441 {
442 s->end_transfer_func = ide_transfer_stop;
443 s->data_ptr = s->io_buffer;
444 s->data_end = s->io_buffer;
445 s->status &= ~DRQ_STAT;
446 }
447
448 int64_t ide_get_sector(IDEState *s)
449 {
450 int64_t sector_num;
451 if (s->select & 0x40) {
452 /* lba */
453 if (!s->lba48) {
454 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
455 (s->lcyl << 8) | s->sector;
456 } else {
457 sector_num = ((int64_t)s->hob_hcyl << 40) |
458 ((int64_t) s->hob_lcyl << 32) |
459 ((int64_t) s->hob_sector << 24) |
460 ((int64_t) s->hcyl << 16) |
461 ((int64_t) s->lcyl << 8) | s->sector;
462 }
463 } else {
464 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
465 (s->select & 0x0f) * s->sectors + (s->sector - 1);
466 }
467 return sector_num;
468 }
469
470 void ide_set_sector(IDEState *s, int64_t sector_num)
471 {
472 unsigned int cyl, r;
473 if (s->select & 0x40) {
474 if (!s->lba48) {
475 s->select = (s->select & 0xf0) | (sector_num >> 24);
476 s->hcyl = (sector_num >> 16);
477 s->lcyl = (sector_num >> 8);
478 s->sector = (sector_num);
479 } else {
480 s->sector = sector_num;
481 s->lcyl = sector_num >> 8;
482 s->hcyl = sector_num >> 16;
483 s->hob_sector = sector_num >> 24;
484 s->hob_lcyl = sector_num >> 32;
485 s->hob_hcyl = sector_num >> 40;
486 }
487 } else {
488 cyl = sector_num / (s->heads * s->sectors);
489 r = sector_num % (s->heads * s->sectors);
490 s->hcyl = cyl >> 8;
491 s->lcyl = cyl;
492 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
493 s->sector = (r % s->sectors) + 1;
494 }
495 }
496
497 static void ide_rw_error(IDEState *s) {
498 ide_abort_command(s);
499 ide_set_irq(s->bus);
500 }
501
502 static void ide_sector_read_cb(void *opaque, int ret)
503 {
504 IDEState *s = opaque;
505 int n;
506
507 s->pio_aiocb = NULL;
508 s->status &= ~BUSY_STAT;
509
510 bdrv_acct_done(s->bs, &s->acct);
511 if (ret != 0) {
512 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
513 BM_STATUS_RETRY_READ)) {
514 return;
515 }
516 }
517
518 n = s->nsector;
519 if (n > s->req_nb_sectors) {
520 n = s->req_nb_sectors;
521 }
522
523 /* Allow the guest to read the io_buffer */
524 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
525
526 ide_set_irq(s->bus);
527
528 ide_set_sector(s, ide_get_sector(s) + n);
529 s->nsector -= n;
530 }
531
532 void ide_sector_read(IDEState *s)
533 {
534 int64_t sector_num;
535 int n;
536
537 s->status = READY_STAT | SEEK_STAT;
538 s->error = 0; /* not needed by IDE spec, but needed by Windows */
539 sector_num = ide_get_sector(s);
540 n = s->nsector;
541
542 if (n == 0) {
543 ide_transfer_stop(s);
544 return;
545 }
546
547 s->status |= BUSY_STAT;
548
549 if (n > s->req_nb_sectors) {
550 n = s->req_nb_sectors;
551 }
552
553 #if defined(DEBUG_IDE)
554 printf("sector=%" PRId64 "\n", sector_num);
555 #endif
556
557 s->iov.iov_base = s->io_buffer;
558 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
559 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
560
561 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
562 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
563 ide_sector_read_cb, s);
564 }
565
566 static void dma_buf_commit(IDEState *s)
567 {
568 qemu_sglist_destroy(&s->sg);
569 }
570
571 static void ide_async_cmd_done(IDEState *s)
572 {
573 if (s->bus->dma->ops->async_cmd_done) {
574 s->bus->dma->ops->async_cmd_done(s->bus->dma);
575 }
576 }
577
578 void ide_set_inactive(IDEState *s)
579 {
580 s->bus->dma->aiocb = NULL;
581 s->bus->dma->ops->set_inactive(s->bus->dma);
582 ide_async_cmd_done(s);
583 }
584
585 void ide_dma_error(IDEState *s)
586 {
587 ide_transfer_stop(s);
588 s->error = ABRT_ERR;
589 s->status = READY_STAT | ERR_STAT;
590 ide_set_inactive(s);
591 ide_set_irq(s->bus);
592 }
593
594 static int ide_handle_rw_error(IDEState *s, int error, int op)
595 {
596 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
597 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
598
599 if (action == BDRV_ACTION_STOP) {
600 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
601 s->bus->error_status = op;
602 } else if (action == BDRV_ACTION_REPORT) {
603 if (op & BM_STATUS_DMA_RETRY) {
604 dma_buf_commit(s);
605 ide_dma_error(s);
606 } else {
607 ide_rw_error(s);
608 }
609 }
610 bdrv_error_action(s->bs, action, is_read, error);
611 return action != BDRV_ACTION_IGNORE;
612 }
613
614 void ide_dma_cb(void *opaque, int ret)
615 {
616 IDEState *s = opaque;
617 int n;
618 int64_t sector_num;
619 bool stay_active = false;
620
621 if (ret < 0) {
622 int op = BM_STATUS_DMA_RETRY;
623
624 if (s->dma_cmd == IDE_DMA_READ)
625 op |= BM_STATUS_RETRY_READ;
626 else if (s->dma_cmd == IDE_DMA_TRIM)
627 op |= BM_STATUS_RETRY_TRIM;
628
629 if (ide_handle_rw_error(s, -ret, op)) {
630 return;
631 }
632 }
633
634 n = s->io_buffer_size >> 9;
635 if (n > s->nsector) {
636 /* The PRDs were longer than needed for this request. Shorten them so
637 * we don't get a negative remainder. The Active bit must remain set
638 * after the request completes. */
639 n = s->nsector;
640 stay_active = true;
641 }
642
643 sector_num = ide_get_sector(s);
644 if (n > 0) {
645 dma_buf_commit(s);
646 sector_num += n;
647 ide_set_sector(s, sector_num);
648 s->nsector -= n;
649 }
650
651 /* end of transfer ? */
652 if (s->nsector == 0) {
653 s->status = READY_STAT | SEEK_STAT;
654 ide_set_irq(s->bus);
655 goto eot;
656 }
657
658 /* launch next transfer */
659 n = s->nsector;
660 s->io_buffer_index = 0;
661 s->io_buffer_size = n * 512;
662 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
663 /* The PRDs were too short. Reset the Active bit, but don't raise an
664 * interrupt. */
665 s->status = READY_STAT | SEEK_STAT;
666 goto eot;
667 }
668
669 #ifdef DEBUG_AIO
670 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
671 sector_num, n, s->dma_cmd);
672 #endif
673
674 switch (s->dma_cmd) {
675 case IDE_DMA_READ:
676 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
677 ide_dma_cb, s);
678 break;
679 case IDE_DMA_WRITE:
680 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
681 ide_dma_cb, s);
682 break;
683 case IDE_DMA_TRIM:
684 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
685 ide_issue_trim, ide_dma_cb, s,
686 DMA_DIRECTION_TO_DEVICE);
687 break;
688 }
689 return;
690
691 eot:
692 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
693 bdrv_acct_done(s->bs, &s->acct);
694 }
695 ide_set_inactive(s);
696 if (stay_active) {
697 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
698 }
699 }
700
701 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
702 {
703 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
704 s->io_buffer_index = 0;
705 s->io_buffer_size = 0;
706 s->dma_cmd = dma_cmd;
707
708 switch (dma_cmd) {
709 case IDE_DMA_READ:
710 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
711 BDRV_ACCT_READ);
712 break;
713 case IDE_DMA_WRITE:
714 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
715 BDRV_ACCT_WRITE);
716 break;
717 default:
718 break;
719 }
720
721 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
722 }
723
724 static void ide_sector_write_timer_cb(void *opaque)
725 {
726 IDEState *s = opaque;
727 ide_set_irq(s->bus);
728 }
729
730 static void ide_sector_write_cb(void *opaque, int ret)
731 {
732 IDEState *s = opaque;
733 int n;
734
735 bdrv_acct_done(s->bs, &s->acct);
736
737 s->pio_aiocb = NULL;
738 s->status &= ~BUSY_STAT;
739
740 if (ret != 0) {
741 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
742 return;
743 }
744 }
745
746 n = s->nsector;
747 if (n > s->req_nb_sectors) {
748 n = s->req_nb_sectors;
749 }
750 s->nsector -= n;
751 if (s->nsector == 0) {
752 /* no more sectors to write */
753 ide_transfer_stop(s);
754 } else {
755 int n1 = s->nsector;
756 if (n1 > s->req_nb_sectors) {
757 n1 = s->req_nb_sectors;
758 }
759 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
760 ide_sector_write);
761 }
762 ide_set_sector(s, ide_get_sector(s) + n);
763
764 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
765 /* It seems there is a bug in the Windows 2000 installer HDD
766 IDE driver which fills the disk with empty logs when the
767 IDE write IRQ comes too early. This hack tries to correct
768 that at the expense of slower write performances. Use this
769 option _only_ to install Windows 2000. You must disable it
770 for normal use. */
771 timer_mod(s->sector_write_timer,
772 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
773 } else {
774 ide_set_irq(s->bus);
775 }
776 }
777
778 void ide_sector_write(IDEState *s)
779 {
780 int64_t sector_num;
781 int n;
782
783 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
784 sector_num = ide_get_sector(s);
785 #if defined(DEBUG_IDE)
786 printf("sector=%" PRId64 "\n", sector_num);
787 #endif
788 n = s->nsector;
789 if (n > s->req_nb_sectors) {
790 n = s->req_nb_sectors;
791 }
792
793 s->iov.iov_base = s->io_buffer;
794 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
795 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
796
797 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
798 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
799 ide_sector_write_cb, s);
800 }
801
802 static void ide_flush_cb(void *opaque, int ret)
803 {
804 IDEState *s = opaque;
805
806 if (ret < 0) {
807 /* XXX: What sector number to set here? */
808 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
809 return;
810 }
811 }
812
813 bdrv_acct_done(s->bs, &s->acct);
814 s->status = READY_STAT | SEEK_STAT;
815 ide_async_cmd_done(s);
816 ide_set_irq(s->bus);
817 }
818
819 void ide_flush_cache(IDEState *s)
820 {
821 if (s->bs == NULL) {
822 ide_flush_cb(s, 0);
823 return;
824 }
825
826 s->status |= BUSY_STAT;
827 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
828 bdrv_aio_flush(s->bs, ide_flush_cb, s);
829 }
830
831 static void ide_cfata_metadata_inquiry(IDEState *s)
832 {
833 uint16_t *p;
834 uint32_t spd;
835
836 p = (uint16_t *) s->io_buffer;
837 memset(p, 0, 0x200);
838 spd = ((s->mdata_size - 1) >> 9) + 1;
839
840 put_le16(p + 0, 0x0001); /* Data format revision */
841 put_le16(p + 1, 0x0000); /* Media property: silicon */
842 put_le16(p + 2, s->media_changed); /* Media status */
843 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
844 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
845 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
846 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
847 }
848
849 static void ide_cfata_metadata_read(IDEState *s)
850 {
851 uint16_t *p;
852
853 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
854 s->status = ERR_STAT;
855 s->error = ABRT_ERR;
856 return;
857 }
858
859 p = (uint16_t *) s->io_buffer;
860 memset(p, 0, 0x200);
861
862 put_le16(p + 0, s->media_changed); /* Media status */
863 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
864 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
865 s->nsector << 9), 0x200 - 2));
866 }
867
868 static void ide_cfata_metadata_write(IDEState *s)
869 {
870 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
871 s->status = ERR_STAT;
872 s->error = ABRT_ERR;
873 return;
874 }
875
876 s->media_changed = 0;
877
878 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
879 s->io_buffer + 2,
880 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
881 s->nsector << 9), 0x200 - 2));
882 }
883
884 /* called when the inserted state of the media has changed */
885 static void ide_cd_change_cb(void *opaque, bool load)
886 {
887 IDEState *s = opaque;
888 uint64_t nb_sectors;
889
890 s->tray_open = !load;
891 bdrv_get_geometry(s->bs, &nb_sectors);
892 s->nb_sectors = nb_sectors;
893
894 /*
895 * First indicate to the guest that a CD has been removed. That's
896 * done on the next command the guest sends us.
897 *
898 * Then we set UNIT_ATTENTION, by which the guest will
899 * detect a new CD in the drive. See ide_atapi_cmd() for details.
900 */
901 s->cdrom_changed = 1;
902 s->events.new_media = true;
903 s->events.eject_request = false;
904 ide_set_irq(s->bus);
905 }
906
907 static void ide_cd_eject_request_cb(void *opaque, bool force)
908 {
909 IDEState *s = opaque;
910
911 s->events.eject_request = true;
912 if (force) {
913 s->tray_locked = false;
914 }
915 ide_set_irq(s->bus);
916 }
917
918 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
919 {
920 s->lba48 = lba48;
921
922 /* handle the 'magic' 0 nsector count conversion here. to avoid
923 * fiddling with the rest of the read logic, we just store the
924 * full sector count in ->nsector and ignore ->hob_nsector from now
925 */
926 if (!s->lba48) {
927 if (!s->nsector)
928 s->nsector = 256;
929 } else {
930 if (!s->nsector && !s->hob_nsector)
931 s->nsector = 65536;
932 else {
933 int lo = s->nsector;
934 int hi = s->hob_nsector;
935
936 s->nsector = (hi << 8) | lo;
937 }
938 }
939 }
940
941 static void ide_clear_hob(IDEBus *bus)
942 {
943 /* any write clears HOB high bit of device control register */
944 bus->ifs[0].select &= ~(1 << 7);
945 bus->ifs[1].select &= ~(1 << 7);
946 }
947
948 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
949 {
950 IDEBus *bus = opaque;
951
952 #ifdef DEBUG_IDE
953 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
954 #endif
955
956 addr &= 7;
957
958 /* ignore writes to command block while busy with previous command */
959 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
960 return;
961
962 switch(addr) {
963 case 0:
964 break;
965 case 1:
966 ide_clear_hob(bus);
967 /* NOTE: data is written to the two drives */
968 bus->ifs[0].hob_feature = bus->ifs[0].feature;
969 bus->ifs[1].hob_feature = bus->ifs[1].feature;
970 bus->ifs[0].feature = val;
971 bus->ifs[1].feature = val;
972 break;
973 case 2:
974 ide_clear_hob(bus);
975 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
976 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
977 bus->ifs[0].nsector = val;
978 bus->ifs[1].nsector = val;
979 break;
980 case 3:
981 ide_clear_hob(bus);
982 bus->ifs[0].hob_sector = bus->ifs[0].sector;
983 bus->ifs[1].hob_sector = bus->ifs[1].sector;
984 bus->ifs[0].sector = val;
985 bus->ifs[1].sector = val;
986 break;
987 case 4:
988 ide_clear_hob(bus);
989 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
990 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
991 bus->ifs[0].lcyl = val;
992 bus->ifs[1].lcyl = val;
993 break;
994 case 5:
995 ide_clear_hob(bus);
996 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
997 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
998 bus->ifs[0].hcyl = val;
999 bus->ifs[1].hcyl = val;
1000 break;
1001 case 6:
1002 /* FIXME: HOB readback uses bit 7 */
1003 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1004 bus->ifs[1].select = (val | 0x10) | 0xa0;
1005 /* select drive */
1006 bus->unit = (val >> 4) & 1;
1007 break;
1008 default:
1009 case 7:
1010 /* command */
1011 ide_exec_cmd(bus, val);
1012 break;
1013 }
1014 }
1015
1016 static bool cmd_nop(IDEState *s, uint8_t cmd)
1017 {
1018 return true;
1019 }
1020
1021 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1022 {
1023 switch (s->feature) {
1024 case DSM_TRIM:
1025 if (s->bs) {
1026 ide_sector_start_dma(s, IDE_DMA_TRIM);
1027 return false;
1028 }
1029 break;
1030 }
1031
1032 ide_abort_command(s);
1033 return true;
1034 }
1035
1036 static bool cmd_identify(IDEState *s, uint8_t cmd)
1037 {
1038 if (s->bs && s->drive_kind != IDE_CD) {
1039 if (s->drive_kind != IDE_CFATA) {
1040 ide_identify(s);
1041 } else {
1042 ide_cfata_identify(s);
1043 }
1044 s->status = READY_STAT | SEEK_STAT;
1045 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1046 ide_set_irq(s->bus);
1047 return false;
1048 } else {
1049 if (s->drive_kind == IDE_CD) {
1050 ide_set_signature(s);
1051 }
1052 ide_abort_command(s);
1053 }
1054
1055 return true;
1056 }
1057
1058 static bool cmd_verify(IDEState *s, uint8_t cmd)
1059 {
1060 bool lba48 = (cmd == WIN_VERIFY_EXT);
1061
1062 /* do sector number check ? */
1063 ide_cmd_lba48_transform(s, lba48);
1064
1065 return true;
1066 }
1067
1068 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1069 {
1070 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1071 /* Disable Read and Write Multiple */
1072 s->mult_sectors = 0;
1073 } else if ((s->nsector & 0xff) != 0 &&
1074 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1075 (s->nsector & (s->nsector - 1)) != 0)) {
1076 ide_abort_command(s);
1077 } else {
1078 s->mult_sectors = s->nsector & 0xff;
1079 }
1080
1081 return true;
1082 }
1083
1084 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1085 {
1086 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1087
1088 if (!s->bs || !s->mult_sectors) {
1089 ide_abort_command(s);
1090 return true;
1091 }
1092
1093 ide_cmd_lba48_transform(s, lba48);
1094 s->req_nb_sectors = s->mult_sectors;
1095 ide_sector_read(s);
1096 return false;
1097 }
1098
1099 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1100 {
1101 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1102 int n;
1103
1104 if (!s->bs || !s->mult_sectors) {
1105 ide_abort_command(s);
1106 return true;
1107 }
1108
1109 ide_cmd_lba48_transform(s, lba48);
1110
1111 s->req_nb_sectors = s->mult_sectors;
1112 n = MIN(s->nsector, s->req_nb_sectors);
1113
1114 s->status = SEEK_STAT | READY_STAT;
1115 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1116
1117 s->media_changed = 1;
1118
1119 return false;
1120 }
1121
1122 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1123 {
1124 bool lba48 = (cmd == WIN_READ_EXT);
1125
1126 if (s->drive_kind == IDE_CD) {
1127 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1128 ide_abort_command(s);
1129 return true;
1130 }
1131
1132 if (!s->bs) {
1133 ide_abort_command(s);
1134 return true;
1135 }
1136
1137 ide_cmd_lba48_transform(s, lba48);
1138 s->req_nb_sectors = 1;
1139 ide_sector_read(s);
1140
1141 return false;
1142 }
1143
1144 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1145 {
1146 bool lba48 = (cmd == WIN_WRITE_EXT);
1147
1148 if (!s->bs) {
1149 ide_abort_command(s);
1150 return true;
1151 }
1152
1153 ide_cmd_lba48_transform(s, lba48);
1154
1155 s->req_nb_sectors = 1;
1156 s->status = SEEK_STAT | READY_STAT;
1157 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1158
1159 s->media_changed = 1;
1160
1161 return false;
1162 }
1163
1164 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1165 {
1166 bool lba48 = (cmd == WIN_READDMA_EXT);
1167
1168 if (!s->bs) {
1169 ide_abort_command(s);
1170 return true;
1171 }
1172
1173 ide_cmd_lba48_transform(s, lba48);
1174 ide_sector_start_dma(s, IDE_DMA_READ);
1175
1176 return false;
1177 }
1178
1179 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1180 {
1181 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1182
1183 if (!s->bs) {
1184 ide_abort_command(s);
1185 return true;
1186 }
1187
1188 ide_cmd_lba48_transform(s, lba48);
1189 ide_sector_start_dma(s, IDE_DMA_WRITE);
1190
1191 s->media_changed = 1;
1192
1193 return false;
1194 }
1195
1196 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1197 {
1198 ide_flush_cache(s);
1199 return false;
1200 }
1201
1202 static bool cmd_seek(IDEState *s, uint8_t cmd)
1203 {
1204 /* XXX: Check that seek is within bounds */
1205 return true;
1206 }
1207
1208 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1209 {
1210 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1211
1212 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1213 if (s->nb_sectors == 0) {
1214 ide_abort_command(s);
1215 return true;
1216 }
1217
1218 ide_cmd_lba48_transform(s, lba48);
1219 ide_set_sector(s, s->nb_sectors - 1);
1220
1221 return true;
1222 }
1223
1224 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1225 {
1226 s->nsector = 0xff; /* device active or idle */
1227 return true;
1228 }
1229
1230 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1231 {
1232 uint16_t *identify_data;
1233
1234 if (!s->bs) {
1235 ide_abort_command(s);
1236 return true;
1237 }
1238
1239 /* XXX: valid for CDROM ? */
1240 switch (s->feature) {
1241 case 0x02: /* write cache enable */
1242 bdrv_set_enable_write_cache(s->bs, true);
1243 identify_data = (uint16_t *)s->identify_data;
1244 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1245 return true;
1246 case 0x82: /* write cache disable */
1247 bdrv_set_enable_write_cache(s->bs, false);
1248 identify_data = (uint16_t *)s->identify_data;
1249 put_le16(identify_data + 85, (1 << 14) | 1);
1250 ide_flush_cache(s);
1251 return false;
1252 case 0xcc: /* reverting to power-on defaults enable */
1253 case 0x66: /* reverting to power-on defaults disable */
1254 case 0xaa: /* read look-ahead enable */
1255 case 0x55: /* read look-ahead disable */
1256 case 0x05: /* set advanced power management mode */
1257 case 0x85: /* disable advanced power management mode */
1258 case 0x69: /* NOP */
1259 case 0x67: /* NOP */
1260 case 0x96: /* NOP */
1261 case 0x9a: /* NOP */
1262 case 0x42: /* enable Automatic Acoustic Mode */
1263 case 0xc2: /* disable Automatic Acoustic Mode */
1264 return true;
1265 case 0x03: /* set transfer mode */
1266 {
1267 uint8_t val = s->nsector & 0x07;
1268 identify_data = (uint16_t *)s->identify_data;
1269
1270 switch (s->nsector >> 3) {
1271 case 0x00: /* pio default */
1272 case 0x01: /* pio mode */
1273 put_le16(identify_data + 62, 0x07);
1274 put_le16(identify_data + 63, 0x07);
1275 put_le16(identify_data + 88, 0x3f);
1276 break;
1277 case 0x02: /* sigle word dma mode*/
1278 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1279 put_le16(identify_data + 63, 0x07);
1280 put_le16(identify_data + 88, 0x3f);
1281 break;
1282 case 0x04: /* mdma mode */
1283 put_le16(identify_data + 62, 0x07);
1284 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1285 put_le16(identify_data + 88, 0x3f);
1286 break;
1287 case 0x08: /* udma mode */
1288 put_le16(identify_data + 62, 0x07);
1289 put_le16(identify_data + 63, 0x07);
1290 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1291 break;
1292 default:
1293 goto abort_cmd;
1294 }
1295 return true;
1296 }
1297 }
1298
1299 abort_cmd:
1300 ide_abort_command(s);
1301 return true;
1302 }
1303
1304
1305 /*** ATAPI commands ***/
1306
1307 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1308 {
1309 ide_atapi_identify(s);
1310 s->status = READY_STAT | SEEK_STAT;
1311 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1312 ide_set_irq(s->bus);
1313 return false;
1314 }
1315
1316 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1317 {
1318 ide_set_signature(s);
1319
1320 if (s->drive_kind == IDE_CD) {
1321 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1322 * devices to return a clear status register
1323 * with READY_STAT *not* set. */
1324 s->error = 0x01;
1325 } else {
1326 s->status = READY_STAT | SEEK_STAT;
1327 /* The bits of the error register are not as usual for this command!
1328 * They are part of the regular output (this is why ERR_STAT isn't set)
1329 * Device 0 passed, Device 1 passed or not present. */
1330 s->error = 0x01;
1331 ide_set_irq(s->bus);
1332 }
1333
1334 return false;
1335 }
1336
1337 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1338 {
1339 ide_set_signature(s);
1340 s->status = 0x00; /* NOTE: READY is _not_ set */
1341 s->error = 0x01;
1342
1343 return false;
1344 }
1345
1346 static bool cmd_packet(IDEState *s, uint8_t cmd)
1347 {
1348 /* overlapping commands not supported */
1349 if (s->feature & 0x02) {
1350 ide_abort_command(s);
1351 return true;
1352 }
1353
1354 s->status = READY_STAT | SEEK_STAT;
1355 s->atapi_dma = s->feature & 1;
1356 s->nsector = 1;
1357 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1358 ide_atapi_cmd);
1359 return false;
1360 }
1361
1362
1363 /*** CF-ATA commands ***/
1364
1365 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1366 {
1367 s->error = 0x09; /* miscellaneous error */
1368 s->status = READY_STAT | SEEK_STAT;
1369 ide_set_irq(s->bus);
1370
1371 return false;
1372 }
1373
1374 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1375 {
1376 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1377 * required for Windows 8 to work with AHCI */
1378
1379 if (cmd == CFA_WEAR_LEVEL) {
1380 s->nsector = 0;
1381 }
1382
1383 if (cmd == CFA_ERASE_SECTORS) {
1384 s->media_changed = 1;
1385 }
1386
1387 return true;
1388 }
1389
1390 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1391 {
1392 s->status = READY_STAT | SEEK_STAT;
1393
1394 memset(s->io_buffer, 0, 0x200);
1395 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1396 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1397 s->io_buffer[0x02] = s->select; /* Head */
1398 s->io_buffer[0x03] = s->sector; /* Sector */
1399 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1400 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1401 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1402 s->io_buffer[0x13] = 0x00; /* Erase flag */
1403 s->io_buffer[0x18] = 0x00; /* Hot count */
1404 s->io_buffer[0x19] = 0x00; /* Hot count */
1405 s->io_buffer[0x1a] = 0x01; /* Hot count */
1406
1407 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1408 ide_set_irq(s->bus);
1409
1410 return false;
1411 }
1412
1413 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1414 {
1415 switch (s->feature) {
1416 case 0x02: /* Inquiry Metadata Storage */
1417 ide_cfata_metadata_inquiry(s);
1418 break;
1419 case 0x03: /* Read Metadata Storage */
1420 ide_cfata_metadata_read(s);
1421 break;
1422 case 0x04: /* Write Metadata Storage */
1423 ide_cfata_metadata_write(s);
1424 break;
1425 default:
1426 ide_abort_command(s);
1427 return true;
1428 }
1429
1430 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1431 s->status = 0x00; /* NOTE: READY is _not_ set */
1432 ide_set_irq(s->bus);
1433
1434 return false;
1435 }
1436
1437 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1438 {
1439 switch (s->feature) {
1440 case 0x01: /* sense temperature in device */
1441 s->nsector = 0x50; /* +20 C */
1442 break;
1443 default:
1444 ide_abort_command(s);
1445 return true;
1446 }
1447
1448 return true;
1449 }
1450
1451
1452 /*** SMART commands ***/
1453
1454 static bool cmd_smart(IDEState *s, uint8_t cmd)
1455 {
1456 int n;
1457
1458 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1459 goto abort_cmd;
1460 }
1461
1462 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1463 goto abort_cmd;
1464 }
1465
1466 switch (s->feature) {
1467 case SMART_DISABLE:
1468 s->smart_enabled = 0;
1469 return true;
1470
1471 case SMART_ENABLE:
1472 s->smart_enabled = 1;
1473 return true;
1474
1475 case SMART_ATTR_AUTOSAVE:
1476 switch (s->sector) {
1477 case 0x00:
1478 s->smart_autosave = 0;
1479 break;
1480 case 0xf1:
1481 s->smart_autosave = 1;
1482 break;
1483 default:
1484 goto abort_cmd;
1485 }
1486 return true;
1487
1488 case SMART_STATUS:
1489 if (!s->smart_errors) {
1490 s->hcyl = 0xc2;
1491 s->lcyl = 0x4f;
1492 } else {
1493 s->hcyl = 0x2c;
1494 s->lcyl = 0xf4;
1495 }
1496 return true;
1497
1498 case SMART_READ_THRESH:
1499 memset(s->io_buffer, 0, 0x200);
1500 s->io_buffer[0] = 0x01; /* smart struct version */
1501
1502 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1503 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1504 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1505 }
1506
1507 /* checksum */
1508 for (n = 0; n < 511; n++) {
1509 s->io_buffer[511] += s->io_buffer[n];
1510 }
1511 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1512
1513 s->status = READY_STAT | SEEK_STAT;
1514 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1515 ide_set_irq(s->bus);
1516 return false;
1517
1518 case SMART_READ_DATA:
1519 memset(s->io_buffer, 0, 0x200);
1520 s->io_buffer[0] = 0x01; /* smart struct version */
1521
1522 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1523 int i;
1524 for (i = 0; i < 11; i++) {
1525 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1526 }
1527 }
1528
1529 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1530 if (s->smart_selftest_count == 0) {
1531 s->io_buffer[363] = 0;
1532 } else {
1533 s->io_buffer[363] =
1534 s->smart_selftest_data[3 +
1535 (s->smart_selftest_count - 1) *
1536 24];
1537 }
1538 s->io_buffer[364] = 0x20;
1539 s->io_buffer[365] = 0x01;
1540 /* offline data collection capacity: execute + self-test*/
1541 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1542 s->io_buffer[368] = 0x03; /* smart capability (1) */
1543 s->io_buffer[369] = 0x00; /* smart capability (2) */
1544 s->io_buffer[370] = 0x01; /* error logging supported */
1545 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1546 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1547 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1548
1549 for (n = 0; n < 511; n++) {
1550 s->io_buffer[511] += s->io_buffer[n];
1551 }
1552 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1553
1554 s->status = READY_STAT | SEEK_STAT;
1555 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1556 ide_set_irq(s->bus);
1557 return false;
1558
1559 case SMART_READ_LOG:
1560 switch (s->sector) {
1561 case 0x01: /* summary smart error log */
1562 memset(s->io_buffer, 0, 0x200);
1563 s->io_buffer[0] = 0x01;
1564 s->io_buffer[1] = 0x00; /* no error entries */
1565 s->io_buffer[452] = s->smart_errors & 0xff;
1566 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1567
1568 for (n = 0; n < 511; n++) {
1569 s->io_buffer[511] += s->io_buffer[n];
1570 }
1571 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1572 break;
1573 case 0x06: /* smart self test log */
1574 memset(s->io_buffer, 0, 0x200);
1575 s->io_buffer[0] = 0x01;
1576 if (s->smart_selftest_count == 0) {
1577 s->io_buffer[508] = 0;
1578 } else {
1579 s->io_buffer[508] = s->smart_selftest_count;
1580 for (n = 2; n < 506; n++) {
1581 s->io_buffer[n] = s->smart_selftest_data[n];
1582 }
1583 }
1584
1585 for (n = 0; n < 511; n++) {
1586 s->io_buffer[511] += s->io_buffer[n];
1587 }
1588 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1589 break;
1590 default:
1591 goto abort_cmd;
1592 }
1593 s->status = READY_STAT | SEEK_STAT;
1594 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1595 ide_set_irq(s->bus);
1596 return false;
1597
1598 case SMART_EXECUTE_OFFLINE:
1599 switch (s->sector) {
1600 case 0: /* off-line routine */
1601 case 1: /* short self test */
1602 case 2: /* extended self test */
1603 s->smart_selftest_count++;
1604 if (s->smart_selftest_count > 21) {
1605 s->smart_selftest_count = 0;
1606 }
1607 n = 2 + (s->smart_selftest_count - 1) * 24;
1608 s->smart_selftest_data[n] = s->sector;
1609 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1610 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1611 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1612 break;
1613 default:
1614 goto abort_cmd;
1615 }
1616 return true;
1617 }
1618
1619 abort_cmd:
1620 ide_abort_command(s);
1621 return true;
1622 }
1623
1624 #define HD_OK (1u << IDE_HD)
1625 #define CD_OK (1u << IDE_CD)
1626 #define CFA_OK (1u << IDE_CFATA)
1627 #define HD_CFA_OK (HD_OK | CFA_OK)
1628 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1629
1630 /* Set the Disk Seek Completed status bit during completion */
1631 #define SET_DSC (1u << 8)
1632
1633 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1634 static const struct {
1635 /* Returns true if the completion code should be run */
1636 bool (*handler)(IDEState *s, uint8_t cmd);
1637 int flags;
1638 } ide_cmd_table[0x100] = {
1639 /* NOP not implemented, mandatory for CD */
1640 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1641 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1642 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1643 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1644 [WIN_READ] = { cmd_read_pio, ALL_OK },
1645 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1646 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1647 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1648 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1649 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1650 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1651 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1652 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1653 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1654 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1655 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1656 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1657 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1658 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1659 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1660 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1661 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1662 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1663 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1664 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1665 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1666 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1667 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1668 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1669 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1670 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1671 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1672 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1673 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1674 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1675 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1676 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1677 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1678 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1679 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1680 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1681 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1682 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1683 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1684 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1685 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1686 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1687 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1688 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1689 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1690 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1691 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1692 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1693 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1694 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1695 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
1696 };
1697
1698 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1699 {
1700 return cmd < ARRAY_SIZE(ide_cmd_table)
1701 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1702 }
1703
1704 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1705 {
1706 IDEState *s;
1707 bool complete;
1708
1709 #if defined(DEBUG_IDE)
1710 printf("ide: CMD=%02x\n", val);
1711 #endif
1712 s = idebus_active_if(bus);
1713 /* ignore commands to non existent slave */
1714 if (s != bus->ifs && !s->bs)
1715 return;
1716
1717 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1718 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1719 return;
1720
1721 if (!ide_cmd_permitted(s, val)) {
1722 ide_abort_command(s);
1723 ide_set_irq(s->bus);
1724 return;
1725 }
1726
1727 s->status = READY_STAT | BUSY_STAT;
1728 s->error = 0;
1729
1730 complete = ide_cmd_table[val].handler(s, val);
1731 if (complete) {
1732 s->status &= ~BUSY_STAT;
1733 assert(!!s->error == !!(s->status & ERR_STAT));
1734
1735 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1736 s->status |= SEEK_STAT;
1737 }
1738
1739 ide_set_irq(s->bus);
1740 }
1741 }
1742
1743 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1744 {
1745 IDEBus *bus = opaque;
1746 IDEState *s = idebus_active_if(bus);
1747 uint32_t addr;
1748 int ret, hob;
1749
1750 addr = addr1 & 7;
1751 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1752 //hob = s->select & (1 << 7);
1753 hob = 0;
1754 switch(addr) {
1755 case 0:
1756 ret = 0xff;
1757 break;
1758 case 1:
1759 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1760 (s != bus->ifs && !s->bs))
1761 ret = 0;
1762 else if (!hob)
1763 ret = s->error;
1764 else
1765 ret = s->hob_feature;
1766 break;
1767 case 2:
1768 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1769 ret = 0;
1770 else if (!hob)
1771 ret = s->nsector & 0xff;
1772 else
1773 ret = s->hob_nsector;
1774 break;
1775 case 3:
1776 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1777 ret = 0;
1778 else if (!hob)
1779 ret = s->sector;
1780 else
1781 ret = s->hob_sector;
1782 break;
1783 case 4:
1784 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1785 ret = 0;
1786 else if (!hob)
1787 ret = s->lcyl;
1788 else
1789 ret = s->hob_lcyl;
1790 break;
1791 case 5:
1792 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1793 ret = 0;
1794 else if (!hob)
1795 ret = s->hcyl;
1796 else
1797 ret = s->hob_hcyl;
1798 break;
1799 case 6:
1800 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1801 ret = 0;
1802 else
1803 ret = s->select;
1804 break;
1805 default:
1806 case 7:
1807 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1808 (s != bus->ifs && !s->bs))
1809 ret = 0;
1810 else
1811 ret = s->status;
1812 qemu_irq_lower(bus->irq);
1813 break;
1814 }
1815 #ifdef DEBUG_IDE
1816 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1817 #endif
1818 return ret;
1819 }
1820
1821 uint32_t ide_status_read(void *opaque, uint32_t addr)
1822 {
1823 IDEBus *bus = opaque;
1824 IDEState *s = idebus_active_if(bus);
1825 int ret;
1826
1827 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1828 (s != bus->ifs && !s->bs))
1829 ret = 0;
1830 else
1831 ret = s->status;
1832 #ifdef DEBUG_IDE
1833 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1834 #endif
1835 return ret;
1836 }
1837
1838 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1839 {
1840 IDEBus *bus = opaque;
1841 IDEState *s;
1842 int i;
1843
1844 #ifdef DEBUG_IDE
1845 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1846 #endif
1847 /* common for both drives */
1848 if (!(bus->cmd & IDE_CMD_RESET) &&
1849 (val & IDE_CMD_RESET)) {
1850 /* reset low to high */
1851 for(i = 0;i < 2; i++) {
1852 s = &bus->ifs[i];
1853 s->status = BUSY_STAT | SEEK_STAT;
1854 s->error = 0x01;
1855 }
1856 } else if ((bus->cmd & IDE_CMD_RESET) &&
1857 !(val & IDE_CMD_RESET)) {
1858 /* high to low */
1859 for(i = 0;i < 2; i++) {
1860 s = &bus->ifs[i];
1861 if (s->drive_kind == IDE_CD)
1862 s->status = 0x00; /* NOTE: READY is _not_ set */
1863 else
1864 s->status = READY_STAT | SEEK_STAT;
1865 ide_set_signature(s);
1866 }
1867 }
1868
1869 bus->cmd = val;
1870 }
1871
1872 /*
1873 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1874 * transferred from the device to the guest), false if it's a PIO in
1875 */
1876 static bool ide_is_pio_out(IDEState *s)
1877 {
1878 if (s->end_transfer_func == ide_sector_write ||
1879 s->end_transfer_func == ide_atapi_cmd) {
1880 return false;
1881 } else if (s->end_transfer_func == ide_sector_read ||
1882 s->end_transfer_func == ide_transfer_stop ||
1883 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1884 s->end_transfer_func == ide_dummy_transfer_stop) {
1885 return true;
1886 }
1887
1888 abort();
1889 }
1890
1891 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1892 {
1893 IDEBus *bus = opaque;
1894 IDEState *s = idebus_active_if(bus);
1895 uint8_t *p;
1896
1897 /* PIO data access allowed only when DRQ bit is set. The result of a write
1898 * during PIO out is indeterminate, just ignore it. */
1899 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1900 return;
1901 }
1902
1903 p = s->data_ptr;
1904 *(uint16_t *)p = le16_to_cpu(val);
1905 p += 2;
1906 s->data_ptr = p;
1907 if (p >= s->data_end)
1908 s->end_transfer_func(s);
1909 }
1910
1911 uint32_t ide_data_readw(void *opaque, uint32_t addr)
1912 {
1913 IDEBus *bus = opaque;
1914 IDEState *s = idebus_active_if(bus);
1915 uint8_t *p;
1916 int ret;
1917
1918 /* PIO data access allowed only when DRQ bit is set. The result of a read
1919 * during PIO in is indeterminate, return 0 and don't move forward. */
1920 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1921 return 0;
1922 }
1923
1924 p = s->data_ptr;
1925 ret = cpu_to_le16(*(uint16_t *)p);
1926 p += 2;
1927 s->data_ptr = p;
1928 if (p >= s->data_end)
1929 s->end_transfer_func(s);
1930 return ret;
1931 }
1932
1933 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1934 {
1935 IDEBus *bus = opaque;
1936 IDEState *s = idebus_active_if(bus);
1937 uint8_t *p;
1938
1939 /* PIO data access allowed only when DRQ bit is set. The result of a write
1940 * during PIO out is indeterminate, just ignore it. */
1941 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1942 return;
1943 }
1944
1945 p = s->data_ptr;
1946 *(uint32_t *)p = le32_to_cpu(val);
1947 p += 4;
1948 s->data_ptr = p;
1949 if (p >= s->data_end)
1950 s->end_transfer_func(s);
1951 }
1952
1953 uint32_t ide_data_readl(void *opaque, uint32_t addr)
1954 {
1955 IDEBus *bus = opaque;
1956 IDEState *s = idebus_active_if(bus);
1957 uint8_t *p;
1958 int ret;
1959
1960 /* PIO data access allowed only when DRQ bit is set. The result of a read
1961 * during PIO in is indeterminate, return 0 and don't move forward. */
1962 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1963 return 0;
1964 }
1965
1966 p = s->data_ptr;
1967 ret = cpu_to_le32(*(uint32_t *)p);
1968 p += 4;
1969 s->data_ptr = p;
1970 if (p >= s->data_end)
1971 s->end_transfer_func(s);
1972 return ret;
1973 }
1974
1975 static void ide_dummy_transfer_stop(IDEState *s)
1976 {
1977 s->data_ptr = s->io_buffer;
1978 s->data_end = s->io_buffer;
1979 s->io_buffer[0] = 0xff;
1980 s->io_buffer[1] = 0xff;
1981 s->io_buffer[2] = 0xff;
1982 s->io_buffer[3] = 0xff;
1983 }
1984
1985 static void ide_reset(IDEState *s)
1986 {
1987 #ifdef DEBUG_IDE
1988 printf("ide: reset\n");
1989 #endif
1990
1991 if (s->pio_aiocb) {
1992 bdrv_aio_cancel(s->pio_aiocb);
1993 s->pio_aiocb = NULL;
1994 }
1995
1996 if (s->drive_kind == IDE_CFATA)
1997 s->mult_sectors = 0;
1998 else
1999 s->mult_sectors = MAX_MULT_SECTORS;
2000 /* ide regs */
2001 s->feature = 0;
2002 s->error = 0;
2003 s->nsector = 0;
2004 s->sector = 0;
2005 s->lcyl = 0;
2006 s->hcyl = 0;
2007
2008 /* lba48 */
2009 s->hob_feature = 0;
2010 s->hob_sector = 0;
2011 s->hob_nsector = 0;
2012 s->hob_lcyl = 0;
2013 s->hob_hcyl = 0;
2014
2015 s->select = 0xa0;
2016 s->status = READY_STAT | SEEK_STAT;
2017
2018 s->lba48 = 0;
2019
2020 /* ATAPI specific */
2021 s->sense_key = 0;
2022 s->asc = 0;
2023 s->cdrom_changed = 0;
2024 s->packet_transfer_size = 0;
2025 s->elementary_transfer_size = 0;
2026 s->io_buffer_index = 0;
2027 s->cd_sector_size = 0;
2028 s->atapi_dma = 0;
2029 s->tray_locked = 0;
2030 s->tray_open = 0;
2031 /* ATA DMA state */
2032 s->io_buffer_size = 0;
2033 s->req_nb_sectors = 0;
2034
2035 ide_set_signature(s);
2036 /* init the transfer handler so that 0xffff is returned on data
2037 accesses */
2038 s->end_transfer_func = ide_dummy_transfer_stop;
2039 ide_dummy_transfer_stop(s);
2040 s->media_changed = 0;
2041 }
2042
2043 void ide_bus_reset(IDEBus *bus)
2044 {
2045 bus->unit = 0;
2046 bus->cmd = 0;
2047 ide_reset(&bus->ifs[0]);
2048 ide_reset(&bus->ifs[1]);
2049 ide_clear_hob(bus);
2050
2051 /* pending async DMA */
2052 if (bus->dma->aiocb) {
2053 #ifdef DEBUG_AIO
2054 printf("aio_cancel\n");
2055 #endif
2056 bdrv_aio_cancel(bus->dma->aiocb);
2057 bus->dma->aiocb = NULL;
2058 }
2059
2060 /* reset dma provider too */
2061 bus->dma->ops->reset(bus->dma);
2062 }
2063
2064 static bool ide_cd_is_tray_open(void *opaque)
2065 {
2066 return ((IDEState *)opaque)->tray_open;
2067 }
2068
2069 static bool ide_cd_is_medium_locked(void *opaque)
2070 {
2071 return ((IDEState *)opaque)->tray_locked;
2072 }
2073
2074 static const BlockDevOps ide_cd_block_ops = {
2075 .change_media_cb = ide_cd_change_cb,
2076 .eject_request_cb = ide_cd_eject_request_cb,
2077 .is_tray_open = ide_cd_is_tray_open,
2078 .is_medium_locked = ide_cd_is_medium_locked,
2079 };
2080
2081 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
2082 const char *version, const char *serial, const char *model,
2083 uint64_t wwn,
2084 uint32_t cylinders, uint32_t heads, uint32_t secs,
2085 int chs_trans)
2086 {
2087 uint64_t nb_sectors;
2088
2089 s->bs = bs;
2090 s->drive_kind = kind;
2091
2092 bdrv_get_geometry(bs, &nb_sectors);
2093 s->cylinders = cylinders;
2094 s->heads = heads;
2095 s->sectors = secs;
2096 s->chs_trans = chs_trans;
2097 s->nb_sectors = nb_sectors;
2098 s->wwn = wwn;
2099 /* The SMART values should be preserved across power cycles
2100 but they aren't. */
2101 s->smart_enabled = 1;
2102 s->smart_autosave = 1;
2103 s->smart_errors = 0;
2104 s->smart_selftest_count = 0;
2105 if (kind == IDE_CD) {
2106 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
2107 bdrv_set_guest_block_size(bs, 2048);
2108 } else {
2109 if (!bdrv_is_inserted(s->bs)) {
2110 error_report("Device needs media, but drive is empty");
2111 return -1;
2112 }
2113 if (bdrv_is_read_only(bs)) {
2114 error_report("Can't use a read-only drive");
2115 return -1;
2116 }
2117 }
2118 if (serial) {
2119 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2120 } else {
2121 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2122 "QM%05d", s->drive_serial);
2123 }
2124 if (model) {
2125 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2126 } else {
2127 switch (kind) {
2128 case IDE_CD:
2129 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2130 break;
2131 case IDE_CFATA:
2132 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2133 break;
2134 default:
2135 strcpy(s->drive_model_str, "QEMU HARDDISK");
2136 break;
2137 }
2138 }
2139
2140 if (version) {
2141 pstrcpy(s->version, sizeof(s->version), version);
2142 } else {
2143 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2144 }
2145
2146 ide_reset(s);
2147 bdrv_iostatus_enable(bs);
2148 return 0;
2149 }
2150
2151 static void ide_init1(IDEBus *bus, int unit)
2152 {
2153 static int drive_serial = 1;
2154 IDEState *s = &bus->ifs[unit];
2155
2156 s->bus = bus;
2157 s->unit = unit;
2158 s->drive_serial = drive_serial++;
2159 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2160 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2161 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2162 memset(s->io_buffer, 0, s->io_buffer_total_len);
2163
2164 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
2165 memset(s->smart_selftest_data, 0, 512);
2166
2167 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2168 ide_sector_write_timer_cb, s);
2169 }
2170
2171 static void ide_nop_start(IDEDMA *dma, IDEState *s,
2172 BlockDriverCompletionFunc *cb)
2173 {
2174 }
2175
2176 static int ide_nop(IDEDMA *dma)
2177 {
2178 return 0;
2179 }
2180
2181 static int ide_nop_int(IDEDMA *dma, int x)
2182 {
2183 return 0;
2184 }
2185
2186 static void ide_nop_restart(void *opaque, int x, RunState y)
2187 {
2188 }
2189
2190 static const IDEDMAOps ide_dma_nop_ops = {
2191 .start_dma = ide_nop_start,
2192 .start_transfer = ide_nop,
2193 .prepare_buf = ide_nop_int,
2194 .rw_buf = ide_nop_int,
2195 .set_unit = ide_nop_int,
2196 .add_status = ide_nop_int,
2197 .set_inactive = ide_nop,
2198 .restart_cb = ide_nop_restart,
2199 .reset = ide_nop,
2200 };
2201
2202 static IDEDMA ide_dma_nop = {
2203 .ops = &ide_dma_nop_ops,
2204 .aiocb = NULL,
2205 };
2206
2207 void ide_init2(IDEBus *bus, qemu_irq irq)
2208 {
2209 int i;
2210
2211 for(i = 0; i < 2; i++) {
2212 ide_init1(bus, i);
2213 ide_reset(&bus->ifs[i]);
2214 }
2215 bus->irq = irq;
2216 bus->dma = &ide_dma_nop;
2217 }
2218
2219 static const MemoryRegionPortio ide_portio_list[] = {
2220 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2221 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2222 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2223 PORTIO_END_OF_LIST(),
2224 };
2225
2226 static const MemoryRegionPortio ide_portio2_list[] = {
2227 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2228 PORTIO_END_OF_LIST(),
2229 };
2230
2231 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2232 {
2233 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2234 bridge has been setup properly to always register with ISA. */
2235 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2236
2237 if (iobase2) {
2238 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2239 }
2240 }
2241
2242 static bool is_identify_set(void *opaque, int version_id)
2243 {
2244 IDEState *s = opaque;
2245
2246 return s->identify_set != 0;
2247 }
2248
2249 static EndTransferFunc* transfer_end_table[] = {
2250 ide_sector_read,
2251 ide_sector_write,
2252 ide_transfer_stop,
2253 ide_atapi_cmd_reply_end,
2254 ide_atapi_cmd,
2255 ide_dummy_transfer_stop,
2256 };
2257
2258 static int transfer_end_table_idx(EndTransferFunc *fn)
2259 {
2260 int i;
2261
2262 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2263 if (transfer_end_table[i] == fn)
2264 return i;
2265
2266 return -1;
2267 }
2268
2269 static int ide_drive_post_load(void *opaque, int version_id)
2270 {
2271 IDEState *s = opaque;
2272
2273 if (s->identify_set) {
2274 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2275 }
2276 return 0;
2277 }
2278
2279 static int ide_drive_pio_post_load(void *opaque, int version_id)
2280 {
2281 IDEState *s = opaque;
2282
2283 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2284 return -EINVAL;
2285 }
2286 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2287 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2288 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2289
2290 return 0;
2291 }
2292
2293 static void ide_drive_pio_pre_save(void *opaque)
2294 {
2295 IDEState *s = opaque;
2296 int idx;
2297
2298 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2299 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2300
2301 idx = transfer_end_table_idx(s->end_transfer_func);
2302 if (idx == -1) {
2303 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2304 __func__);
2305 s->end_transfer_fn_idx = 2;
2306 } else {
2307 s->end_transfer_fn_idx = idx;
2308 }
2309 }
2310
2311 static bool ide_drive_pio_state_needed(void *opaque)
2312 {
2313 IDEState *s = opaque;
2314
2315 return ((s->status & DRQ_STAT) != 0)
2316 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
2317 }
2318
2319 static bool ide_tray_state_needed(void *opaque)
2320 {
2321 IDEState *s = opaque;
2322
2323 return s->tray_open || s->tray_locked;
2324 }
2325
2326 static bool ide_atapi_gesn_needed(void *opaque)
2327 {
2328 IDEState *s = opaque;
2329
2330 return s->events.new_media || s->events.eject_request;
2331 }
2332
2333 static bool ide_error_needed(void *opaque)
2334 {
2335 IDEBus *bus = opaque;
2336
2337 return (bus->error_status != 0);
2338 }
2339
2340 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2341 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2342 .name ="ide_drive/atapi/gesn_state",
2343 .version_id = 1,
2344 .minimum_version_id = 1,
2345 .minimum_version_id_old = 1,
2346 .fields = (VMStateField []) {
2347 VMSTATE_BOOL(events.new_media, IDEState),
2348 VMSTATE_BOOL(events.eject_request, IDEState),
2349 VMSTATE_END_OF_LIST()
2350 }
2351 };
2352
2353 static const VMStateDescription vmstate_ide_tray_state = {
2354 .name = "ide_drive/tray_state",
2355 .version_id = 1,
2356 .minimum_version_id = 1,
2357 .minimum_version_id_old = 1,
2358 .fields = (VMStateField[]) {
2359 VMSTATE_BOOL(tray_open, IDEState),
2360 VMSTATE_BOOL(tray_locked, IDEState),
2361 VMSTATE_END_OF_LIST()
2362 }
2363 };
2364
2365 static const VMStateDescription vmstate_ide_drive_pio_state = {
2366 .name = "ide_drive/pio_state",
2367 .version_id = 1,
2368 .minimum_version_id = 1,
2369 .minimum_version_id_old = 1,
2370 .pre_save = ide_drive_pio_pre_save,
2371 .post_load = ide_drive_pio_post_load,
2372 .fields = (VMStateField []) {
2373 VMSTATE_INT32(req_nb_sectors, IDEState),
2374 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2375 vmstate_info_uint8, uint8_t),
2376 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2377 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2378 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2379 VMSTATE_INT32(elementary_transfer_size, IDEState),
2380 VMSTATE_INT32(packet_transfer_size, IDEState),
2381 VMSTATE_END_OF_LIST()
2382 }
2383 };
2384
2385 const VMStateDescription vmstate_ide_drive = {
2386 .name = "ide_drive",
2387 .version_id = 3,
2388 .minimum_version_id = 0,
2389 .minimum_version_id_old = 0,
2390 .post_load = ide_drive_post_load,
2391 .fields = (VMStateField []) {
2392 VMSTATE_INT32(mult_sectors, IDEState),
2393 VMSTATE_INT32(identify_set, IDEState),
2394 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2395 VMSTATE_UINT8(feature, IDEState),
2396 VMSTATE_UINT8(error, IDEState),
2397 VMSTATE_UINT32(nsector, IDEState),
2398 VMSTATE_UINT8(sector, IDEState),
2399 VMSTATE_UINT8(lcyl, IDEState),
2400 VMSTATE_UINT8(hcyl, IDEState),
2401 VMSTATE_UINT8(hob_feature, IDEState),
2402 VMSTATE_UINT8(hob_sector, IDEState),
2403 VMSTATE_UINT8(hob_nsector, IDEState),
2404 VMSTATE_UINT8(hob_lcyl, IDEState),
2405 VMSTATE_UINT8(hob_hcyl, IDEState),
2406 VMSTATE_UINT8(select, IDEState),
2407 VMSTATE_UINT8(status, IDEState),
2408 VMSTATE_UINT8(lba48, IDEState),
2409 VMSTATE_UINT8(sense_key, IDEState),
2410 VMSTATE_UINT8(asc, IDEState),
2411 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2412 VMSTATE_END_OF_LIST()
2413 },
2414 .subsections = (VMStateSubsection []) {
2415 {
2416 .vmsd = &vmstate_ide_drive_pio_state,
2417 .needed = ide_drive_pio_state_needed,
2418 }, {
2419 .vmsd = &vmstate_ide_tray_state,
2420 .needed = ide_tray_state_needed,
2421 }, {
2422 .vmsd = &vmstate_ide_atapi_gesn_state,
2423 .needed = ide_atapi_gesn_needed,
2424 }, {
2425 /* empty */
2426 }
2427 }
2428 };
2429
2430 static const VMStateDescription vmstate_ide_error_status = {
2431 .name ="ide_bus/error",
2432 .version_id = 1,
2433 .minimum_version_id = 1,
2434 .minimum_version_id_old = 1,
2435 .fields = (VMStateField []) {
2436 VMSTATE_INT32(error_status, IDEBus),
2437 VMSTATE_END_OF_LIST()
2438 }
2439 };
2440
2441 const VMStateDescription vmstate_ide_bus = {
2442 .name = "ide_bus",
2443 .version_id = 1,
2444 .minimum_version_id = 1,
2445 .minimum_version_id_old = 1,
2446 .fields = (VMStateField []) {
2447 VMSTATE_UINT8(cmd, IDEBus),
2448 VMSTATE_UINT8(unit, IDEBus),
2449 VMSTATE_END_OF_LIST()
2450 },
2451 .subsections = (VMStateSubsection []) {
2452 {
2453 .vmsd = &vmstate_ide_error_status,
2454 .needed = ide_error_needed,
2455 }, {
2456 /* empty */
2457 }
2458 }
2459 };
2460
2461 void ide_drive_get(DriveInfo **hd, int max_bus)
2462 {
2463 int i;
2464
2465 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2466 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2467 exit(1);
2468 }
2469
2470 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2471 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2472 }
2473 }
AR7 emulation for QEMU