hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/ssi.h"
  12 #include "hw/arm/arm.h"
  13 #include "hw/devices.h"
  14 #include "qemu/timer.h"
  15 #include "hw/i2c/i2c.h"
  16 #include "net/net.h"
  17 #include "hw/boards.h"
  18 #include "exec/address-spaces.h"
  19
  20 #define GPIO_A 0
  21 #define GPIO_B 1
  22 #define GPIO_C 2
  23 #define GPIO_D 3
  24 #define GPIO_E 4
  25 #define GPIO_F 5
  26 #define GPIO_G 6
  27
  28 #define BP_OLED_I2C  0x01
  29 #define BP_OLED_SSI  0x02
  30 #define BP_GAMEPAD   0x04
  31
  32 typedef const struct {
  33     const char *name;
  34     uint32_t did0;
  35     uint32_t did1;
  36     uint32_t dc0;
  37     uint32_t dc1;
  38     uint32_t dc2;
  39     uint32_t dc3;
  40     uint32_t dc4;
  41     uint32_t peripherals;
  42 } stellaris_board_info;
  43
  44 /* General purpose timer module.  */
  45
  46 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  47 #define STELLARIS_GPTM(obj) \
  48     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  49
  50 typedef struct gptm_state {
  51     SysBusDevice parent_obj;
  52
  53     MemoryRegion iomem;
  54     uint32_t config;
  55     uint32_t mode[2];
  56     uint32_t control;
  57     uint32_t state;
  58     uint32_t mask;
  59     uint32_t load[2];
  60     uint32_t match[2];
  61     uint32_t prescale[2];
  62     uint32_t match_prescale[2];
  63     uint32_t rtc;
  64     int64_t tick[2];
  65     struct gptm_state *opaque[2];
  66     QEMUTimer *timer[2];
  67     /* The timers have an alternate output used to trigger the ADC.  */
  68     qemu_irq trigger;
  69     qemu_irq irq;
  70 } gptm_state;
  71
  72 static void gptm_update_irq(gptm_state *s)
  73 {
  74     int level;
  75     level = (s->state & s->mask) != 0;
  76     qemu_set_irq(s->irq, level);
  77 }
  78
  79 static void gptm_stop(gptm_state *s, int n)
  80 {
  81     timer_del(s->timer[n]);
  82 }
  83
  84 static void gptm_reload(gptm_state *s, int n, int reset)
  85 {
  86     int64_t tick;
  87     if (reset)
  88         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  89     else
  90         tick = s->tick[n];
  91
  92     if (s->config == 0) {
  93         /* 32-bit CountDown.  */
  94         uint32_t count;
  95         count = s->load[0] | (s->load[1] << 16);
  96         tick += (int64_t)count * system_clock_scale;
  97     } else if (s->config == 1) {
  98         /* 32-bit RTC.  1Hz tick.  */
  99         tick += get_ticks_per_sec();
 100     } else if (s->mode[n] == 0xa) {
 101         /* PWM mode.  Not implemented.  */
 102     } else {
 103         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 104     }
 105     s->tick[n] = tick;
 106     timer_mod(s->timer[n], tick);
 107 }
 108
 109 static void gptm_tick(void *opaque)
 110 {
 111     gptm_state **p = (gptm_state **)opaque;
 112     gptm_state *s;
 113     int n;
 114
 115     s = *p;
 116     n = p - s->opaque;
 117     if (s->config == 0) {
 118         s->state |= 1;
 119         if ((s->control & 0x20)) {
 120             /* Output trigger.  */
 121             qemu_irq_pulse(s->trigger);
 122         }
 123         if (s->mode[0] & 1) {
 124             /* One-shot.  */
 125             s->control &= ~1;
 126         } else {
 127             /* Periodic.  */
 128             gptm_reload(s, 0, 0);
 129         }
 130     } else if (s->config == 1) {
 131         /* RTC.  */
 132         uint32_t match;
 133         s->rtc++;
 134         match = s->match[0] | (s->match[1] << 16);
 135         if (s->rtc > match)
 136             s->rtc = 0;
 137         if (s->rtc == 0) {
 138             s->state |= 8;
 139         }
 140         gptm_reload(s, 0, 0);
 141     } else if (s->mode[n] == 0xa) {
 142         /* PWM mode.  Not implemented.  */
 143     } else {
 144         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 145     }
 146     gptm_update_irq(s);
 147 }
 148
 149 static uint64_t gptm_read(void *opaque, hwaddr offset,
 150                           unsigned size)
 151 {
 152     gptm_state *s = (gptm_state *)opaque;
 153
 154     switch (offset) {
 155     case 0x00: /* CFG */
 156         return s->config;
 157     case 0x04: /* TAMR */
 158         return s->mode[0];
 159     case 0x08: /* TBMR */
 160         return s->mode[1];
 161     case 0x0c: /* CTL */
 162         return s->control;
 163     case 0x18: /* IMR */
 164         return s->mask;
 165     case 0x1c: /* RIS */
 166         return s->state;
 167     case 0x20: /* MIS */
 168         return s->state & s->mask;
 169     case 0x24: /* CR */
 170         return 0;
 171     case 0x28: /* TAILR */
 172         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 173     case 0x2c: /* TBILR */
 174         return s->load[1];
 175     case 0x30: /* TAMARCHR */
 176         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 177     case 0x34: /* TBMATCHR */
 178         return s->match[1];
 179     case 0x38: /* TAPR */
 180         return s->prescale[0];
 181     case 0x3c: /* TBPR */
 182         return s->prescale[1];
 183     case 0x40: /* TAPMR */
 184         return s->match_prescale[0];
 185     case 0x44: /* TBPMR */
 186         return s->match_prescale[1];
 187     case 0x48: /* TAR */
 188         if (s->control == 1)
 189             return s->rtc;
 190     case 0x4c: /* TBR */
 191         hw_error("TODO: Timer value read\n");
 192     default:
 193         hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
 194         return 0;
 195     }
 196 }
 197
 198 static void gptm_write(void *opaque, hwaddr offset,
 199                        uint64_t value, unsigned size)
 200 {
 201     gptm_state *s = (gptm_state *)opaque;
 202     uint32_t oldval;
 203
 204     /* The timers should be disabled before changing the configuration.
 205        We take advantage of this and defer everything until the timer
 206        is enabled.  */
 207     switch (offset) {
 208     case 0x00: /* CFG */
 209         s->config = value;
 210         break;
 211     case 0x04: /* TAMR */
 212         s->mode[0] = value;
 213         break;
 214     case 0x08: /* TBMR */
 215         s->mode[1] = value;
 216         break;
 217     case 0x0c: /* CTL */
 218         oldval = s->control;
 219         s->control = value;
 220         /* TODO: Implement pause.  */
 221         if ((oldval ^ value) & 1) {
 222             if (value & 1) {
 223                 gptm_reload(s, 0, 1);
 224             } else {
 225                 gptm_stop(s, 0);
 226             }
 227         }
 228         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 229             if (value & 0x100) {
 230                 gptm_reload(s, 1, 1);
 231             } else {
 232                 gptm_stop(s, 1);
 233             }
 234         }
 235         break;
 236     case 0x18: /* IMR */
 237         s->mask = value & 0x77;
 238         gptm_update_irq(s);
 239         break;
 240     case 0x24: /* CR */
 241         s->state &= ~value;
 242         break;
 243     case 0x28: /* TAILR */
 244         s->load[0] = value & 0xffff;
 245         if (s->config < 4) {
 246             s->load[1] = value >> 16;
 247         }
 248         break;
 249     case 0x2c: /* TBILR */
 250         s->load[1] = value & 0xffff;
 251         break;
 252     case 0x30: /* TAMARCHR */
 253         s->match[0] = value & 0xffff;
 254         if (s->config < 4) {
 255             s->match[1] = value >> 16;
 256         }
 257         break;
 258     case 0x34: /* TBMATCHR */
 259         s->match[1] = value >> 16;
 260         break;
 261     case 0x38: /* TAPR */
 262         s->prescale[0] = value;
 263         break;
 264     case 0x3c: /* TBPR */
 265         s->prescale[1] = value;
 266         break;
 267     case 0x40: /* TAPMR */
 268         s->match_prescale[0] = value;
 269         break;
 270     case 0x44: /* TBPMR */
 271         s->match_prescale[0] = value;
 272         break;
 273     default:
 274         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 275     }
 276     gptm_update_irq(s);
 277 }
 278
 279 static const MemoryRegionOps gptm_ops = {
 280     .read = gptm_read,
 281     .write = gptm_write,
 282     .endianness = DEVICE_NATIVE_ENDIAN,
 283 };
 284
 285 static const VMStateDescription vmstate_stellaris_gptm = {
 286     .name = "stellaris_gptm",
 287     .version_id = 1,
 288     .minimum_version_id = 1,
 289     .minimum_version_id_old = 1,
 290     .fields      = (VMStateField[]) {
 291         VMSTATE_UINT32(config, gptm_state),
 292         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 293         VMSTATE_UINT32(control, gptm_state),
 294         VMSTATE_UINT32(state, gptm_state),
 295         VMSTATE_UINT32(mask, gptm_state),
 296         VMSTATE_UNUSED(8),
 297         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 298         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 299         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 300         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 301         VMSTATE_UINT32(rtc, gptm_state),
 302         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 303         VMSTATE_TIMER_ARRAY(timer, gptm_state, 2),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static int stellaris_gptm_init(SysBusDevice *sbd)
 309 {
 310     DeviceState *dev = DEVICE(sbd);
 311     gptm_state *s = STELLARIS_GPTM(dev);
 312
 313     sysbus_init_irq(sbd, &s->irq);
 314     qdev_init_gpio_out(dev, &s->trigger, 1);
 315
 316     memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
 317                           "gptm", 0x1000);
 318     sysbus_init_mmio(sbd, &s->iomem);
 319
 320     s->opaque[0] = s->opaque[1] = s;
 321     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 322     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 323     vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
 324     return 0;
 325 }
 326
 327
 328 /* System controller.  */
 329
 330 typedef struct {
 331     MemoryRegion iomem;
 332     uint32_t pborctl;
 333     uint32_t ldopctl;
 334     uint32_t int_status;
 335     uint32_t int_mask;
 336     uint32_t resc;
 337     uint32_t rcc;
 338     uint32_t rcc2;
 339     uint32_t rcgc[3];
 340     uint32_t scgc[3];
 341     uint32_t dcgc[3];
 342     uint32_t clkvclr;
 343     uint32_t ldoarst;
 344     uint32_t user0;
 345     uint32_t user1;
 346     qemu_irq irq;
 347     stellaris_board_info *board;
 348 } ssys_state;
 349
 350 static void ssys_update(ssys_state *s)
 351 {
 352   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 353 }
 354
 355 static uint32_t pllcfg_sandstorm[16] = {
 356     0x31c0, /* 1 Mhz */
 357     0x1ae0, /* 1.8432 Mhz */
 358     0x18c0, /* 2 Mhz */
 359     0xd573, /* 2.4576 Mhz */
 360     0x37a6, /* 3.57954 Mhz */
 361     0x1ae2, /* 3.6864 Mhz */
 362     0x0c40, /* 4 Mhz */
 363     0x98bc, /* 4.906 Mhz */
 364     0x935b, /* 4.9152 Mhz */
 365     0x09c0, /* 5 Mhz */
 366     0x4dee, /* 5.12 Mhz */
 367     0x0c41, /* 6 Mhz */
 368     0x75db, /* 6.144 Mhz */
 369     0x1ae6, /* 7.3728 Mhz */
 370     0x0600, /* 8 Mhz */
 371     0x585b /* 8.192 Mhz */
 372 };
 373
 374 static uint32_t pllcfg_fury[16] = {
 375     0x3200, /* 1 Mhz */
 376     0x1b20, /* 1.8432 Mhz */
 377     0x1900, /* 2 Mhz */
 378     0xf42b, /* 2.4576 Mhz */
 379     0x37e3, /* 3.57954 Mhz */
 380     0x1b21, /* 3.6864 Mhz */
 381     0x0c80, /* 4 Mhz */
 382     0x98ee, /* 4.906 Mhz */
 383     0xd5b4, /* 4.9152 Mhz */
 384     0x0a00, /* 5 Mhz */
 385     0x4e27, /* 5.12 Mhz */
 386     0x1902, /* 6 Mhz */
 387     0xec1c, /* 6.144 Mhz */
 388     0x1b23, /* 7.3728 Mhz */
 389     0x0640, /* 8 Mhz */
 390     0xb11c /* 8.192 Mhz */
 391 };
 392
 393 #define DID0_VER_MASK        0x70000000
 394 #define DID0_VER_0           0x00000000
 395 #define DID0_VER_1           0x10000000
 396
 397 #define DID0_CLASS_MASK      0x00FF0000
 398 #define DID0_CLASS_SANDSTORM 0x00000000
 399 #define DID0_CLASS_FURY      0x00010000
 400
 401 static int ssys_board_class(const ssys_state *s)
 402 {
 403     uint32_t did0 = s->board->did0;
 404     switch (did0 & DID0_VER_MASK) {
 405     case DID0_VER_0:
 406         return DID0_CLASS_SANDSTORM;
 407     case DID0_VER_1:
 408         switch (did0 & DID0_CLASS_MASK) {
 409         case DID0_CLASS_SANDSTORM:
 410         case DID0_CLASS_FURY:
 411             return did0 & DID0_CLASS_MASK;
 412         }
 413         /* for unknown classes, fall through */
 414     default:
 415         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 416     }
 417 }
 418
 419 static uint64_t ssys_read(void *opaque, hwaddr offset,
 420                           unsigned size)
 421 {
 422     ssys_state *s = (ssys_state *)opaque;
 423
 424     switch (offset) {
 425     case 0x000: /* DID0 */
 426         return s->board->did0;
 427     case 0x004: /* DID1 */
 428         return s->board->did1;
 429     case 0x008: /* DC0 */
 430         return s->board->dc0;
 431     case 0x010: /* DC1 */
 432         return s->board->dc1;
 433     case 0x014: /* DC2 */
 434         return s->board->dc2;
 435     case 0x018: /* DC3 */
 436         return s->board->dc3;
 437     case 0x01c: /* DC4 */
 438         return s->board->dc4;
 439     case 0x030: /* PBORCTL */
 440         return s->pborctl;
 441     case 0x034: /* LDOPCTL */
 442         return s->ldopctl;
 443     case 0x040: /* SRCR0 */
 444         return 0;
 445     case 0x044: /* SRCR1 */
 446         return 0;
 447     case 0x048: /* SRCR2 */
 448         return 0;
 449     case 0x050: /* RIS */
 450         return s->int_status;
 451     case 0x054: /* IMC */
 452         return s->int_mask;
 453     case 0x058: /* MISC */
 454         return s->int_status & s->int_mask;
 455     case 0x05c: /* RESC */
 456         return s->resc;
 457     case 0x060: /* RCC */
 458         return s->rcc;
 459     case 0x064: /* PLLCFG */
 460         {
 461             int xtal;
 462             xtal = (s->rcc >> 6) & 0xf;
 463             switch (ssys_board_class(s)) {
 464             case DID0_CLASS_FURY:
 465                 return pllcfg_fury[xtal];
 466             case DID0_CLASS_SANDSTORM:
 467                 return pllcfg_sandstorm[xtal];
 468             default:
 469                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 470                 return 0;
 471             }
 472         }
 473     case 0x070: /* RCC2 */
 474         return s->rcc2;
 475     case 0x100: /* RCGC0 */
 476         return s->rcgc[0];
 477     case 0x104: /* RCGC1 */
 478         return s->rcgc[1];
 479     case 0x108: /* RCGC2 */
 480         return s->rcgc[2];
 481     case 0x110: /* SCGC0 */
 482         return s->scgc[0];
 483     case 0x114: /* SCGC1 */
 484         return s->scgc[1];
 485     case 0x118: /* SCGC2 */
 486         return s->scgc[2];
 487     case 0x120: /* DCGC0 */
 488         return s->dcgc[0];
 489     case 0x124: /* DCGC1 */
 490         return s->dcgc[1];
 491     case 0x128: /* DCGC2 */
 492         return s->dcgc[2];
 493     case 0x150: /* CLKVCLR */
 494         return s->clkvclr;
 495     case 0x160: /* LDOARST */
 496         return s->ldoarst;
 497     case 0x1e0: /* USER0 */
 498         return s->user0;
 499     case 0x1e4: /* USER1 */
 500         return s->user1;
 501     default:
 502         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 503         return 0;
 504     }
 505 }
 506
 507 static bool ssys_use_rcc2(ssys_state *s)
 508 {
 509     return (s->rcc2 >> 31) & 0x1;
 510 }
 511
 512 /*
 513  * Caculate the sys. clock period in ms.
 514  */
 515 static void ssys_calculate_system_clock(ssys_state *s)
 516 {
 517     if (ssys_use_rcc2(s)) {
 518         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 519     } else {
 520         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 521     }
 522 }
 523
 524 static void ssys_write(void *opaque, hwaddr offset,
 525                        uint64_t value, unsigned size)
 526 {
 527     ssys_state *s = (ssys_state *)opaque;
 528
 529     switch (offset) {
 530     case 0x030: /* PBORCTL */
 531         s->pborctl = value & 0xffff;
 532         break;
 533     case 0x034: /* LDOPCTL */
 534         s->ldopctl = value & 0x1f;
 535         break;
 536     case 0x040: /* SRCR0 */
 537     case 0x044: /* SRCR1 */
 538     case 0x048: /* SRCR2 */
 539         fprintf(stderr, "Peripheral reset not implemented\n");
 540         break;
 541     case 0x054: /* IMC */
 542         s->int_mask = value & 0x7f;
 543         break;
 544     case 0x058: /* MISC */
 545         s->int_status &= ~value;
 546         break;
 547     case 0x05c: /* RESC */
 548         s->resc = value & 0x3f;
 549         break;
 550     case 0x060: /* RCC */
 551         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 552             /* PLL enable.  */
 553             s->int_status |= (1 << 6);
 554         }
 555         s->rcc = value;
 556         ssys_calculate_system_clock(s);
 557         break;
 558     case 0x070: /* RCC2 */
 559         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 560             break;
 561         }
 562
 563         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 564             /* PLL enable.  */
 565             s->int_status |= (1 << 6);
 566         }
 567         s->rcc2 = value;
 568         ssys_calculate_system_clock(s);
 569         break;
 570     case 0x100: /* RCGC0 */
 571         s->rcgc[0] = value;
 572         break;
 573     case 0x104: /* RCGC1 */
 574         s->rcgc[1] = value;
 575         break;
 576     case 0x108: /* RCGC2 */
 577         s->rcgc[2] = value;
 578         break;
 579     case 0x110: /* SCGC0 */
 580         s->scgc[0] = value;
 581         break;
 582     case 0x114: /* SCGC1 */
 583         s->scgc[1] = value;
 584         break;
 585     case 0x118: /* SCGC2 */
 586         s->scgc[2] = value;
 587         break;
 588     case 0x120: /* DCGC0 */
 589         s->dcgc[0] = value;
 590         break;
 591     case 0x124: /* DCGC1 */
 592         s->dcgc[1] = value;
 593         break;
 594     case 0x128: /* DCGC2 */
 595         s->dcgc[2] = value;
 596         break;
 597     case 0x150: /* CLKVCLR */
 598         s->clkvclr = value;
 599         break;
 600     case 0x160: /* LDOARST */
 601         s->ldoarst = value;
 602         break;
 603     default:
 604         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 605     }
 606     ssys_update(s);
 607 }
 608
 609 static const MemoryRegionOps ssys_ops = {
 610     .read = ssys_read,
 611     .write = ssys_write,
 612     .endianness = DEVICE_NATIVE_ENDIAN,
 613 };
 614
 615 static void ssys_reset(void *opaque)
 616 {
 617     ssys_state *s = (ssys_state *)opaque;
 618
 619     s->pborctl = 0x7ffd;
 620     s->rcc = 0x078e3ac0;
 621
 622     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 623         s->rcc2 = 0;
 624     } else {
 625         s->rcc2 = 0x07802810;
 626     }
 627     s->rcgc[0] = 1;
 628     s->scgc[0] = 1;
 629     s->dcgc[0] = 1;
 630     ssys_calculate_system_clock(s);
 631 }
 632
 633 static int stellaris_sys_post_load(void *opaque, int version_id)
 634 {
 635     ssys_state *s = opaque;
 636
 637     ssys_calculate_system_clock(s);
 638
 639     return 0;
 640 }
 641
 642 static const VMStateDescription vmstate_stellaris_sys = {
 643     .name = "stellaris_sys",
 644     .version_id = 2,
 645     .minimum_version_id = 1,
 646     .minimum_version_id_old = 1,
 647     .post_load = stellaris_sys_post_load,
 648     .fields      = (VMStateField[]) {
 649         VMSTATE_UINT32(pborctl, ssys_state),
 650         VMSTATE_UINT32(ldopctl, ssys_state),
 651         VMSTATE_UINT32(int_mask, ssys_state),
 652         VMSTATE_UINT32(int_status, ssys_state),
 653         VMSTATE_UINT32(resc, ssys_state),
 654         VMSTATE_UINT32(rcc, ssys_state),
 655         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 656         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 657         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 658         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 659         VMSTATE_UINT32(clkvclr, ssys_state),
 660         VMSTATE_UINT32(ldoarst, ssys_state),
 661         VMSTATE_END_OF_LIST()
 662     }
 663 };
 664
 665 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 666                               stellaris_board_info * board,
 667                               uint8_t *macaddr)
 668 {
 669     ssys_state *s;
 670
 671     s = (ssys_state *)g_malloc0(sizeof(ssys_state));
 672     s->irq = irq;
 673     s->board = board;
 674     /* Most devices come preprogrammed with a MAC address in the user data. */
 675     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 676     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 677
 678     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 679     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 680     ssys_reset(s);
 681     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 682     return 0;
 683 }
 684
 685
 686 /* I2C controller.  */
 687
 688 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 689 #define STELLARIS_I2C(obj) \
 690     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 691
 692 typedef struct {
 693     SysBusDevice parent_obj;
 694
 695     I2CBus *bus;
 696     qemu_irq irq;
 697     MemoryRegion iomem;
 698     uint32_t msa;
 699     uint32_t mcs;
 700     uint32_t mdr;
 701     uint32_t mtpr;
 702     uint32_t mimr;
 703     uint32_t mris;
 704     uint32_t mcr;
 705 } stellaris_i2c_state;
 706
 707 #define STELLARIS_I2C_MCS_BUSY    0x01
 708 #define STELLARIS_I2C_MCS_ERROR   0x02
 709 #define STELLARIS_I2C_MCS_ADRACK  0x04
 710 #define STELLARIS_I2C_MCS_DATACK  0x08
 711 #define STELLARIS_I2C_MCS_ARBLST  0x10
 712 #define STELLARIS_I2C_MCS_IDLE    0x20
 713 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 714
 715 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 716                                    unsigned size)
 717 {
 718     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 719
 720     switch (offset) {
 721     case 0x00: /* MSA */
 722         return s->msa;
 723     case 0x04: /* MCS */
 724         /* We don't emulate timing, so the controller is never busy.  */
 725         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 726     case 0x08: /* MDR */
 727         return s->mdr;
 728     case 0x0c: /* MTPR */
 729         return s->mtpr;
 730     case 0x10: /* MIMR */
 731         return s->mimr;
 732     case 0x14: /* MRIS */
 733         return s->mris;
 734     case 0x18: /* MMIS */
 735         return s->mris & s->mimr;
 736     case 0x20: /* MCR */
 737         return s->mcr;
 738     default:
 739         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 740         return 0;
 741     }
 742 }
 743
 744 static void stellaris_i2c_update(stellaris_i2c_state *s)
 745 {
 746     int level;
 747
 748     level = (s->mris & s->mimr) != 0;
 749     qemu_set_irq(s->irq, level);
 750 }
 751
 752 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 753                                 uint64_t value, unsigned size)
 754 {
 755     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 756
 757     switch (offset) {
 758     case 0x00: /* MSA */
 759         s->msa = value & 0xff;
 760         break;
 761     case 0x04: /* MCS */
 762         if ((s->mcr & 0x10) == 0) {
 763             /* Disabled.  Do nothing.  */
 764             break;
 765         }
 766         /* Grab the bus if this is starting a transfer.  */
 767         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 768             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 769                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 770             } else {
 771                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 772                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 773             }
 774         }
 775         /* If we don't have the bus then indicate an error.  */
 776         if (!i2c_bus_busy(s->bus)
 777                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 778             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 779             break;
 780         }
 781         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 782         if (value & 1) {
 783             /* Transfer a byte.  */
 784             /* TODO: Handle errors.  */
 785             if (s->msa & 1) {
 786                 /* Recv */
 787                 s->mdr = i2c_recv(s->bus) & 0xff;
 788             } else {
 789                 /* Send */
 790                 i2c_send(s->bus, s->mdr);
 791             }
 792             /* Raise an interrupt.  */
 793             s->mris |= 1;
 794         }
 795         if (value & 4) {
 796             /* Finish transfer.  */
 797             i2c_end_transfer(s->bus);
 798             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 799         }
 800         break;
 801     case 0x08: /* MDR */
 802         s->mdr = value & 0xff;
 803         break;
 804     case 0x0c: /* MTPR */
 805         s->mtpr = value & 0xff;
 806         break;
 807     case 0x10: /* MIMR */
 808         s->mimr = 1;
 809         break;
 810     case 0x1c: /* MICR */
 811         s->mris &= ~value;
 812         break;
 813     case 0x20: /* MCR */
 814         if (value & 1)
 815             hw_error(
 816                       "stellaris_i2c_write: Loopback not implemented\n");
 817         if (value & 0x20)
 818             hw_error(
 819                       "stellaris_i2c_write: Slave mode not implemented\n");
 820         s->mcr = value & 0x31;
 821         break;
 822     default:
 823         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 824                   (int)offset);
 825     }
 826     stellaris_i2c_update(s);
 827 }
 828
 829 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 830 {
 831     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 832         i2c_end_transfer(s->bus);
 833
 834     s->msa = 0;
 835     s->mcs = 0;
 836     s->mdr = 0;
 837     s->mtpr = 1;
 838     s->mimr = 0;
 839     s->mris = 0;
 840     s->mcr = 0;
 841     stellaris_i2c_update(s);
 842 }
 843
 844 static const MemoryRegionOps stellaris_i2c_ops = {
 845     .read = stellaris_i2c_read,
 846     .write = stellaris_i2c_write,
 847     .endianness = DEVICE_NATIVE_ENDIAN,
 848 };
 849
 850 static const VMStateDescription vmstate_stellaris_i2c = {
 851     .name = "stellaris_i2c",
 852     .version_id = 1,
 853     .minimum_version_id = 1,
 854     .minimum_version_id_old = 1,
 855     .fields      = (VMStateField[]) {
 856         VMSTATE_UINT32(msa, stellaris_i2c_state),
 857         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 858         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 859         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 860         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 861         VMSTATE_UINT32(mris, stellaris_i2c_state),
 862         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 863         VMSTATE_END_OF_LIST()
 864     }
 865 };
 866
 867 static int stellaris_i2c_init(SysBusDevice *sbd)
 868 {
 869     DeviceState *dev = DEVICE(sbd);
 870     stellaris_i2c_state *s = STELLARIS_I2C(dev);
 871     I2CBus *bus;
 872
 873     sysbus_init_irq(sbd, &s->irq);
 874     bus = i2c_init_bus(dev, "i2c");
 875     s->bus = bus;
 876
 877     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
 878                           "i2c", 0x1000);
 879     sysbus_init_mmio(sbd, &s->iomem);
 880     /* ??? For now we only implement the master interface.  */
 881     stellaris_i2c_reset(s);
 882     vmstate_register(dev, -1, &vmstate_stellaris_i2c, s);
 883     return 0;
 884 }
 885
 886 /* Analogue to Digital Converter.  This is only partially implemented,
 887    enough for applications that use a combined ADC and timer tick.  */
 888
 889 #define STELLARIS_ADC_EM_CONTROLLER 0
 890 #define STELLARIS_ADC_EM_COMP       1
 891 #define STELLARIS_ADC_EM_EXTERNAL   4
 892 #define STELLARIS_ADC_EM_TIMER      5
 893 #define STELLARIS_ADC_EM_PWM0       6
 894 #define STELLARIS_ADC_EM_PWM1       7
 895 #define STELLARIS_ADC_EM_PWM2       8
 896
 897 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 898 #define STELLARIS_ADC_FIFO_FULL     0x1000
 899
 900 #define TYPE_STELLARIS_ADC "stellaris-adc"
 901 #define STELLARIS_ADC(obj) \
 902     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 903
 904 typedef struct StellarisADCState {
 905     SysBusDevice parent_obj;
 906
 907     MemoryRegion iomem;
 908     uint32_t actss;
 909     uint32_t ris;
 910     uint32_t im;
 911     uint32_t emux;
 912     uint32_t ostat;
 913     uint32_t ustat;
 914     uint32_t sspri;
 915     uint32_t sac;
 916     struct {
 917         uint32_t state;
 918         uint32_t data[16];
 919     } fifo[4];
 920     uint32_t ssmux[4];
 921     uint32_t ssctl[4];
 922     uint32_t noise;
 923     qemu_irq irq[4];
 924 } stellaris_adc_state;
 925
 926 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 927 {
 928     int tail;
 929
 930     tail = s->fifo[n].state & 0xf;
 931     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 932         s->ustat |= 1 << n;
 933     } else {
 934         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 935         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 936         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 937             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 938     }
 939     return s->fifo[n].data[tail];
 940 }
 941
 942 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 943                                      uint32_t value)
 944 {
 945     int head;
 946
 947     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 948        FIFO fir each sequencer.  */
 949     head = (s->fifo[n].state >> 4) & 0xf;
 950     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 951         s->ostat |= 1 << n;
 952         return;
 953     }
 954     s->fifo[n].data[head] = value;
 955     head = (head + 1) & 0xf;
 956     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 957     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 958     if ((s->fifo[n].state & 0xf) == head)
 959         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 960 }
 961
 962 static void stellaris_adc_update(stellaris_adc_state *s)
 963 {
 964     int level;
 965     int n;
 966
 967     for (n = 0; n < 4; n++) {
 968         level = (s->ris & s->im & (1 << n)) != 0;
 969         qemu_set_irq(s->irq[n], level);
 970     }
 971 }
 972
 973 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 974 {
 975     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 976     int n;
 977
 978     for (n = 0; n < 4; n++) {
 979         if ((s->actss & (1 << n)) == 0) {
 980             continue;
 981         }
 982
 983         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 984             continue;
 985         }
 986
 987         /* Some applications use the ADC as a random number source, so introduce
 988            some variation into the signal.  */
 989         s->noise = s->noise * 314159 + 1;
 990         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 991         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 992         s->ris |= (1 << n);
 993         stellaris_adc_update(s);
 994     }
 995 }
 996
 997 static void stellaris_adc_reset(stellaris_adc_state *s)
 998 {
 999     int n;
1000
1001     for (n = 0; n < 4; n++) {
1002         s->ssmux[n] = 0;
1003         s->ssctl[n] = 0;
1004         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1005     }
1006 }
1007
1008 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1009                                    unsigned size)
1010 {
1011     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1012
1013     /* TODO: Implement this.  */
1014     if (offset >= 0x40 && offset < 0xc0) {
1015         int n;
1016         n = (offset - 0x40) >> 5;
1017         switch (offset & 0x1f) {
1018         case 0x00: /* SSMUX */
1019             return s->ssmux[n];
1020         case 0x04: /* SSCTL */
1021             return s->ssctl[n];
1022         case 0x08: /* SSFIFO */
1023             return stellaris_adc_fifo_read(s, n);
1024         case 0x0c: /* SSFSTAT */
1025             return s->fifo[n].state;
1026         default:
1027             break;
1028         }
1029     }
1030     switch (offset) {
1031     case 0x00: /* ACTSS */
1032         return s->actss;
1033     case 0x04: /* RIS */
1034         return s->ris;
1035     case 0x08: /* IM */
1036         return s->im;
1037     case 0x0c: /* ISC */
1038         return s->ris & s->im;
1039     case 0x10: /* OSTAT */
1040         return s->ostat;
1041     case 0x14: /* EMUX */
1042         return s->emux;
1043     case 0x18: /* USTAT */
1044         return s->ustat;
1045     case 0x20: /* SSPRI */
1046         return s->sspri;
1047     case 0x30: /* SAC */
1048         return s->sac;
1049     default:
1050         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1051                   (int)offset);
1052         return 0;
1053     }
1054 }
1055
1056 static void stellaris_adc_write(void *opaque, hwaddr offset,
1057                                 uint64_t value, unsigned size)
1058 {
1059     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1060
1061     /* TODO: Implement this.  */
1062     if (offset >= 0x40 && offset < 0xc0) {
1063         int n;
1064         n = (offset - 0x40) >> 5;
1065         switch (offset & 0x1f) {
1066         case 0x00: /* SSMUX */
1067             s->ssmux[n] = value & 0x33333333;
1068             return;
1069         case 0x04: /* SSCTL */
1070             if (value != 6) {
1071                 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
1072                           value);
1073             }
1074             s->ssctl[n] = value;
1075             return;
1076         default:
1077             break;
1078         }
1079     }
1080     switch (offset) {
1081     case 0x00: /* ACTSS */
1082         s->actss = value & 0xf;
1083         break;
1084     case 0x08: /* IM */
1085         s->im = value;
1086         break;
1087     case 0x0c: /* ISC */
1088         s->ris &= ~value;
1089         break;
1090     case 0x10: /* OSTAT */
1091         s->ostat &= ~value;
1092         break;
1093     case 0x14: /* EMUX */
1094         s->emux = value;
1095         break;
1096     case 0x18: /* USTAT */
1097         s->ustat &= ~value;
1098         break;
1099     case 0x20: /* SSPRI */
1100         s->sspri = value;
1101         break;
1102     case 0x28: /* PSSI */
1103         hw_error("Not implemented:  ADC sample initiate\n");
1104         break;
1105     case 0x30: /* SAC */
1106         s->sac = value;
1107         break;
1108     default:
1109         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1110     }
1111     stellaris_adc_update(s);
1112 }
1113
1114 static const MemoryRegionOps stellaris_adc_ops = {
1115     .read = stellaris_adc_read,
1116     .write = stellaris_adc_write,
1117     .endianness = DEVICE_NATIVE_ENDIAN,
1118 };
1119
1120 static const VMStateDescription vmstate_stellaris_adc = {
1121     .name = "stellaris_adc",
1122     .version_id = 1,
1123     .minimum_version_id = 1,
1124     .minimum_version_id_old = 1,
1125     .fields      = (VMStateField[]) {
1126         VMSTATE_UINT32(actss, stellaris_adc_state),
1127         VMSTATE_UINT32(ris, stellaris_adc_state),
1128         VMSTATE_UINT32(im, stellaris_adc_state),
1129         VMSTATE_UINT32(emux, stellaris_adc_state),
1130         VMSTATE_UINT32(ostat, stellaris_adc_state),
1131         VMSTATE_UINT32(ustat, stellaris_adc_state),
1132         VMSTATE_UINT32(sspri, stellaris_adc_state),
1133         VMSTATE_UINT32(sac, stellaris_adc_state),
1134         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1135         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1136         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1137         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1138         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1139         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1140         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1141         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1142         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1143         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1144         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1145         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1146         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1147         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1148         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1149         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1150         VMSTATE_UINT32(noise, stellaris_adc_state),
1151         VMSTATE_END_OF_LIST()
1152     }
1153 };
1154
1155 static int stellaris_adc_init(SysBusDevice *sbd)
1156 {
1157     DeviceState *dev = DEVICE(sbd);
1158     stellaris_adc_state *s = STELLARIS_ADC(dev);
1159     int n;
1160
1161     for (n = 0; n < 4; n++) {
1162         sysbus_init_irq(sbd, &s->irq[n]);
1163     }
1164
1165     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
1166                           "adc", 0x1000);
1167     sysbus_init_mmio(sbd, &s->iomem);
1168     stellaris_adc_reset(s);
1169     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1170     vmstate_register(dev, -1, &vmstate_stellaris_adc, s);
1171     return 0;
1172 }
1173
1174 /* Board init.  */
1175 static stellaris_board_info stellaris_boards[] = {
1176   { "LM3S811EVB",
1177     0,
1178     0x0032000e,
1179     0x001f001f, /* dc0 */
1180     0x001132bf,
1181     0x01071013,
1182     0x3f0f01ff,
1183     0x0000001f,
1184     BP_OLED_I2C
1185   },
1186   { "LM3S6965EVB",
1187     0x10010002,
1188     0x1073402e,
1189     0x00ff007f, /* dc0 */
1190     0x001133ff,
1191     0x030f5317,
1192     0x0f0f87ff,
1193     0x5000007f,
1194     BP_OLED_SSI | BP_GAMEPAD
1195   }
1196 };
1197
1198 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1199                            stellaris_board_info *board)
1200 {
1201     static const int uart_irq[] = {5, 6, 33, 34};
1202     static const int timer_irq[] = {19, 21, 23, 35};
1203     static const uint32_t gpio_addr[7] =
1204       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1205         0x40024000, 0x40025000, 0x40026000};
1206     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1207
1208     MemoryRegion *address_space_mem = get_system_memory();
1209     qemu_irq *pic;
1210     DeviceState *gpio_dev[7];
1211     qemu_irq gpio_in[7][8];
1212     qemu_irq gpio_out[7][8];
1213     qemu_irq adc;
1214     int sram_size;
1215     int flash_size;
1216     I2CBus *i2c;
1217     DeviceState *dev;
1218     int i;
1219     int j;
1220
1221     flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1222     sram_size = (board->dc0 >> 18) + 1;
1223     pic = armv7m_init(address_space_mem,
1224                       flash_size, sram_size, kernel_filename, cpu_model);
1225
1226     if (board->dc1 & (1 << 16)) {
1227         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1228                                     pic[14], pic[15], pic[16], pic[17], NULL);
1229         adc = qdev_get_gpio_in(dev, 0);
1230     } else {
1231         adc = NULL;
1232     }
1233     for (i = 0; i < 4; i++) {
1234         if (board->dc2 & (0x10000 << i)) {
1235             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1236                                        0x40030000 + i * 0x1000,
1237                                        pic[timer_irq[i]]);
1238             /* TODO: This is incorrect, but we get away with it because
1239                the ADC output is only ever pulsed.  */
1240             qdev_connect_gpio_out(dev, 0, adc);
1241         }
1242     }
1243
1244     stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
1245
1246     for (i = 0; i < 7; i++) {
1247         if (board->dc4 & (1 << i)) {
1248             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1249                                                pic[gpio_irq[i]]);
1250             for (j = 0; j < 8; j++) {
1251                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1252                 gpio_out[i][j] = NULL;
1253             }
1254         }
1255     }
1256
1257     if (board->dc2 & (1 << 12)) {
1258         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);
1259         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1260         if (board->peripherals & BP_OLED_I2C) {
1261             i2c_create_slave(i2c, "ssd0303", 0x3d);
1262         }
1263     }
1264
1265     for (i = 0; i < 4; i++) {
1266         if (board->dc2 & (1 << i)) {
1267             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1268                                  pic[uart_irq[i]]);
1269         }
1270     }
1271     if (board->dc2 & (1 << 4)) {
1272         dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
1273         if (board->peripherals & BP_OLED_SSI) {
1274             void *bus;
1275             DeviceState *sddev;
1276             DeviceState *ssddev;
1277
1278             /* Some boards have both an OLED controller and SD card connected to
1279              * the same SSI port, with the SD card chip select connected to a
1280              * GPIO pin.  Technically the OLED chip select is connected to the
1281              * SSI Fss pin.  We do not bother emulating that as both devices
1282              * should never be selected simultaneously, and our OLED controller
1283              * ignores stray 0xff commands that occur when deselecting the SD
1284              * card.
1285              */
1286             bus = qdev_get_child_bus(dev, "ssi");
1287
1288             sddev = ssi_create_slave(bus, "ssi-sd");
1289             ssddev = ssi_create_slave(bus, "ssd0323");
1290             gpio_out[GPIO_D][0] = qemu_irq_split(qdev_get_gpio_in(sddev, 0),
1291                                                  qdev_get_gpio_in(ssddev, 0));
1292             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 1);
1293
1294             /* Make sure the select pin is high.  */
1295             qemu_irq_raise(gpio_out[GPIO_D][0]);
1296         }
1297     }
1298     if (board->dc4 & (1 << 28)) {
1299         DeviceState *enet;
1300
1301         qemu_check_nic_model(&nd_table[0], "stellaris");
1302
1303         enet = qdev_create(NULL, "stellaris_enet");
1304         qdev_set_nic_properties(enet, &nd_table[0]);
1305         qdev_init_nofail(enet);
1306         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1307         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]);
1308     }
1309     if (board->peripherals & BP_GAMEPAD) {
1310         qemu_irq gpad_irq[5];
1311         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1312
1313         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1314         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1315         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1316         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1317         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1318
1319         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1320     }
1321     for (i = 0; i < 7; i++) {
1322         if (board->dc4 & (1 << i)) {
1323             for (j = 0; j < 8; j++) {
1324                 if (gpio_out[i][j]) {
1325                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1326                 }
1327             }
1328         }
1329     }
1330 }
1331
1332 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1333 static void lm3s811evb_init(QEMUMachineInitArgs *args)
1334 {
1335     const char *cpu_model = args->cpu_model;
1336     const char *kernel_filename = args->kernel_filename;
1337     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1338 }
1339
1340 static void lm3s6965evb_init(QEMUMachineInitArgs *args)
1341 {
1342     const char *cpu_model = args->cpu_model;
1343     const char *kernel_filename = args->kernel_filename;
1344     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1345 }
1346
1347 static QEMUMachine lm3s811evb_machine = {
1348     .name = "lm3s811evb",
1349     .desc = "Stellaris LM3S811EVB",
1350     .init = lm3s811evb_init,
1351 };
1352
1353 static QEMUMachine lm3s6965evb_machine = {
1354     .name = "lm3s6965evb",
1355     .desc = "Stellaris LM3S6965EVB",
1356     .init = lm3s6965evb_init,
1357 };
1358
1359 static void stellaris_machine_init(void)
1360 {
1361     qemu_register_machine(&lm3s811evb_machine);
1362     qemu_register_machine(&lm3s6965evb_machine);
1363 }
1364
1365 machine_init(stellaris_machine_init);
1366
1367 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1368 {
1369     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1370
1371     sdc->init = stellaris_i2c_init;
1372 }
1373
1374 static const TypeInfo stellaris_i2c_info = {
1375     .name          = TYPE_STELLARIS_I2C,
1376     .parent        = TYPE_SYS_BUS_DEVICE,
1377     .instance_size = sizeof(stellaris_i2c_state),
1378     .class_init    = stellaris_i2c_class_init,
1379 };
1380
1381 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1382 {
1383     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1384
1385     sdc->init = stellaris_gptm_init;
1386 }
1387
1388 static const TypeInfo stellaris_gptm_info = {
1389     .name          = TYPE_STELLARIS_GPTM,
1390     .parent        = TYPE_SYS_BUS_DEVICE,
1391     .instance_size = sizeof(gptm_state),
1392     .class_init    = stellaris_gptm_class_init,
1393 };
1394
1395 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1396 {
1397     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1398
1399     sdc->init = stellaris_adc_init;
1400 }
1401
1402 static const TypeInfo stellaris_adc_info = {
1403     .name          = TYPE_STELLARIS_ADC,
1404     .parent        = TYPE_SYS_BUS_DEVICE,
1405     .instance_size = sizeof(stellaris_adc_state),
1406     .class_init    = stellaris_adc_class_init,
1407 };
1408
1409 static void stellaris_register_types(void)
1410 {
1411     type_register_static(&stellaris_i2c_info);
1412     type_register_static(&stellaris_gptm_info);
1413     type_register_static(&stellaris_adc_info);
1414 }
1415
1416 type_init(stellaris_register_types)