hw/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "sysemu.h"
  27 #include "qemu-timer.h"
  28
  29 #define D(x)
  30
  31 #define R_TCSR     0
  32 #define R_TLR      1
  33 #define R_TCR      2
  34 #define R_MAX      4
  35
  36 #define TCSR_MDT        (1<<0)
  37 #define TCSR_UDT        (1<<1)
  38 #define TCSR_GENT       (1<<2)
  39 #define TCSR_CAPT       (1<<3)
  40 #define TCSR_ARHT       (1<<4)
  41 #define TCSR_LOAD       (1<<5)
  42 #define TCSR_ENIT       (1<<6)
  43 #define TCSR_ENT        (1<<7)
  44 #define TCSR_TINT       (1<<8)
  45 #define TCSR_PWMA       (1<<9)
  46 #define TCSR_ENALL      (1<<10)
  47
  48 struct xlx_timer
  49 {
  50     QEMUBH *bh;
  51     ptimer_state *ptimer;
  52     void *parent;
  53     int nr; /* for debug.  */
  54
  55     unsigned long timer_div;
  56
  57     uint32_t regs[R_MAX];
  58 };
  59
  60 struct timerblock
  61 {
  62     SysBusDevice busdev;
  63     qemu_irq irq;
  64     uint32_t nr_timers;
  65     uint32_t freq_hz;
  66     struct xlx_timer *timers;
  67 };
  68
  69 static inline unsigned int timer_from_addr(target_phys_addr_t addr)
  70 {
  71     /* Timers get a 4x32bit control reg area each.  */
  72     return addr >> 2;
  73 }
  74
  75 static void timer_update_irq(struct timerblock *t)
  76 {
  77     unsigned int i, irq = 0;
  78     uint32_t csr;
  79
  80     for (i = 0; i < t->nr_timers; i++) {
  81         csr = t->timers[i].regs[R_TCSR];
  82         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  83     }
  84
  85     /* All timers within the same slave share a single IRQ line.  */
  86     qemu_set_irq(t->irq, !!irq);
  87 }
  88
  89 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  90 {
  91     struct timerblock *t = opaque;
  92     struct xlx_timer *xt;
  93     uint32_t r = 0;
  94     unsigned int timer;
  95
  96     addr >>= 2;
  97     timer = timer_from_addr(addr);
  98     xt = &t->timers[timer];
  99     /* Further decoding to address a specific timers reg.  */
 100     addr &= 0x3;
 101     switch (addr)
 102     {
 103         case R_TCR:
 104                 r = ptimer_get_count(xt->ptimer);
 105                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 106                     r = ~r;
 107                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 108                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 109             break;
 110         default:
 111             if (addr < ARRAY_SIZE(xt->regs))
 112                 r = xt->regs[addr];
 113             break;
 114
 115     }
 116     D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 117     return r;
 118 }
 119
 120 static void timer_enable(struct xlx_timer *xt)
 121 {
 122     uint64_t count;
 123
 124     D(printf("%s timer=%d down=%d\n", __func__,
 125               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 126
 127     ptimer_stop(xt->ptimer);
 128
 129     if (xt->regs[R_TCSR] & TCSR_UDT)
 130         count = xt->regs[R_TLR];
 131     else
 132         count = ~0 - xt->regs[R_TLR];
 133     ptimer_set_count(xt->ptimer, count);
 134     ptimer_run(xt->ptimer, 1);
 135 }
 136
 137 static void
 138 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 139 {
 140     struct timerblock *t = opaque;
 141     struct xlx_timer *xt;
 142     unsigned int timer;
 143
 144     addr >>= 2;
 145     timer = timer_from_addr(addr);
 146     xt = &t->timers[timer];
 147     D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
 148              __func__, addr * 4, value, timer, addr & 3));
 149     /* Further decoding to address a specific timers reg.  */
 150     addr &= 3;
 151     switch (addr)
 152     {
 153         case R_TCSR:
 154             if (value & TCSR_TINT)
 155                 value &= ~TCSR_TINT;
 156
 157             xt->regs[addr] = value;
 158             if (value & TCSR_ENT)
 159                 timer_enable(xt);
 160             break;
 161
 162         default:
 163             if (addr < ARRAY_SIZE(xt->regs))
 164                 xt->regs[addr] = value;
 165             break;
 166     }
 167     timer_update_irq(t);
 168 }
 169
 170 static CPUReadMemoryFunc * const timer_read[] = {
 171     NULL, NULL,
 172     &timer_readl,
 173 };
 174
 175 static CPUWriteMemoryFunc * const timer_write[] = {
 176     NULL, NULL,
 177     &timer_writel,
 178 };
 179
 180 static void timer_hit(void *opaque)
 181 {
 182     struct xlx_timer *xt = opaque;
 183     struct timerblock *t = xt->parent;
 184     D(printf("%s %d\n", __func__, timer));
 185     xt->regs[R_TCSR] |= TCSR_TINT;
 186
 187     if (xt->regs[R_TCSR] & TCSR_ARHT)
 188         timer_enable(xt);
 189     timer_update_irq(t);
 190 }
 191
 192 static int xilinx_timer_init(SysBusDevice *dev)
 193 {
 194     struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
 195     unsigned int i;
 196     int timer_regs;
 197
 198     /* All timers share a single irq line.  */
 199     sysbus_init_irq(dev, &t->irq);
 200
 201     /* Init all the ptimers.  */
 202     t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
 203     for (i = 0; i < t->nr_timers; i++) {
 204         struct xlx_timer *xt = &t->timers[i];
 205
 206         xt->parent = t;
 207         xt->nr = i;
 208         xt->bh = qemu_bh_new(timer_hit, xt);
 209         xt->ptimer = ptimer_init(xt->bh);
 210         ptimer_set_freq(xt->ptimer, t->freq_hz);
 211     }
 212
 213     timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
 214                                         DEVICE_NATIVE_ENDIAN);
 215     sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
 216     return 0;
 217 }
 218
 219 static SysBusDeviceInfo xilinx_timer_info = {
 220     .init = xilinx_timer_init,
 221     .qdev.name  = "xilinx,timer",
 222     .qdev.size  = sizeof(struct timerblock),
 223     .qdev.props = (Property[]) {
 224         DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
 225         DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
 226         DEFINE_PROP_END_OF_LIST(),
 227     }
 228 };
 229
 230 static void xilinx_timer_register(void)
 231 {
 232     sysbus_register_withprop(&xilinx_timer_info);
 233 }
 234
 235 device_init(xilinx_timer_register)