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pc: acpi: drop manual hole punching for CPU hotplug resources
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob0de261a536525e94b1f9d9b0977fe040ce4156d5
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
32 #include "qom/cpu.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 typedef struct AcpiCpuInfo {
85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
86 } AcpiCpuInfo;
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t cpu_hp_io_len;
106 uint16_t mem_hp_io_base;
107 uint16_t mem_hp_io_len;
108 uint16_t pcihp_io_base;
109 uint16_t pcihp_io_len;
110 } AcpiPmInfo;
111
112 typedef struct AcpiMiscInfo {
113 bool has_hpet;
114 bool has_tpm;
115 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
116 const unsigned char *dsdt_code;
117 unsigned dsdt_size;
118 uint16_t pvpanic_port;
119 } AcpiMiscInfo;
120
121 typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
125 bool pcihp_bridge_en;
126 } AcpiBuildPciBusHotplugState;
127
128 static void acpi_get_dsdt(AcpiMiscInfo *info)
129 {
130 uint16_t *applesmc_sta;
131 Object *piix = piix4_pm_find();
132 Object *lpc = ich9_lpc_find();
133 assert(!!piix != !!lpc);
134
135 if (piix) {
136 info->dsdt_code = AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof AcpiDsdtAmlCode;
138 applesmc_sta = piix_dsdt_applesmc_sta;
139 }
140 if (lpc) {
141 info->dsdt_code = Q35AcpiDsdtAmlCode;
142 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
143 applesmc_sta = q35_dsdt_applesmc_sta;
144 }
145
146 /* Patch in appropriate value for AppleSMC _STA */
147 *(uint8_t *)(info->dsdt_code + *applesmc_sta) =
148 applesmc_find() ? 0x0b : 0x00;
149 }
150
151 static
152 int acpi_add_cpu_info(Object *o, void *opaque)
153 {
154 AcpiCpuInfo *cpu = opaque;
155 uint64_t apic_id;
156
157 if (object_dynamic_cast(o, TYPE_CPU)) {
158 apic_id = object_property_get_int(o, "apic-id", NULL);
159 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
160
161 set_bit(apic_id, cpu->found_cpus);
162 }
163
164 object_child_foreach(o, acpi_add_cpu_info, opaque);
165 return 0;
166 }
167
168 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
169 {
170 Object *root = object_get_root();
171
172 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
173 object_child_foreach(root, acpi_add_cpu_info, cpu);
174 }
175
176 static void acpi_get_pm_info(AcpiPmInfo *pm)
177 {
178 Object *piix = piix4_pm_find();
179 Object *lpc = ich9_lpc_find();
180 Object *obj = NULL;
181 QObject *o;
182
183 pm->pcihp_io_base = 0;
184 pm->pcihp_io_len = 0;
185 if (piix) {
186 obj = piix;
187 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
188 pm->pcihp_io_base =
189 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
190 pm->pcihp_io_len =
191 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
192 }
193 if (lpc) {
194 obj = lpc;
195 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
196 }
197 assert(obj);
198
199 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
200 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
201 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
202
203 /* Fill in optional s3/s4 related properties */
204 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
205 if (o) {
206 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
207 } else {
208 pm->s3_disabled = false;
209 }
210 qobject_decref(o);
211 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
212 if (o) {
213 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
214 } else {
215 pm->s4_disabled = false;
216 }
217 qobject_decref(o);
218 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
219 if (o) {
220 pm->s4_val = qint_get_int(qobject_to_qint(o));
221 } else {
222 pm->s4_val = false;
223 }
224 qobject_decref(o);
225
226 /* Fill in mandatory properties */
227 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
228
229 pm->acpi_enable_cmd = object_property_get_int(obj,
230 ACPI_PM_PROP_ACPI_ENABLE_CMD,
231 NULL);
232 pm->acpi_disable_cmd = object_property_get_int(obj,
233 ACPI_PM_PROP_ACPI_DISABLE_CMD,
234 NULL);
235 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
236 NULL);
237 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
238 NULL);
239 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
240 NULL);
241 pm->pcihp_bridge_en =
242 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
243 NULL);
244 }
245
246 static void acpi_get_misc_info(AcpiMiscInfo *info)
247 {
248 info->has_hpet = hpet_find();
249 info->has_tpm = tpm_find();
250 info->pvpanic_port = pvpanic_port();
251 }
252
253 static void acpi_get_pci_info(PcPciInfo *info)
254 {
255 Object *pci_host;
256 bool ambiguous;
257
258 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
259 g_assert(!ambiguous);
260 g_assert(pci_host);
261
262 info->w32.begin = object_property_get_int(pci_host,
263 PCI_HOST_PROP_PCI_HOLE_START,
264 NULL);
265 info->w32.end = object_property_get_int(pci_host,
266 PCI_HOST_PROP_PCI_HOLE_END,
267 NULL);
268 info->w64.begin = object_property_get_int(pci_host,
269 PCI_HOST_PROP_PCI_HOLE64_START,
270 NULL);
271 info->w64.end = object_property_get_int(pci_host,
272 PCI_HOST_PROP_PCI_HOLE64_END,
273 NULL);
274 }
275
276 #define ACPI_BUILD_APPNAME "Bochs"
277 #define ACPI_BUILD_APPNAME6 "BOCHS "
278 #define ACPI_BUILD_APPNAME4 "BXPC"
279
280 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
281 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
282 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
283
284 static void
285 build_header(GArray *linker, GArray *table_data,
286 AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
287 {
288 memcpy(&h->signature, sig, 4);
289 h->length = cpu_to_le32(len);
290 h->revision = rev;
291 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
292 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
293 memcpy(h->oem_table_id + 4, sig, 4);
294 h->oem_revision = cpu_to_le32(1);
295 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
296 h->asl_compiler_revision = cpu_to_le32(1);
297 h->checksum = 0;
298 /* Checksum to be filled in by Guest linker */
299 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
300 table_data->data, h, len, &h->checksum);
301 }
302
303 static GArray *build_alloc_method(const char *name, uint8_t arg_count)
304 {
305 GArray *method = build_alloc_array();
306
307 build_append_namestring(method, "%s", name);
308 build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
309
310 return method;
311 }
312
313 static void build_append_and_cleanup_method(GArray *device, GArray *method)
314 {
315 uint8_t op = 0x14; /* MethodOp */
316
317 build_package(method, op);
318
319 build_append_array(device, method);
320 build_free_array(method);
321 }
322
323 /* End here */
324 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
325
326 static inline void *acpi_data_push(GArray *table_data, unsigned size)
327 {
328 unsigned off = table_data->len;
329 g_array_set_size(table_data, off + size);
330 return table_data->data + off;
331 }
332
333 static unsigned acpi_data_len(GArray *table)
334 {
335 #if GLIB_CHECK_VERSION(2, 22, 0)
336 assert(g_array_get_element_size(table) == 1);
337 #endif
338 return table->len;
339 }
340
341 static void acpi_align_size(GArray *blob, unsigned align)
342 {
343 /* Align size to multiple of given size. This reduces the chance
344 * we need to change size in the future (breaking cross version migration).
345 */
346 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
347 }
348
349 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
350 {
351 uint32_t offset = cpu_to_le32(table_data->len);
352 g_array_append_val(table_offsets, offset);
353 }
354
355 /* FACS */
356 static void
357 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
358 {
359 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
360 memcpy(&facs->signature, "FACS", 4);
361 facs->length = cpu_to_le32(sizeof(*facs));
362 }
363
364 /* Load chipset information in FADT */
365 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
366 {
367 fadt->model = 1;
368 fadt->reserved1 = 0;
369 fadt->sci_int = cpu_to_le16(pm->sci_int);
370 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
371 fadt->acpi_enable = pm->acpi_enable_cmd;
372 fadt->acpi_disable = pm->acpi_disable_cmd;
373 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
374 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
375 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
376 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
377 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
378 /* EVT, CNT, TMR length matches hw/acpi/core.c */
379 fadt->pm1_evt_len = 4;
380 fadt->pm1_cnt_len = 2;
381 fadt->pm_tmr_len = 4;
382 fadt->gpe0_blk_len = pm->gpe0_blk_len;
383 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
384 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
385 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
386 (1 << ACPI_FADT_F_PROC_C1) |
387 (1 << ACPI_FADT_F_SLP_BUTTON) |
388 (1 << ACPI_FADT_F_RTC_S4));
389 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
390 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
391 * For more than 8 CPUs, "Clustered Logical" mode has to be used
392 */
393 if (max_cpus > 8) {
394 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
395 }
396 }
397
398
399 /* FADT */
400 static void
401 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
402 unsigned facs, unsigned dsdt)
403 {
404 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
405
406 fadt->firmware_ctrl = cpu_to_le32(facs);
407 /* FACS address to be filled by Guest linker */
408 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
409 ACPI_BUILD_TABLE_FILE,
410 table_data, &fadt->firmware_ctrl,
411 sizeof fadt->firmware_ctrl);
412
413 fadt->dsdt = cpu_to_le32(dsdt);
414 /* DSDT address to be filled by Guest linker */
415 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
416 ACPI_BUILD_TABLE_FILE,
417 table_data, &fadt->dsdt,
418 sizeof fadt->dsdt);
419
420 fadt_setup(fadt, pm);
421
422 build_header(linker, table_data,
423 (void *)fadt, "FACP", sizeof(*fadt), 1);
424 }
425
426 static void
427 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
428 PcGuestInfo *guest_info)
429 {
430 int madt_start = table_data->len;
431
432 AcpiMultipleApicTable *madt;
433 AcpiMadtIoApic *io_apic;
434 AcpiMadtIntsrcovr *intsrcovr;
435 AcpiMadtLocalNmi *local_nmi;
436 int i;
437
438 madt = acpi_data_push(table_data, sizeof *madt);
439 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
440 madt->flags = cpu_to_le32(1);
441
442 for (i = 0; i < guest_info->apic_id_limit; i++) {
443 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
444 apic->type = ACPI_APIC_PROCESSOR;
445 apic->length = sizeof(*apic);
446 apic->processor_id = i;
447 apic->local_apic_id = i;
448 if (test_bit(i, cpu->found_cpus)) {
449 apic->flags = cpu_to_le32(1);
450 } else {
451 apic->flags = cpu_to_le32(0);
452 }
453 }
454 io_apic = acpi_data_push(table_data, sizeof *io_apic);
455 io_apic->type = ACPI_APIC_IO;
456 io_apic->length = sizeof(*io_apic);
457 #define ACPI_BUILD_IOAPIC_ID 0x0
458 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
459 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
460 io_apic->interrupt = cpu_to_le32(0);
461
462 if (guest_info->apic_xrupt_override) {
463 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
464 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
465 intsrcovr->length = sizeof(*intsrcovr);
466 intsrcovr->source = 0;
467 intsrcovr->gsi = cpu_to_le32(2);
468 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
469 }
470 for (i = 1; i < 16; i++) {
471 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
472 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
473 /* No need for a INT source override structure. */
474 continue;
475 }
476 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
477 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
478 intsrcovr->length = sizeof(*intsrcovr);
479 intsrcovr->source = i;
480 intsrcovr->gsi = cpu_to_le32(i);
481 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
482 }
483
484 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
485 local_nmi->type = ACPI_APIC_LOCAL_NMI;
486 local_nmi->length = sizeof(*local_nmi);
487 local_nmi->processor_id = 0xff; /* all processors */
488 local_nmi->flags = cpu_to_le16(0);
489 local_nmi->lint = 1; /* ACPI_LINT1 */
490
491 build_header(linker, table_data,
492 (void *)(table_data->data + madt_start), "APIC",
493 table_data->len - madt_start, 1);
494 }
495
496 /* Encode a hex value */
497 static inline char acpi_get_hex(uint32_t val)
498 {
499 val &= 0x0f;
500 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
501 }
502
503 /* 0x5B 0x82 DeviceOp PkgLength NameString */
504 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
505 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
506 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
507 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
508 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
509 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
510
511 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
512 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
513 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
514 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
515
516 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
517 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
518 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
519 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
520
521 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
522 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
523 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
524 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
525
526 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
527 #define ACPI_SSDT_HEADER_LENGTH 36
528
529 #include "hw/i386/ssdt-misc.hex"
530 #include "hw/i386/ssdt-pcihp.hex"
531 #include "hw/i386/ssdt-tpm.hex"
532
533 static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
534 {
535 unsigned devfn = PCI_DEVFN(slot, 0);
536
537 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
538 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
539 ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
540 ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
541 }
542
543 static void patch_pcinohp(int slot, uint8_t *ssdt_ptr)
544 {
545 unsigned devfn = PCI_DEVFN(slot, 0);
546
547 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
548 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
549 ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot;
550 }
551
552 static void patch_pcivga(int slot, uint8_t *ssdt_ptr)
553 {
554 unsigned devfn = PCI_DEVFN(slot, 0);
555
556 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
557 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn);
558 ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot;
559 }
560
561 static void patch_pciqxl(int slot, uint8_t *ssdt_ptr)
562 {
563 unsigned devfn = PCI_DEVFN(slot, 0);
564
565 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
566 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn);
567 ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot;
568 }
569
570 /* Assign BSEL property to all buses. In the future, this can be changed
571 * to only assign to buses that support hotplug.
572 */
573 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
574 {
575 unsigned *bsel_alloc = opaque;
576 unsigned *bus_bsel;
577
578 if (qbus_is_hotpluggable(BUS(bus))) {
579 bus_bsel = g_malloc(sizeof *bus_bsel);
580
581 *bus_bsel = (*bsel_alloc)++;
582 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
583 bus_bsel, NULL);
584 }
585
586 return bsel_alloc;
587 }
588
589 static void acpi_set_pci_info(void)
590 {
591 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
592 unsigned bsel_alloc = 0;
593
594 if (bus) {
595 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
596 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
597 }
598 }
599
600 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
601 AcpiBuildPciBusHotplugState *parent,
602 bool pcihp_bridge_en)
603 {
604 state->parent = parent;
605 state->device_table = build_alloc_array();
606 state->notify_table = build_alloc_array();
607 state->pcihp_bridge_en = pcihp_bridge_en;
608 }
609
610 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
611 {
612 build_free_array(state->device_table);
613 build_free_array(state->notify_table);
614 }
615
616 static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
617 {
618 AcpiBuildPciBusHotplugState *parent = parent_state;
619 AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
620
621 build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en);
622
623 return child;
624 }
625
626 static void build_pci_bus_end(PCIBus *bus, void *bus_state)
627 {
628 AcpiBuildPciBusHotplugState *child = bus_state;
629 AcpiBuildPciBusHotplugState *parent = child->parent;
630 GArray *bus_table = build_alloc_array();
631 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
632 DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX);
633 DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX);
634 DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX);
635 DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX);
636 uint8_t op;
637 int i;
638 QObject *bsel;
639 GArray *method;
640 bool bus_hotplug_support = false;
641
642 /*
643 * Skip bridge subtree creation if bridge hotplug is disabled
644 * to make acpi tables compatible with legacy machine types.
645 * Skip creation for hotplugged bridges as well.
646 */
647 if (bus->parent_dev && (!child->pcihp_bridge_en ||
648 DEVICE(bus->parent_dev)->hotplugged)) {
649 build_free_array(bus_table);
650 build_pci_bus_state_cleanup(child);
651 g_free(child);
652 return;
653 }
654
655 if (bus->parent_dev) {
656 op = 0x82; /* DeviceOp */
657 build_append_namestring(bus_table, "S%.02X",
658 bus->parent_dev->devfn);
659 build_append_byte(bus_table, 0x08); /* NameOp */
660 build_append_namestring(bus_table, "_SUN");
661 build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn));
662 build_append_byte(bus_table, 0x08); /* NameOp */
663 build_append_namestring(bus_table, "_ADR");
664 build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
665 PCI_FUNC(bus->parent_dev->devfn));
666 } else {
667 op = 0x10; /* ScopeOp */;
668 build_append_namestring(bus_table, "PCI0");
669 }
670
671 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
672 if (bsel) {
673 build_append_byte(bus_table, 0x08); /* NameOp */
674 build_append_namestring(bus_table, "BSEL");
675 build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
676 memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
677 } else {
678 /* No bsel - no slots are hot-pluggable */
679 memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable);
680 }
681
682 memset(slot_device_present, 0x00, sizeof slot_device_present);
683 memset(slot_device_system, 0x00, sizeof slot_device_present);
684 memset(slot_device_vga, 0x00, sizeof slot_device_vga);
685 memset(slot_device_qxl, 0x00, sizeof slot_device_qxl);
686
687 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
688 DeviceClass *dc;
689 PCIDeviceClass *pc;
690 PCIDevice *pdev = bus->devices[i];
691 int slot = PCI_SLOT(i);
692 bool bridge_in_acpi;
693
694 if (!pdev) {
695 continue;
696 }
697
698 set_bit(slot, slot_device_present);
699 pc = PCI_DEVICE_GET_CLASS(pdev);
700 dc = DEVICE_GET_CLASS(pdev);
701
702 /* When hotplug for bridges is enabled, bridges are
703 * described in ACPI separately (see build_pci_bus_end).
704 * In this case they aren't themselves hot-pluggable.
705 * Hotplugged bridges *are* hot-pluggable.
706 */
707 bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en &&
708 !DEVICE(pdev)->hotplugged;
709
710 if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) {
711 set_bit(slot, slot_device_system);
712 }
713
714 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
715 set_bit(slot, slot_device_vga);
716
717 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
718 set_bit(slot, slot_device_qxl);
719 }
720 }
721
722 if (!dc->hotpluggable || bridge_in_acpi) {
723 clear_bit(slot, slot_hotplug_enable);
724 }
725 }
726
727 /* Append Device object for each slot */
728 for (i = 0; i < PCI_SLOT_MAX; i++) {
729 bool can_eject = test_bit(i, slot_hotplug_enable);
730 bool present = test_bit(i, slot_device_present);
731 bool vga = test_bit(i, slot_device_vga);
732 bool qxl = test_bit(i, slot_device_qxl);
733 bool system = test_bit(i, slot_device_system);
734 if (can_eject) {
735 void *pcihp = acpi_data_push(bus_table,
736 ACPI_PCIHP_SIZEOF);
737 memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
738 patch_pcihp(i, pcihp);
739 bus_hotplug_support = true;
740 } else if (qxl) {
741 void *pcihp = acpi_data_push(bus_table,
742 ACPI_PCIQXL_SIZEOF);
743 memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF);
744 patch_pciqxl(i, pcihp);
745 } else if (vga) {
746 void *pcihp = acpi_data_push(bus_table,
747 ACPI_PCIVGA_SIZEOF);
748 memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF);
749 patch_pcivga(i, pcihp);
750 } else if (system) {
751 /* Nothing to do: system devices are in DSDT or in SSDT above. */
752 } else if (present) {
753 void *pcihp = acpi_data_push(bus_table,
754 ACPI_PCINOHP_SIZEOF);
755 memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF);
756 patch_pcinohp(i, pcihp);
757 }
758 }
759
760 if (bsel) {
761 method = build_alloc_method("DVNT", 2);
762
763 for (i = 0; i < PCI_SLOT_MAX; i++) {
764 GArray *notify;
765 uint8_t op;
766
767 if (!test_bit(i, slot_hotplug_enable)) {
768 continue;
769 }
770
771 notify = build_alloc_array();
772 op = 0xA0; /* IfOp */
773
774 build_append_byte(notify, 0x7B); /* AndOp */
775 build_append_byte(notify, 0x68); /* Arg0Op */
776 build_append_int(notify, 0x1U << i);
777 build_append_byte(notify, 0x00); /* NullName */
778 build_append_byte(notify, 0x86); /* NotifyOp */
779 build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0));
780 build_append_byte(notify, 0x69); /* Arg1Op */
781
782 /* Pack it up */
783 build_package(notify, op);
784
785 build_append_array(method, notify);
786
787 build_free_array(notify);
788 }
789
790 build_append_and_cleanup_method(bus_table, method);
791 }
792
793 /* Append PCNT method to notify about events on local and child buses.
794 * Add unconditionally for root since DSDT expects it.
795 */
796 if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
797 method = build_alloc_method("PCNT", 0);
798
799 /* If bus supports hotplug select it and notify about local events */
800 if (bsel) {
801 build_append_byte(method, 0x70); /* StoreOp */
802 build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
803 build_append_namestring(method, "BNUM");
804 build_append_namestring(method, "DVNT");
805 build_append_namestring(method, "PCIU");
806 build_append_int(method, 1); /* Device Check */
807 build_append_namestring(method, "DVNT");
808 build_append_namestring(method, "PCID");
809 build_append_int(method, 3); /* Eject Request */
810 }
811
812 /* Notify about child bus events in any case */
813 build_append_array(method, child->notify_table);
814
815 build_append_and_cleanup_method(bus_table, method);
816
817 /* Append description of child buses */
818 build_append_array(bus_table, child->device_table);
819
820 /* Pack it up */
821 if (bus->parent_dev) {
822 build_extop_package(bus_table, op);
823 } else {
824 build_package(bus_table, op);
825 }
826
827 /* Append our bus description to parent table */
828 build_append_array(parent->device_table, bus_table);
829
830 /* Also tell parent how to notify us, invoking PCNT method.
831 * At the moment this is not needed for root as we have a single root.
832 */
833 if (bus->parent_dev) {
834 build_append_namestring(parent->notify_table, "^PCNT.S%.02X",
835 bus->parent_dev->devfn);
836 }
837 }
838
839 qobject_decref(bsel);
840 build_free_array(bus_table);
841 build_pci_bus_state_cleanup(child);
842 g_free(child);
843 }
844
845 static void
846 build_ssdt(GArray *table_data, GArray *linker,
847 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
848 PcPciInfo *pci, PcGuestInfo *guest_info)
849 {
850 MachineState *machine = MACHINE(qdev_get_machine());
851 uint32_t nr_mem = machine->ram_slots;
852 unsigned acpi_cpus = guest_info->apic_id_limit;
853 uint8_t *ssdt_ptr;
854 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
855 int i;
856
857 ssdt = init_aml_allocator();
858 /* The current AML generator can cover the APIC ID range [0..255],
859 * inclusive, for VCPU hotplug. */
860 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
861 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
862
863 /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
864 ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml));
865 memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
866
867 scope = aml_scope("\\_SB.PCI0");
868 /* build PCI0._CRS */
869 crs = aml_resource_template();
870 aml_append(crs,
871 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
872 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
873 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
874
875 aml_append(crs,
876 aml_word_io(aml_min_fixed, aml_max_fixed,
877 aml_pos_decode, aml_entire_range,
878 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
879 if (ich9_lpc_find()) { /* Q35 */
880 aml_append(crs,
881 aml_word_io(aml_min_fixed, aml_max_fixed,
882 aml_pos_decode, aml_entire_range,
883 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
884 } else { /* piix4 */
885 aml_append(crs,
886 aml_word_io(aml_min_fixed, aml_max_fixed,
887 aml_pos_decode, aml_entire_range,
888 0x0000, 0x0D00, 0xAFDF, 0x0000, 0xA2E0));
889 aml_append(crs,
890 aml_word_io(aml_min_fixed, aml_max_fixed,
891 aml_pos_decode, aml_entire_range,
892 0x0000, 0xAFE4, 0xFFFF, 0x0000, 0x501C));
893 }
894 aml_append(crs,
895 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
896 aml_cacheable, aml_ReadWrite,
897 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
898 aml_append(crs,
899 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
900 aml_non_cacheable, aml_ReadWrite,
901 0, pci->w32.begin, pci->w32.end - 1, 0,
902 pci->w32.end - pci->w32.begin));
903 if (pci->w64.begin) {
904 aml_append(crs,
905 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
906 aml_cacheable, aml_ReadWrite,
907 0, pci->w64.begin, pci->w64.end - 1, 0,
908 pci->w64.end - pci->w64.begin));
909 }
910 aml_append(scope, aml_name_decl("_CRS", crs));
911
912 /* reserve PCIHP resources */
913 if (pm->pcihp_io_len) {
914 dev = aml_device("PHPR");
915 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
916 aml_append(dev,
917 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
918 /* device present, functioning, decoding, not shown in UI */
919 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
920 crs = aml_resource_template();
921 aml_append(crs,
922 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
923 pm->pcihp_io_len)
924 );
925 aml_append(dev, aml_name_decl("_CRS", crs));
926 aml_append(scope, dev);
927 }
928 aml_append(ssdt, scope);
929
930 /* create S3_ / S4_ / S5_ packages if necessary */
931 scope = aml_scope("\\");
932 if (!pm->s3_disabled) {
933 pkg = aml_package(4);
934 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
935 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
936 aml_append(pkg, aml_int(0)); /* reserved */
937 aml_append(pkg, aml_int(0)); /* reserved */
938 aml_append(scope, aml_name_decl("_S3", pkg));
939 }
940
941 if (!pm->s4_disabled) {
942 pkg = aml_package(4);
943 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
944 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
945 aml_append(pkg, aml_int(pm->s4_val));
946 aml_append(pkg, aml_int(0)); /* reserved */
947 aml_append(pkg, aml_int(0)); /* reserved */
948 aml_append(scope, aml_name_decl("_S4", pkg));
949 }
950
951 pkg = aml_package(4);
952 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
953 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
954 aml_append(pkg, aml_int(0)); /* reserved */
955 aml_append(pkg, aml_int(0)); /* reserved */
956 aml_append(scope, aml_name_decl("_S5", pkg));
957 aml_append(ssdt, scope);
958
959 if (misc->pvpanic_port) {
960 scope = aml_scope("\\_SB.PCI0.ISA");
961
962 dev = aml_device("PEVR");
963 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
964
965 crs = aml_resource_template();
966 aml_append(crs,
967 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
968 );
969 aml_append(dev, aml_name_decl("_CRS", crs));
970
971 aml_append(dev, aml_operation_region("PEOR", aml_system_io,
972 misc->pvpanic_port, 1));
973 field = aml_field("PEOR", aml_byte_acc);
974 aml_append(field, aml_named_field("PEPT", 8));
975 aml_append(dev, field);
976
977 method = aml_method("RDPT", 0);
978 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
979 aml_append(method, aml_return(aml_local(0)));
980 aml_append(dev, method);
981
982 method = aml_method("WRPT", 1);
983 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
984 aml_append(dev, method);
985
986 aml_append(scope, dev);
987 aml_append(ssdt, scope);
988 }
989
990 sb_scope = aml_scope("_SB");
991 {
992 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
993 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
994 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
995 aml_append(dev,
996 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
997 );
998 /* device present, functioning, decoding, not shown in UI */
999 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1000 crs = aml_resource_template();
1001 aml_append(crs,
1002 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1003 pm->cpu_hp_io_len)
1004 );
1005 aml_append(dev, aml_name_decl("_CRS", crs));
1006 aml_append(sb_scope, dev);
1007 /* declare CPU hotplug MMIO region and PRS field to access it */
1008 aml_append(sb_scope, aml_operation_region(
1009 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1010 field = aml_field("PRST", aml_byte_acc);
1011 aml_append(field, aml_named_field("PRS", 256));
1012 aml_append(sb_scope, field);
1013
1014 /* build Processor object for each processor */
1015 for (i = 0; i < acpi_cpus; i++) {
1016 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1017
1018 method = aml_method("_MAT", 0);
1019 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1020 aml_append(dev, method);
1021
1022 method = aml_method("_STA", 0);
1023 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1024 aml_append(dev, method);
1025
1026 method = aml_method("_EJ0", 1);
1027 aml_append(method,
1028 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1029 );
1030 aml_append(dev, method);
1031
1032 aml_append(sb_scope, dev);
1033 }
1034
1035 /* build this code:
1036 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1037 */
1038 /* Arg0 = Processor ID = APIC ID */
1039 method = aml_method("NTFY", 2);
1040 for (i = 0; i < acpi_cpus; i++) {
1041 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1042 aml_append(ifctx,
1043 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1044 );
1045 aml_append(method, ifctx);
1046 }
1047 aml_append(sb_scope, method);
1048
1049 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1050 *
1051 * Note: The ability to create variable-sized packages was first
1052 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1053 * ith up to 255 elements. Windows guests up to win2k8 fail when
1054 * VarPackageOp is used.
1055 */
1056 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1057 aml_varpackage(acpi_cpus);
1058
1059 for (i = 0; i < acpi_cpus; i++) {
1060 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1061 aml_append(pkg, aml_int(b));
1062 }
1063 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1064
1065 /* build memory devices */
1066 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1067 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1068 aml_append(scope,
1069 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1070 );
1071
1072 crs = aml_resource_template();
1073 aml_append(crs,
1074 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1075 pm->mem_hp_io_len)
1076 );
1077 aml_append(scope, aml_name_decl("_CRS", crs));
1078
1079 aml_append(scope, aml_operation_region(
1080 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
1081 pm->mem_hp_io_base, pm->mem_hp_io_len)
1082 );
1083
1084 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1085 aml_append(field, /* read only */
1086 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1087 aml_append(field, /* read only */
1088 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1089 aml_append(field, /* read only */
1090 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1091 aml_append(field, /* read only */
1092 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1093 aml_append(field, /* read only */
1094 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1095 aml_append(scope, field);
1096
1097 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc);
1098 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1099 aml_append(field, /* 1 if enabled, read only */
1100 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1101 aml_append(field,
1102 /*(read) 1 if has a insert event. (write) 1 to clear event */
1103 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1104 aml_append(scope, field);
1105
1106 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1107 aml_append(field, /* DIMM selector, write only */
1108 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1109 aml_append(field, /* _OST event code, write only */
1110 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1111 aml_append(field, /* _OST status code, write only */
1112 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1113 aml_append(scope, field);
1114
1115 aml_append(sb_scope, scope);
1116
1117 for (i = 0; i < nr_mem; i++) {
1118 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1119 const char *s;
1120
1121 dev = aml_device("MP%02X", i);
1122 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1123 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1124
1125 method = aml_method("_CRS", 0);
1126 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1127 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1128 aml_append(dev, method);
1129
1130 method = aml_method("_STA", 0);
1131 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1132 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1133 aml_append(dev, method);
1134
1135 method = aml_method("_PXM", 0);
1136 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1137 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1138 aml_append(dev, method);
1139
1140 method = aml_method("_OST", 3);
1141 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1142 aml_append(method, aml_return(aml_call4(
1143 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1144 )));
1145 aml_append(dev, method);
1146
1147 aml_append(sb_scope, dev);
1148 }
1149
1150 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1151 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1152 */
1153 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1154 for (i = 0; i < nr_mem; i++) {
1155 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1156 aml_append(ifctx,
1157 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1158 );
1159 aml_append(method, ifctx);
1160 }
1161 aml_append(sb_scope, method);
1162
1163 {
1164 AcpiBuildPciBusHotplugState hotplug_state;
1165 Object *pci_host;
1166 PCIBus *bus = NULL;
1167 bool ambiguous;
1168
1169 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1170 if (!ambiguous && pci_host) {
1171 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1172 }
1173
1174 build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en);
1175
1176 if (bus) {
1177 /* Scan all PCI buses. Generate tables to support hotplug. */
1178 pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
1179 build_pci_bus_end, &hotplug_state);
1180 }
1181
1182 build_append_array(sb_scope->buf, hotplug_state.device_table);
1183 build_pci_bus_state_cleanup(&hotplug_state);
1184 }
1185 aml_append(ssdt, sb_scope);
1186 }
1187
1188 /* copy AML table into ACPI tables blob and patch header there */
1189 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1190 build_header(linker, table_data,
1191 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1192 "SSDT", ssdt->buf->len, 1);
1193 free_aml_allocator();
1194 }
1195
1196 static void
1197 build_hpet(GArray *table_data, GArray *linker)
1198 {
1199 Acpi20Hpet *hpet;
1200
1201 hpet = acpi_data_push(table_data, sizeof(*hpet));
1202 /* Note timer_block_id value must be kept in sync with value advertised by
1203 * emulated hpet
1204 */
1205 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1206 hpet->addr.address = cpu_to_le64(HPET_BASE);
1207 build_header(linker, table_data,
1208 (void *)hpet, "HPET", sizeof(*hpet), 1);
1209 }
1210
1211 static void
1212 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1213 {
1214 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1215 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1216
1217 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1218 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1219 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1220
1221 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1222 false /* high memory */);
1223
1224 /* log area start address to be filled by Guest linker */
1225 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1226 ACPI_BUILD_TPMLOG_FILE,
1227 table_data, &tcpa->log_area_start_address,
1228 sizeof(tcpa->log_area_start_address));
1229
1230 build_header(linker, table_data,
1231 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1232
1233 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1234 }
1235
1236 static void
1237 build_tpm_ssdt(GArray *table_data, GArray *linker)
1238 {
1239 void *tpm_ptr;
1240
1241 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml));
1242 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml));
1243 }
1244
1245 typedef enum {
1246 MEM_AFFINITY_NOFLAGS = 0,
1247 MEM_AFFINITY_ENABLED = (1 << 0),
1248 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1249 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1250 } MemoryAffinityFlags;
1251
1252 static void
1253 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1254 uint64_t len, int node, MemoryAffinityFlags flags)
1255 {
1256 numamem->type = ACPI_SRAT_MEMORY;
1257 numamem->length = sizeof(*numamem);
1258 memset(numamem->proximity, 0, 4);
1259 numamem->proximity[0] = node;
1260 numamem->flags = cpu_to_le32(flags);
1261 numamem->base_addr = cpu_to_le64(base);
1262 numamem->range_length = cpu_to_le64(len);
1263 }
1264
1265 static void
1266 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1267 {
1268 AcpiSystemResourceAffinityTable *srat;
1269 AcpiSratProcessorAffinity *core;
1270 AcpiSratMemoryAffinity *numamem;
1271
1272 int i;
1273 uint64_t curnode;
1274 int srat_start, numa_start, slots;
1275 uint64_t mem_len, mem_base, next_base;
1276 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1277 ram_addr_t hotplugabble_address_space_size =
1278 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1279 NULL);
1280
1281 srat_start = table_data->len;
1282
1283 srat = acpi_data_push(table_data, sizeof *srat);
1284 srat->reserved1 = cpu_to_le32(1);
1285 core = (void *)(srat + 1);
1286
1287 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1288 core = acpi_data_push(table_data, sizeof *core);
1289 core->type = ACPI_SRAT_PROCESSOR;
1290 core->length = sizeof(*core);
1291 core->local_apic_id = i;
1292 curnode = guest_info->node_cpu[i];
1293 core->proximity_lo = curnode;
1294 memset(core->proximity_hi, 0, 3);
1295 core->local_sapic_eid = 0;
1296 core->flags = cpu_to_le32(1);
1297 }
1298
1299
1300 /* the memory map is a bit tricky, it contains at least one hole
1301 * from 640k-1M and possibly another one from 3.5G-4G.
1302 */
1303 next_base = 0;
1304 numa_start = table_data->len;
1305
1306 numamem = acpi_data_push(table_data, sizeof *numamem);
1307 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1308 next_base = 1024 * 1024;
1309 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1310 mem_base = next_base;
1311 mem_len = guest_info->node_mem[i - 1];
1312 if (i == 1) {
1313 mem_len -= 1024 * 1024;
1314 }
1315 next_base = mem_base + mem_len;
1316
1317 /* Cut out the ACPI_PCI hole */
1318 if (mem_base <= guest_info->ram_size_below_4g &&
1319 next_base > guest_info->ram_size_below_4g) {
1320 mem_len -= next_base - guest_info->ram_size_below_4g;
1321 if (mem_len > 0) {
1322 numamem = acpi_data_push(table_data, sizeof *numamem);
1323 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1324 MEM_AFFINITY_ENABLED);
1325 }
1326 mem_base = 1ULL << 32;
1327 mem_len = next_base - guest_info->ram_size_below_4g;
1328 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1329 }
1330 numamem = acpi_data_push(table_data, sizeof *numamem);
1331 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1332 MEM_AFFINITY_ENABLED);
1333 }
1334 slots = (table_data->len - numa_start) / sizeof *numamem;
1335 for (; slots < guest_info->numa_nodes + 2; slots++) {
1336 numamem = acpi_data_push(table_data, sizeof *numamem);
1337 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1338 }
1339
1340 /*
1341 * Entry is required for Windows to enable memory hotplug in OS.
1342 * Memory devices may override proximity set by this entry,
1343 * providing _PXM method if necessary.
1344 */
1345 if (hotplugabble_address_space_size) {
1346 numamem = acpi_data_push(table_data, sizeof *numamem);
1347 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base,
1348 hotplugabble_address_space_size, 0,
1349 MEM_AFFINITY_HOTPLUGGABLE |
1350 MEM_AFFINITY_ENABLED);
1351 }
1352
1353 build_header(linker, table_data,
1354 (void *)(table_data->data + srat_start),
1355 "SRAT",
1356 table_data->len - srat_start, 1);
1357 }
1358
1359 static void
1360 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1361 {
1362 AcpiTableMcfg *mcfg;
1363 const char *sig;
1364 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1365
1366 mcfg = acpi_data_push(table_data, len);
1367 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1368 /* Only a single allocation so no need to play with segments */
1369 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1370 mcfg->allocation[0].start_bus_number = 0;
1371 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1372
1373 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1374 * To avoid table size changes (which create migration issues),
1375 * always create the table even if there are no allocations,
1376 * but set the signature to a reserved value in this case.
1377 * ACPI spec requires OSPMs to ignore such tables.
1378 */
1379 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1380 /* Reserved signature: ignored by OSPM */
1381 sig = "QEMU";
1382 } else {
1383 sig = "MCFG";
1384 }
1385 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1386 }
1387
1388 static void
1389 build_dmar_q35(GArray *table_data, GArray *linker)
1390 {
1391 int dmar_start = table_data->len;
1392
1393 AcpiTableDmar *dmar;
1394 AcpiDmarHardwareUnit *drhd;
1395
1396 dmar = acpi_data_push(table_data, sizeof(*dmar));
1397 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1398 dmar->flags = 0; /* No intr_remap for now */
1399
1400 /* DMAR Remapping Hardware Unit Definition structure */
1401 drhd = acpi_data_push(table_data, sizeof(*drhd));
1402 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1403 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1404 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1405 drhd->pci_segment = cpu_to_le16(0);
1406 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1407
1408 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1409 "DMAR", table_data->len - dmar_start, 1);
1410 }
1411
1412 static void
1413 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1414 {
1415 AcpiTableHeader *dsdt;
1416
1417 assert(misc->dsdt_code && misc->dsdt_size);
1418
1419 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1420 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1421
1422 memset(dsdt, 0, sizeof *dsdt);
1423 build_header(linker, table_data, dsdt, "DSDT",
1424 misc->dsdt_size, 1);
1425 }
1426
1427 /* Build final rsdt table */
1428 static void
1429 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
1430 {
1431 AcpiRsdtDescriptorRev1 *rsdt;
1432 size_t rsdt_len;
1433 int i;
1434
1435 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
1436 rsdt = acpi_data_push(table_data, rsdt_len);
1437 memcpy(rsdt->table_offset_entry, table_offsets->data,
1438 sizeof(uint32_t) * table_offsets->len);
1439 for (i = 0; i < table_offsets->len; ++i) {
1440 /* rsdt->table_offset_entry to be filled by Guest linker */
1441 bios_linker_loader_add_pointer(linker,
1442 ACPI_BUILD_TABLE_FILE,
1443 ACPI_BUILD_TABLE_FILE,
1444 table_data, &rsdt->table_offset_entry[i],
1445 sizeof(uint32_t));
1446 }
1447 build_header(linker, table_data,
1448 (void *)rsdt, "RSDT", rsdt_len, 1);
1449 }
1450
1451 static GArray *
1452 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1453 {
1454 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1455
1456 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1457 true /* fseg memory */);
1458
1459 memcpy(&rsdp->signature, "RSD PTR ", 8);
1460 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1461 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1462 /* Address to be filled by Guest linker */
1463 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1464 ACPI_BUILD_TABLE_FILE,
1465 rsdp_table, &rsdp->rsdt_physical_address,
1466 sizeof rsdp->rsdt_physical_address);
1467 rsdp->checksum = 0;
1468 /* Checksum to be filled by Guest linker */
1469 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1470 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1471
1472 return rsdp_table;
1473 }
1474
1475 typedef
1476 struct AcpiBuildTables {
1477 GArray *table_data;
1478 GArray *rsdp;
1479 GArray *tcpalog;
1480 GArray *linker;
1481 } AcpiBuildTables;
1482
1483 static inline void acpi_build_tables_init(AcpiBuildTables *tables)
1484 {
1485 tables->rsdp = g_array_new(false, true /* clear */, 1);
1486 tables->table_data = g_array_new(false, true /* clear */, 1);
1487 tables->tcpalog = g_array_new(false, true /* clear */, 1);
1488 tables->linker = bios_linker_loader_init();
1489 }
1490
1491 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
1492 {
1493 void *linker_data = bios_linker_loader_cleanup(tables->linker);
1494 g_free(linker_data);
1495 g_array_free(tables->rsdp, true);
1496 g_array_free(tables->table_data, true);
1497 g_array_free(tables->tcpalog, mfre);
1498 }
1499
1500 typedef
1501 struct AcpiBuildState {
1502 /* Copy of table in RAM (for patching). */
1503 ram_addr_t table_ram;
1504 /* Is table patched? */
1505 uint8_t patched;
1506 PcGuestInfo *guest_info;
1507 void *rsdp;
1508 ram_addr_t rsdp_ram;
1509 ram_addr_t linker_ram;
1510 } AcpiBuildState;
1511
1512 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1513 {
1514 Object *pci_host;
1515 QObject *o;
1516 bool ambiguous;
1517
1518 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1519 g_assert(!ambiguous);
1520 g_assert(pci_host);
1521
1522 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1523 if (!o) {
1524 return false;
1525 }
1526 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1527 qobject_decref(o);
1528
1529 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1530 assert(o);
1531 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1532 qobject_decref(o);
1533 return true;
1534 }
1535
1536 static bool acpi_has_iommu(void)
1537 {
1538 bool ambiguous;
1539 Object *intel_iommu;
1540
1541 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1542 &ambiguous);
1543 return intel_iommu && !ambiguous;
1544 }
1545
1546 static
1547 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1548 {
1549 GArray *table_offsets;
1550 unsigned facs, ssdt, dsdt, rsdt;
1551 AcpiCpuInfo cpu;
1552 AcpiPmInfo pm;
1553 AcpiMiscInfo misc;
1554 AcpiMcfgInfo mcfg;
1555 PcPciInfo pci;
1556 uint8_t *u;
1557 size_t aml_len = 0;
1558 GArray *tables_blob = tables->table_data;
1559
1560 acpi_get_cpu_info(&cpu);
1561 acpi_get_pm_info(&pm);
1562 acpi_get_dsdt(&misc);
1563 acpi_get_misc_info(&misc);
1564 acpi_get_pci_info(&pci);
1565
1566 table_offsets = g_array_new(false, true /* clear */,
1567 sizeof(uint32_t));
1568 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1569
1570 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1571 64 /* Ensure FACS is aligned */,
1572 false /* high memory */);
1573
1574 /*
1575 * FACS is pointed to by FADT.
1576 * We place it first since it's the only table that has alignment
1577 * requirements.
1578 */
1579 facs = tables_blob->len;
1580 build_facs(tables_blob, tables->linker, guest_info);
1581
1582 /* DSDT is pointed to by FADT */
1583 dsdt = tables_blob->len;
1584 build_dsdt(tables_blob, tables->linker, &misc);
1585
1586 /* Count the size of the DSDT and SSDT, we will need it for legacy
1587 * sizing of ACPI tables.
1588 */
1589 aml_len += tables_blob->len - dsdt;
1590
1591 /* ACPI tables pointed to by RSDT */
1592 acpi_add_table(table_offsets, tables_blob);
1593 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1594
1595 ssdt = tables_blob->len;
1596 acpi_add_table(table_offsets, tables_blob);
1597 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1598 guest_info);
1599 aml_len += tables_blob->len - ssdt;
1600
1601 acpi_add_table(table_offsets, tables_blob);
1602 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1603
1604 if (misc.has_hpet) {
1605 acpi_add_table(table_offsets, tables_blob);
1606 build_hpet(tables_blob, tables->linker);
1607 }
1608 if (misc.has_tpm) {
1609 acpi_add_table(table_offsets, tables_blob);
1610 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1611
1612 acpi_add_table(table_offsets, tables_blob);
1613 build_tpm_ssdt(tables_blob, tables->linker);
1614 }
1615 if (guest_info->numa_nodes) {
1616 acpi_add_table(table_offsets, tables_blob);
1617 build_srat(tables_blob, tables->linker, guest_info);
1618 }
1619 if (acpi_get_mcfg(&mcfg)) {
1620 acpi_add_table(table_offsets, tables_blob);
1621 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1622 }
1623 if (acpi_has_iommu()) {
1624 acpi_add_table(table_offsets, tables_blob);
1625 build_dmar_q35(tables_blob, tables->linker);
1626 }
1627
1628 /* Add tables supplied by user (if any) */
1629 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1630 unsigned len = acpi_table_len(u);
1631
1632 acpi_add_table(table_offsets, tables_blob);
1633 g_array_append_vals(tables_blob, u, len);
1634 }
1635
1636 /* RSDT is pointed to by RSDP */
1637 rsdt = tables_blob->len;
1638 build_rsdt(tables_blob, tables->linker, table_offsets);
1639
1640 /* RSDP is in FSEG memory, so allocate it separately */
1641 build_rsdp(tables->rsdp, tables->linker, rsdt);
1642
1643 /* We'll expose it all to Guest so we want to reduce
1644 * chance of size changes.
1645 *
1646 * We used to align the tables to 4k, but of course this would
1647 * too simple to be enough. 4k turned out to be too small an
1648 * alignment very soon, and in fact it is almost impossible to
1649 * keep the table size stable for all (max_cpus, max_memory_slots)
1650 * combinations. So the table size is always 64k for pc-i440fx-2.1
1651 * and we give an error if the table grows beyond that limit.
1652 *
1653 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1654 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1655 * than 2.0 and we can always pad the smaller tables with zeros. We can
1656 * then use the exact size of the 2.0 tables.
1657 *
1658 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1659 */
1660 if (guest_info->legacy_acpi_table_size) {
1661 /* Subtracting aml_len gives the size of fixed tables. Then add the
1662 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1663 */
1664 int legacy_aml_len =
1665 guest_info->legacy_acpi_table_size +
1666 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1667 int legacy_table_size =
1668 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1669 ACPI_BUILD_ALIGN_SIZE);
1670 if (tables_blob->len > legacy_table_size) {
1671 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1672 error_report("Warning: migration may not work.");
1673 }
1674 g_array_set_size(tables_blob, legacy_table_size);
1675 } else {
1676 /* Make sure we have a buffer in case we need to resize the tables. */
1677 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1678 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1679 error_report("Warning: ACPI tables are larger than 64k.");
1680 error_report("Warning: migration may not work.");
1681 error_report("Warning: please remove CPUs, NUMA nodes, "
1682 "memory slots or PCI bridges.");
1683 }
1684 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1685 }
1686
1687 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1688
1689 /* Cleanup memory that's no longer used. */
1690 g_array_free(table_offsets, true);
1691 }
1692
1693 static void acpi_ram_update(ram_addr_t ram, GArray *data)
1694 {
1695 uint32_t size = acpi_data_len(data);
1696
1697 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1698 qemu_ram_resize(ram, size, &error_abort);
1699
1700 memcpy(qemu_get_ram_ptr(ram), data->data, size);
1701 cpu_physical_memory_set_dirty_range_nocode(ram, size);
1702 }
1703
1704 static void acpi_build_update(void *build_opaque, uint32_t offset)
1705 {
1706 AcpiBuildState *build_state = build_opaque;
1707 AcpiBuildTables tables;
1708
1709 /* No state to update or already patched? Nothing to do. */
1710 if (!build_state || build_state->patched) {
1711 return;
1712 }
1713 build_state->patched = 1;
1714
1715 acpi_build_tables_init(&tables);
1716
1717 acpi_build(build_state->guest_info, &tables);
1718
1719 acpi_ram_update(build_state->table_ram, tables.table_data);
1720
1721 if (build_state->rsdp) {
1722 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1723 } else {
1724 acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
1725 }
1726
1727 acpi_ram_update(build_state->linker_ram, tables.linker);
1728 acpi_build_tables_cleanup(&tables, true);
1729 }
1730
1731 static void acpi_build_reset(void *build_opaque)
1732 {
1733 AcpiBuildState *build_state = build_opaque;
1734 build_state->patched = 0;
1735 }
1736
1737 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
1738 const char *name, uint64_t max_size)
1739 {
1740 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1741 name, acpi_build_update, build_state);
1742 }
1743
1744 static const VMStateDescription vmstate_acpi_build = {
1745 .name = "acpi_build",
1746 .version_id = 1,
1747 .minimum_version_id = 1,
1748 .fields = (VMStateField[]) {
1749 VMSTATE_UINT8(patched, AcpiBuildState),
1750 VMSTATE_END_OF_LIST()
1751 },
1752 };
1753
1754 void acpi_setup(PcGuestInfo *guest_info)
1755 {
1756 AcpiBuildTables tables;
1757 AcpiBuildState *build_state;
1758
1759 if (!guest_info->fw_cfg) {
1760 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1761 return;
1762 }
1763
1764 if (!guest_info->has_acpi_build) {
1765 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1766 return;
1767 }
1768
1769 if (!acpi_enabled) {
1770 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1771 return;
1772 }
1773
1774 build_state = g_malloc0(sizeof *build_state);
1775
1776 build_state->guest_info = guest_info;
1777
1778 acpi_set_pci_info();
1779
1780 acpi_build_tables_init(&tables);
1781 acpi_build(build_state->guest_info, &tables);
1782
1783 /* Now expose it all to Guest */
1784 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
1785 ACPI_BUILD_TABLE_FILE,
1786 ACPI_BUILD_TABLE_MAX_SIZE);
1787 assert(build_state->table_ram != RAM_ADDR_MAX);
1788
1789 build_state->linker_ram =
1790 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1791
1792 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1793 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1794
1795 if (!guest_info->rsdp_in_ram) {
1796 /*
1797 * Keep for compatibility with old machine types.
1798 * Though RSDP is small, its contents isn't immutable, so
1799 * we'll update it along with the rest of tables on guest access.
1800 */
1801 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1802
1803 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1804 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1805 acpi_build_update, build_state,
1806 build_state->rsdp, rsdp_size);
1807 build_state->rsdp_ram = (ram_addr_t)-1;
1808 } else {
1809 build_state->rsdp = NULL;
1810 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
1811 ACPI_BUILD_RSDP_FILE, 0);
1812 }
1813
1814 qemu_register_reset(acpi_build_reset, build_state);
1815 acpi_build_reset(build_state);
1816 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1817
1818 /* Cleanup tables but don't free the memory: we track it
1819 * in build_state.
1820 */
1821 acpi_build_tables_cleanup(&tables, false);
1822 }
AR7 emulation for QEMU