hw/timer/sh_timer.c

   1 /*
   2  * SuperH Timer modules.
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Based on arm_timer.c by Paul Brook
   6  * Copyright (c) 2005-2006 CodeSourcery.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "hw/hw.h"
  13 #include "hw/sh4/sh.h"
  14 #include "qemu/timer.h"
  15 #include "qemu/main-loop.h"
  16 #include "hw/ptimer.h"
  17
  18 //#define DEBUG_TIMER
  19
  20 #define TIMER_TCR_TPSC          (7 << 0)
  21 #define TIMER_TCR_CKEG          (3 << 3)
  22 #define TIMER_TCR_UNIE          (1 << 5)
  23 #define TIMER_TCR_ICPE          (3 << 6)
  24 #define TIMER_TCR_UNF           (1 << 8)
  25 #define TIMER_TCR_ICPF          (1 << 9)
  26 #define TIMER_TCR_RESERVED      (0x3f << 10)
  27
  28 #define TIMER_FEAT_CAPT   (1 << 0)
  29 #define TIMER_FEAT_EXTCLK (1 << 1)
  30
  31 #define OFFSET_TCOR   0
  32 #define OFFSET_TCNT   1
  33 #define OFFSET_TCR    2
  34 #define OFFSET_TCPR   3
  35
  36 typedef struct {
  37     ptimer_state *timer;
  38     uint32_t tcnt;
  39     uint32_t tcor;
  40     uint32_t tcr;
  41     uint32_t tcpr;
  42     int freq;
  43     int int_level;
  44     int old_level;
  45     int feat;
  46     int enabled;
  47     qemu_irq irq;
  48 } sh_timer_state;
  49
  50 /* Check all active timers, and schedule the next timer interrupt. */
  51
  52 static void sh_timer_update(sh_timer_state *s)
  53 {
  54     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
  55
  56     if (new_level != s->old_level)
  57       qemu_set_irq (s->irq, new_level);
  58
  59     s->old_level = s->int_level;
  60     s->int_level = new_level;
  61 }
  62
  63 static uint32_t sh_timer_read(void *opaque, hwaddr offset)
  64 {
  65     sh_timer_state *s = (sh_timer_state *)opaque;
  66
  67     switch (offset >> 2) {
  68     case OFFSET_TCOR:
  69         return s->tcor;
  70     case OFFSET_TCNT:
  71         return ptimer_get_count(s->timer);
  72     case OFFSET_TCR:
  73         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
  74     case OFFSET_TCPR:
  75         if (s->feat & TIMER_FEAT_CAPT)
  76             return s->tcpr;
  77         /* fall through */
  78     default:
  79         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
  80         return 0;
  81     }
  82 }
  83
  84 static void sh_timer_write(void *opaque, hwaddr offset,
  85                             uint32_t value)
  86 {
  87     sh_timer_state *s = (sh_timer_state *)opaque;
  88     int freq;
  89
  90     switch (offset >> 2) {
  91     case OFFSET_TCOR:
  92         s->tcor = value;
  93         ptimer_set_limit(s->timer, s->tcor, 0);
  94         break;
  95     case OFFSET_TCNT:
  96         s->tcnt = value;
  97         ptimer_set_count(s->timer, s->tcnt);
  98         break;
  99     case OFFSET_TCR:
 100         if (s->enabled) {
 101             /* Pause the timer if it is running.  This may cause some
 102                inaccuracy dure to rounding, but avoids a whole lot of other
 103                messyness.  */
 104             ptimer_stop(s->timer);
 105         }
 106         freq = s->freq;
 107         /* ??? Need to recalculate expiry time after changing divisor.  */
 108         switch (value & TIMER_TCR_TPSC) {
 109         case 0: freq >>= 2; break;
 110         case 1: freq >>= 4; break;
 111         case 2: freq >>= 6; break;
 112         case 3: freq >>= 8; break;
 113         case 4: freq >>= 10; break;
 114         case 6:
 115         case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
 116         default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
 117         }
 118         switch ((value & TIMER_TCR_CKEG) >> 3) {
 119         case 0: break;
 120         case 1:
 121         case 2:
 122         case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
 123         default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
 124         }
 125         switch ((value & TIMER_TCR_ICPE) >> 6) {
 126         case 0: break;
 127         case 2:
 128         case 3: if (s->feat & TIMER_FEAT_CAPT) break;
 129         default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
 130         }
 131         if ((value & TIMER_TCR_UNF) == 0)
 132             s->int_level = 0;
 133
 134         value &= ~TIMER_TCR_UNF;
 135
 136         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
 137             hw_error("sh_timer_write: Reserved ICPF value\n");
 138
 139         value &= ~TIMER_TCR_ICPF; /* capture not supported */
 140
 141         if (value & TIMER_TCR_RESERVED)
 142             hw_error("sh_timer_write: Reserved TCR bits set\n");
 143         s->tcr = value;
 144         ptimer_set_limit(s->timer, s->tcor, 0);
 145         ptimer_set_freq(s->timer, freq);
 146         if (s->enabled) {
 147             /* Restart the timer if still enabled.  */
 148             ptimer_run(s->timer, 0);
 149         }
 150         break;
 151     case OFFSET_TCPR:
 152         if (s->feat & TIMER_FEAT_CAPT) {
 153             s->tcpr = value;
 154             break;
 155         }
 156     default:
 157         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
 158     }
 159     sh_timer_update(s);
 160 }
 161
 162 static void sh_timer_start_stop(void *opaque, int enable)
 163 {
 164     sh_timer_state *s = (sh_timer_state *)opaque;
 165
 166 #ifdef DEBUG_TIMER
 167     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
 168 #endif
 169
 170     if (s->enabled && !enable) {
 171         ptimer_stop(s->timer);
 172     }
 173     if (!s->enabled && enable) {
 174         ptimer_run(s->timer, 0);
 175     }
 176     s->enabled = !!enable;
 177
 178 #ifdef DEBUG_TIMER
 179     printf("sh_timer_start_stop done %d\n", s->enabled);
 180 #endif
 181 }
 182
 183 static void sh_timer_tick(void *opaque)
 184 {
 185     sh_timer_state *s = (sh_timer_state *)opaque;
 186     s->int_level = s->enabled;
 187     sh_timer_update(s);
 188 }
 189
 190 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
 191 {
 192     sh_timer_state *s;
 193     QEMUBH *bh;
 194
 195     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
 196     s->freq = freq;
 197     s->feat = feat;
 198     s->tcor = 0xffffffff;
 199     s->tcnt = 0xffffffff;
 200     s->tcpr = 0xdeadbeef;
 201     s->tcr = 0;
 202     s->enabled = 0;
 203     s->irq = irq;
 204
 205     bh = qemu_bh_new(sh_timer_tick, s);
 206     s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 207
 208     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
 209     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
 210     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
 211     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
 212     /* ??? Save/restore.  */
 213     return s;
 214 }
 215
 216 typedef struct {
 217     MemoryRegion iomem;
 218     MemoryRegion iomem_p4;
 219     MemoryRegion iomem_a7;
 220     void *timer[3];
 221     int level[3];
 222     uint32_t tocr;
 223     uint32_t tstr;
 224     int feat;
 225 } tmu012_state;
 226
 227 static uint64_t tmu012_read(void *opaque, hwaddr offset,
 228                             unsigned size)
 229 {
 230     tmu012_state *s = (tmu012_state *)opaque;
 231
 232 #ifdef DEBUG_TIMER
 233     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
 234 #endif
 235
 236     if (offset >= 0x20) {
 237         if (!(s->feat & TMU012_FEAT_3CHAN))
 238             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 239         return sh_timer_read(s->timer[2], offset - 0x20);
 240     }
 241
 242     if (offset >= 0x14)
 243         return sh_timer_read(s->timer[1], offset - 0x14);
 244
 245     if (offset >= 0x08)
 246         return sh_timer_read(s->timer[0], offset - 0x08);
 247
 248     if (offset == 4)
 249         return s->tstr;
 250
 251     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
 252         return s->tocr;
 253
 254     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
 255     return 0;
 256 }
 257
 258 static void tmu012_write(void *opaque, hwaddr offset,
 259                         uint64_t value, unsigned size)
 260 {
 261     tmu012_state *s = (tmu012_state *)opaque;
 262
 263 #ifdef DEBUG_TIMER
 264     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 265 #endif
 266
 267     if (offset >= 0x20) {
 268         if (!(s->feat & TMU012_FEAT_3CHAN))
 269             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 270         sh_timer_write(s->timer[2], offset - 0x20, value);
 271         return;
 272     }
 273
 274     if (offset >= 0x14) {
 275         sh_timer_write(s->timer[1], offset - 0x14, value);
 276         return;
 277     }
 278
 279     if (offset >= 0x08) {
 280         sh_timer_write(s->timer[0], offset - 0x08, value);
 281         return;
 282     }
 283
 284     if (offset == 4) {
 285         sh_timer_start_stop(s->timer[0], value & (1 << 0));
 286         sh_timer_start_stop(s->timer[1], value & (1 << 1));
 287         if (s->feat & TMU012_FEAT_3CHAN)
 288             sh_timer_start_stop(s->timer[2], value & (1 << 2));
 289         else
 290             if (value & (1 << 2))
 291                 hw_error("tmu012_write: Bad channel\n");
 292
 293         s->tstr = value;
 294         return;
 295     }
 296
 297     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
 298         s->tocr = value & (1 << 0);
 299     }
 300 }
 301
 302 static const MemoryRegionOps tmu012_ops = {
 303     .read = tmu012_read,
 304     .write = tmu012_write,
 305     .endianness = DEVICE_NATIVE_ENDIAN,
 306 };
 307
 308 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
 309                  int feat, uint32_t freq,
 310                  qemu_irq ch0_irq, qemu_irq ch1_irq,
 311                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 312 {
 313     tmu012_state *s;
 314     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 315
 316     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
 317     s->feat = feat;
 318     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 319     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
 320     if (feat & TMU012_FEAT_3CHAN)
 321         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
 322                                     ch2_irq0); /* ch2_irq1 not supported */
 323
 324     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
 325                           "timer", 0x100000000ULL);
 326
 327     memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
 328                              &s->iomem, 0, 0x1000);
 329     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 330
 331     memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
 332                              &s->iomem, 0, 0x1000);
 333     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 334     /* ??? Save/restore.  */
 335 }