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target/mips: Restrict mmu_init() to TCG
[qemu/ar7.git] / target / mips / cpu.c
blobc3159e3d7f3a0ef1e324c654d2b0177202eb5751
1 /*
2 * QEMU MIPS CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "qapi/error.h"
25 #include "cpu.h"
26 #include "internal.h"
27 #include "kvm_mips.h"
28 #include "qemu/module.h"
29 #include "sysemu/kvm.h"
30 #include "sysemu/qtest.h"
31 #include "exec/exec-all.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-clock.h"
34 #include "semihosting/semihost.h"
35 #include "qapi/qapi-commands-machine-target.h"
36 #include "fpu_helper.h"
37
38 const char regnames[32][4] = {
39 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
42 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
43 };
44
45 #if !defined(CONFIG_USER_ONLY)
46
47 /* Called for updates to CP0_Status. */
48 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
49 {
50 int32_t tcstatus, *tcst;
51 uint32_t v = cpu->CP0_Status;
52 uint32_t cu, mx, asid, ksu;
53 uint32_t mask = ((1 << CP0TCSt_TCU3)
54 | (1 << CP0TCSt_TCU2)
55 | (1 << CP0TCSt_TCU1)
56 | (1 << CP0TCSt_TCU0)
57 | (1 << CP0TCSt_TMX)
58 | (3 << CP0TCSt_TKSU)
59 | (0xff << CP0TCSt_TASID));
60
61 cu = (v >> CP0St_CU0) & 0xf;
62 mx = (v >> CP0St_MX) & 0x1;
63 ksu = (v >> CP0St_KSU) & 0x3;
64 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
65
66 tcstatus = cu << CP0TCSt_TCU0;
67 tcstatus |= mx << CP0TCSt_TMX;
68 tcstatus |= ksu << CP0TCSt_TKSU;
69 tcstatus |= asid;
70
71 if (tc == cpu->current_tc) {
72 tcst = &cpu->active_tc.CP0_TCStatus;
73 } else {
74 tcst = &cpu->tcs[tc].CP0_TCStatus;
75 }
76
77 *tcst &= ~mask;
78 *tcst |= tcstatus;
79 compute_hflags(cpu);
80 }
81
82 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
83 {
84 uint32_t mask = env->CP0_Status_rw_bitmask;
85 target_ulong old = env->CP0_Status;
86
87 if (env->insn_flags & ISA_MIPS_R6) {
88 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
89 #if defined(TARGET_MIPS64)
90 uint32_t ksux = (1 << CP0St_KX) & val;
91 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
92 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
93 val = (val & ~(7 << CP0St_UX)) | ksux;
94 #endif
95 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
96 mask &= ~(3 << CP0St_KSU);
97 }
98 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
99 }
100
101 env->CP0_Status = (old & ~mask) | (val & mask);
102 #if defined(TARGET_MIPS64)
103 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
104 /* Access to at least one of the 64-bit segments has been disabled */
105 tlb_flush(env_cpu(env));
106 }
107 #endif
108 if (ase_mt_available(env)) {
109 sync_c0_status(env, env, env->current_tc);
110 } else {
111 compute_hflags(env);
112 }
113 }
114
115 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
116 {
117 uint32_t mask = 0x00C00300;
118 uint32_t old = env->CP0_Cause;
119 int i;
120
121 if (env->insn_flags & ISA_MIPS_R2) {
122 mask |= 1 << CP0Ca_DC;
123 }
124 if (env->insn_flags & ISA_MIPS_R6) {
125 mask &= ~((1 << CP0Ca_WP) & val);
126 }
127
128 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
129
130 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
131 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
132 cpu_mips_stop_count(env);
133 } else {
134 cpu_mips_start_count(env);
135 }
136 }
137
138 /* Set/reset software interrupts */
139 for (i = 0 ; i < 2 ; i++) {
140 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
141 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
142 }
143 }
144 }
145
146 #endif /* !CONFIG_USER_ONLY */
147
148 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
149 {
150 if (is_fpu64) {
151 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
152 fpr->w[FP_ENDIAN_IDX], fpr->d,
153 (double)fpr->fd,
154 (double)fpr->fs[FP_ENDIAN_IDX],
155 (double)fpr->fs[!FP_ENDIAN_IDX]);
156 } else {
157 fpr_t tmp;
158
159 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
160 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
161 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
162 tmp.w[FP_ENDIAN_IDX], tmp.d,
163 (double)tmp.fd,
164 (double)tmp.fs[FP_ENDIAN_IDX],
165 (double)tmp.fs[!FP_ENDIAN_IDX]);
166 }
167 }
168
169 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
170 {
171 int i;
172 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
173
174 qemu_fprintf(f,
175 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
176 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
177 get_float_exception_flags(&env->active_fpu.fp_status));
178 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
179 qemu_fprintf(f, "%3s: ", fregnames[i]);
180 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
181 }
182 }
183
184 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
185 {
186 MIPSCPU *cpu = MIPS_CPU(cs);
187 CPUMIPSState *env = &cpu->env;
188 int i;
189
190 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
191 " LO=0x" TARGET_FMT_lx " ds %04x "
192 TARGET_FMT_lx " " TARGET_FMT_ld "\n",
193 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
194 env->hflags, env->btarget, env->bcond);
195 for (i = 0; i < 32; i++) {
196 if ((i & 3) == 0) {
197 qemu_fprintf(f, "GPR%02d:", i);
198 }
199 qemu_fprintf(f, " %s " TARGET_FMT_lx,
200 regnames[i], env->active_tc.gpr[i]);
201 if ((i & 3) == 3) {
202 qemu_fprintf(f, "\n");
203 }
204 }
205
206 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
207 TARGET_FMT_lx "\n",
208 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
209 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
210 PRIx64 "\n",
211 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
212 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
213 env->CP0_Config2, env->CP0_Config3);
214 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
215 env->CP0_Config4, env->CP0_Config5);
216 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
217 fpu_dump_state(env, f, flags);
218 }
219 }
220
221 static const char * const excp_names[EXCP_LAST + 1] = {
222 [EXCP_RESET] = "reset",
223 [EXCP_SRESET] = "soft reset",
224 [EXCP_DSS] = "debug single step",
225 [EXCP_DINT] = "debug interrupt",
226 [EXCP_NMI] = "non-maskable interrupt",
227 [EXCP_MCHECK] = "machine check",
228 [EXCP_EXT_INTERRUPT] = "interrupt",
229 [EXCP_DFWATCH] = "deferred watchpoint",
230 [EXCP_DIB] = "debug instruction breakpoint",
231 [EXCP_IWATCH] = "instruction fetch watchpoint",
232 [EXCP_AdEL] = "address error load",
233 [EXCP_AdES] = "address error store",
234 [EXCP_TLBF] = "TLB refill",
235 [EXCP_IBE] = "instruction bus error",
236 [EXCP_DBp] = "debug breakpoint",
237 [EXCP_SYSCALL] = "syscall",
238 [EXCP_BREAK] = "break",
239 [EXCP_CpU] = "coprocessor unusable",
240 [EXCP_RI] = "reserved instruction",
241 [EXCP_OVERFLOW] = "arithmetic overflow",
242 [EXCP_TRAP] = "trap",
243 [EXCP_FPE] = "floating point",
244 [EXCP_DDBS] = "debug data break store",
245 [EXCP_DWATCH] = "data watchpoint",
246 [EXCP_LTLBL] = "TLB modify",
247 [EXCP_TLBL] = "TLB load",
248 [EXCP_TLBS] = "TLB store",
249 [EXCP_DBE] = "data bus error",
250 [EXCP_DDBL] = "debug data break load",
251 [EXCP_THREAD] = "thread",
252 [EXCP_MDMX] = "MDMX",
253 [EXCP_C2E] = "precise coprocessor 2",
254 [EXCP_CACHE] = "cache error",
255 [EXCP_TLBXI] = "TLB execute-inhibit",
256 [EXCP_TLBRI] = "TLB read-inhibit",
257 [EXCP_MSADIS] = "MSA disabled",
258 [EXCP_MSAFPE] = "MSA floating point",
259 };
260
261 const char *mips_exception_name(int32_t exception)
262 {
263 if (exception < 0 || exception > EXCP_LAST) {
264 return "unknown";
265 }
266 return excp_names[exception];
267 }
268
269 void cpu_set_exception_base(int vp_index, target_ulong address)
270 {
271 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
272 vp->env.exception_base = address;
273 }
274
275 target_ulong exception_resume_pc(CPUMIPSState *env)
276 {
277 target_ulong bad_pc;
278 target_ulong isa_mode;
279
280 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
281 bad_pc = env->active_tc.PC | isa_mode;
282 if (env->hflags & MIPS_HFLAG_BMASK) {
283 /*
284 * If the exception was raised from a delay slot, come back to
285 * the jump.
286 */
287 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
288 }
289
290 return bad_pc;
291 }
292
293 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
294 {
295 if (interrupt_request & CPU_INTERRUPT_HARD) {
296 MIPSCPU *cpu = MIPS_CPU(cs);
297 CPUMIPSState *env = &cpu->env;
298
299 if (cpu_mips_hw_interrupts_enabled(env) &&
300 cpu_mips_hw_interrupts_pending(env)) {
301 /* Raise it */
302 cs->exception_index = EXCP_EXT_INTERRUPT;
303 env->error_code = 0;
304 mips_cpu_do_interrupt(cs);
305 return true;
306 }
307 }
308 return false;
309 }
310
311 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
312 uint32_t exception,
313 int error_code,
314 uintptr_t pc)
315 {
316 CPUState *cs = env_cpu(env);
317
318 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
319 __func__, exception, mips_exception_name(exception),
320 error_code);
321 cs->exception_index = exception;
322 env->error_code = error_code;
323
324 cpu_loop_exit_restore(cs, pc);
325 }
326
327 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
328 {
329 MIPSCPU *cpu = MIPS_CPU(cs);
330
331 mips_env_set_pc(&cpu->env, value);
332 }
333
334 #ifdef CONFIG_TCG
335 static void mips_cpu_synchronize_from_tb(CPUState *cs,
336 const TranslationBlock *tb)
337 {
338 MIPSCPU *cpu = MIPS_CPU(cs);
339 CPUMIPSState *env = &cpu->env;
340
341 env->active_tc.PC = tb->pc;
342 env->hflags &= ~MIPS_HFLAG_BMASK;
343 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
344 }
345
346 # ifndef CONFIG_USER_ONLY
347 static bool mips_io_recompile_replay_branch(CPUState *cs,
348 const TranslationBlock *tb)
349 {
350 MIPSCPU *cpu = MIPS_CPU(cs);
351 CPUMIPSState *env = &cpu->env;
352
353 if ((env->hflags & MIPS_HFLAG_BMASK) != 0
354 && env->active_tc.PC != tb->pc) {
355 env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
356 env->hflags &= ~MIPS_HFLAG_BMASK;
357 return true;
358 }
359 return false;
360 }
361 # endif /* !CONFIG_USER_ONLY */
362 #endif /* CONFIG_TCG */
363
364 static bool mips_cpu_has_work(CPUState *cs)
365 {
366 MIPSCPU *cpu = MIPS_CPU(cs);
367 CPUMIPSState *env = &cpu->env;
368 bool has_work = false;
369
370 /*
371 * Prior to MIPS Release 6 it is implementation dependent if non-enabled
372 * interrupts wake-up the CPU, however most of the implementations only
373 * check for interrupts that can be taken.
374 */
375 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
376 cpu_mips_hw_interrupts_pending(env)) {
377 if (cpu_mips_hw_interrupts_enabled(env) ||
378 (env->insn_flags & ISA_MIPS_R6)) {
379 has_work = true;
380 }
381 }
382
383 /* MIPS-MT has the ability to halt the CPU. */
384 if (ase_mt_available(env)) {
385 /*
386 * The QEMU model will issue an _WAKE request whenever the CPUs
387 * should be woken up.
388 */
389 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
390 has_work = true;
391 }
392
393 if (!mips_vpe_active(env)) {
394 has_work = false;
395 }
396 }
397 /* MIPS Release 6 has the ability to halt the CPU. */
398 if (env->CP0_Config5 & (1 << CP0C5_VP)) {
399 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
400 has_work = true;
401 }
402 if (!mips_vp_active(env)) {
403 has_work = false;
404 }
405 }
406 return has_work;
407 }
408
409 #include "cpu-defs.c.inc"
410
411 static void mips_cpu_reset(DeviceState *dev)
412 {
413 CPUState *cs = CPU(dev);
414 MIPSCPU *cpu = MIPS_CPU(cs);
415 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
416 CPUMIPSState *env = &cpu->env;
417
418 mcc->parent_reset(dev);
419
420 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
421
422 /* Reset registers to their default values */
423 env->CP0_PRid = env->cpu_model->CP0_PRid;
424 env->CP0_Config0 = env->cpu_model->CP0_Config0;
425 #ifdef TARGET_WORDS_BIGENDIAN
426 env->CP0_Config0 |= (1 << CP0C0_BE);
427 #endif
428 env->CP0_Config1 = env->cpu_model->CP0_Config1;
429 env->CP0_Config2 = env->cpu_model->CP0_Config2;
430 env->CP0_Config3 = env->cpu_model->CP0_Config3;
431 env->CP0_Config4 = env->cpu_model->CP0_Config4;
432 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
433 env->CP0_Config5 = env->cpu_model->CP0_Config5;
434 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
435 env->CP0_Config6 = env->cpu_model->CP0_Config6;
436 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
437 env->CP0_Config7 = env->cpu_model->CP0_Config7;
438 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
439 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
440 << env->cpu_model->CP0_LLAddr_shift;
441 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
442 env->SYNCI_Step = env->cpu_model->SYNCI_Step;
443 env->CCRes = env->cpu_model->CCRes;
444 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
445 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
446 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
447 env->current_tc = 0;
448 env->SEGBITS = env->cpu_model->SEGBITS;
449 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
450 #if defined(TARGET_MIPS64)
451 if (env->cpu_model->insn_flags & ISA_MIPS3) {
452 env->SEGMask |= 3ULL << 62;
453 }
454 #endif
455 env->PABITS = env->cpu_model->PABITS;
456 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
457 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
458 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
459 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
460 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
461 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
462 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
463 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
464 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
465 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
466 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
467 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
468 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
469 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
470 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
471 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
472 env->msair = env->cpu_model->MSAIR;
473 env->insn_flags = env->cpu_model->insn_flags;
474
475 #if defined(CONFIG_USER_ONLY)
476 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
477 # ifdef TARGET_MIPS64
478 /* Enable 64-bit register mode. */
479 env->CP0_Status |= (1 << CP0St_PX);
480 # endif
481 # ifdef TARGET_ABI_MIPSN64
482 /* Enable 64-bit address mode. */
483 env->CP0_Status |= (1 << CP0St_UX);
484 # endif
485 /*
486 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
487 * hardware registers.
488 */
489 env->CP0_HWREna |= 0x0000000F;
490 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
491 env->CP0_Status |= (1 << CP0St_CU1);
492 }
493 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
494 env->CP0_Status |= (1 << CP0St_MX);
495 }
496 # if defined(TARGET_MIPS64)
497 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
498 if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
499 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
500 env->CP0_Status |= (1 << CP0St_FR);
501 }
502 # endif
503 #else /* !CONFIG_USER_ONLY */
504 if (env->hflags & MIPS_HFLAG_BMASK) {
505 /*
506 * If the exception was raised from a delay slot,
507 * come back to the jump.
508 */
509 env->CP0_ErrorEPC = (env->active_tc.PC
510 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
511 } else {
512 env->CP0_ErrorEPC = env->active_tc.PC;
513 }
514 env->active_tc.PC = env->exception_base;
515 env->CP0_Random = env->tlb->nb_tlb - 1;
516 env->tlb->tlb_in_use = env->tlb->nb_tlb;
517 env->CP0_Wired = 0;
518 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
519 env->CP0_EBase = (cs->cpu_index & 0x3FF);
520 if (mips_um_ksegs_enabled()) {
521 env->CP0_EBase |= 0x40000000;
522 } else {
523 env->CP0_EBase |= (int32_t)0x80000000;
524 }
525 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
526 env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
527 }
528 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
529 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
530 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
531 /*
532 * Vectored interrupts not implemented, timer on int 7,
533 * no performance counters.
534 */
535 env->CP0_IntCtl = 0xe0000000;
536 {
537 int i;
538
539 for (i = 0; i < 7; i++) {
540 env->CP0_WatchLo[i] = 0;
541 env->CP0_WatchHi[i] = 0x80000000;
542 }
543 env->CP0_WatchLo[7] = 0;
544 env->CP0_WatchHi[7] = 0;
545 }
546 /* Count register increments in debug mode, EJTAG version 1 */
547 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
548
549 cpu_mips_store_count(env, 1);
550
551 if (ase_mt_available(env)) {
552 int i;
553
554 /* Only TC0 on VPE 0 starts as active. */
555 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
556 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
557 env->tcs[i].CP0_TCHalt = 1;
558 }
559 env->active_tc.CP0_TCHalt = 1;
560 cs->halted = 1;
561
562 if (cs->cpu_index == 0) {
563 /* VPE0 starts up enabled. */
564 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
565 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
566
567 /* TC0 starts up unhalted. */
568 cs->halted = 0;
569 env->active_tc.CP0_TCHalt = 0;
570 env->tcs[0].CP0_TCHalt = 0;
571 /* With thread 0 active. */
572 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
573 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
574 }
575 }
576
577 /*
578 * Configure default legacy segmentation control. We use this regardless of
579 * whether segmentation control is presented to the guest.
580 */
581 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
582 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
583 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
584 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
585 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
586 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
587 (2 << CP0SC_C);
588 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
589 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
590 (3 << CP0SC_C)) << 16;
591 /* USeg (seg4 0x40000000..0x7FFFFFFF) */
592 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
593 (1 << CP0SC_EU) | (2 << CP0SC_C);
594 /* USeg (seg5 0x00000000..0x3FFFFFFF) */
595 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
596 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
597 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
598 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
599 #endif /* !CONFIG_USER_ONLY */
600 if ((env->insn_flags & ISA_MIPS_R6) &&
601 (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
602 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
603 env->CP0_Status |= (1 << CP0St_FR);
604 }
605
606 if (env->insn_flags & ISA_MIPS_R6) {
607 /* PTW = 1 */
608 env->CP0_PWSize = 0x40;
609 /* GDI = 12 */
610 /* UDI = 12 */
611 /* MDI = 12 */
612 /* PRI = 12 */
613 /* PTEI = 2 */
614 env->CP0_PWField = 0x0C30C302;
615 } else {
616 /* GDI = 0 */
617 /* UDI = 0 */
618 /* MDI = 0 */
619 /* PRI = 0 */
620 /* PTEI = 2 */
621 env->CP0_PWField = 0x02;
622 }
623
624 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
625 /* microMIPS on reset when Config3.ISA is 3 */
626 env->hflags |= MIPS_HFLAG_M16;
627 }
628
629 msa_reset(env);
630
631 compute_hflags(env);
632 restore_fp_status(env);
633 restore_pamask(env);
634 cs->exception_index = EXCP_NONE;
635
636 if (semihosting_get_argc()) {
637 /* UHI interface can be used to obtain argc and argv */
638 env->active_tc.gpr[4] = -1;
639 }
640
641 #ifndef CONFIG_USER_ONLY
642 if (kvm_enabled()) {
643 kvm_mips_reset_vcpu(cpu);
644 }
645 #endif
646 }
647
648 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
649 {
650 MIPSCPU *cpu = MIPS_CPU(s);
651 CPUMIPSState *env = &cpu->env;
652
653 if (!(env->insn_flags & ISA_NANOMIPS32)) {
654 #ifdef TARGET_WORDS_BIGENDIAN
655 info->print_insn = print_insn_big_mips;
656 #else
657 info->print_insn = print_insn_little_mips;
658 #endif
659 } else {
660 #if defined(CONFIG_NANOMIPS_DIS)
661 info->print_insn = print_insn_nanomips;
662 #endif
663 }
664 }
665
666 /*
667 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
668 */
669 #define CPU_FREQ_HZ_DEFAULT 200000000
670 #define CP0_COUNT_RATE_DEFAULT 2
671
672 static void mips_cp0_period_set(MIPSCPU *cpu)
673 {
674 CPUMIPSState *env = &cpu->env;
675
676 env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
677 cpu->cp0_count_rate);
678 assert(env->cp0_count_ns);
679 }
680
681 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
682 {
683 CPUState *cs = CPU(dev);
684 MIPSCPU *cpu = MIPS_CPU(dev);
685 CPUMIPSState *env = &cpu->env;
686 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
687 Error *local_err = NULL;
688
689 if (!clock_get(cpu->clock)) {
690 #ifndef CONFIG_USER_ONLY
691 if (!qtest_enabled()) {
692 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
693
694 warn_report("CPU input clock is not connected to any output clock, "
695 "using default frequency of %s.", cpu_freq_str);
696 }
697 #endif
698 /* Initialize the frequency in case the clock remains unconnected. */
699 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
700 }
701 mips_cp0_period_set(cpu);
702
703 cpu_exec_realizefn(cs, &local_err);
704 if (local_err != NULL) {
705 error_propagate(errp, local_err);
706 return;
707 }
708
709 env->exception_base = (int32_t)0xBFC00000;
710
711 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
712 mmu_init(env, env->cpu_model);
713 #endif
714 fpu_init(env, env->cpu_model);
715 mvp_init(env);
716
717 cpu_reset(cs);
718 qemu_init_vcpu(cs);
719
720 mcc->parent_realize(dev, errp);
721 }
722
723 static void mips_cpu_initfn(Object *obj)
724 {
725 MIPSCPU *cpu = MIPS_CPU(obj);
726 CPUMIPSState *env = &cpu->env;
727 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
728
729 cpu_set_cpustate_pointers(cpu);
730 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
731 env->cpu_model = mcc->cpu_def;
732 }
733
734 static char *mips_cpu_type_name(const char *cpu_model)
735 {
736 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
737 }
738
739 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
740 {
741 ObjectClass *oc;
742 char *typename;
743
744 typename = mips_cpu_type_name(cpu_model);
745 oc = object_class_by_name(typename);
746 g_free(typename);
747 return oc;
748 }
749
750 static Property mips_cpu_properties[] = {
751 /* CP0 timer running at half the clock of the CPU */
752 DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
753 CP0_COUNT_RATE_DEFAULT),
754 DEFINE_PROP_END_OF_LIST()
755 };
756
757 #ifdef CONFIG_TCG
758 #include "hw/core/tcg-cpu-ops.h"
759 /*
760 * NB: cannot be const, as some elements are changed for specific
761 * mips hardware (see hw/mips/jazz.c).
762 */
763 static struct TCGCPUOps mips_tcg_ops = {
764 .initialize = mips_tcg_init,
765 .synchronize_from_tb = mips_cpu_synchronize_from_tb,
766 .cpu_exec_interrupt = mips_cpu_exec_interrupt,
767 .tlb_fill = mips_cpu_tlb_fill,
768
769 #if !defined(CONFIG_USER_ONLY)
770 .do_interrupt = mips_cpu_do_interrupt,
771 .do_transaction_failed = mips_cpu_do_transaction_failed,
772 .do_unaligned_access = mips_cpu_do_unaligned_access,
773 .io_recompile_replay_branch = mips_io_recompile_replay_branch,
774 #endif /* !CONFIG_USER_ONLY */
775 };
776 #endif /* CONFIG_TCG */
777
778 static void mips_cpu_class_init(ObjectClass *c, void *data)
779 {
780 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
781 CPUClass *cc = CPU_CLASS(c);
782 DeviceClass *dc = DEVICE_CLASS(c);
783
784 device_class_set_parent_realize(dc, mips_cpu_realizefn,
785 &mcc->parent_realize);
786 device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
787 device_class_set_props(dc, mips_cpu_properties);
788
789 cc->class_by_name = mips_cpu_class_by_name;
790 cc->has_work = mips_cpu_has_work;
791 cc->dump_state = mips_cpu_dump_state;
792 cc->set_pc = mips_cpu_set_pc;
793 cc->gdb_read_register = mips_cpu_gdb_read_register;
794 cc->gdb_write_register = mips_cpu_gdb_write_register;
795 #ifndef CONFIG_USER_ONLY
796 cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
797 cc->vmsd = &vmstate_mips_cpu;
798 #endif
799 cc->disas_set_info = mips_cpu_disas_set_info;
800 cc->gdb_num_core_regs = 73;
801 cc->gdb_stop_before_watchpoint = true;
802 #ifdef CONFIG_TCG
803 cc->tcg_ops = &mips_tcg_ops;
804 #endif /* CONFIG_TCG */
805 }
806
807 static const TypeInfo mips_cpu_type_info = {
808 .name = TYPE_MIPS_CPU,
809 .parent = TYPE_CPU,
810 .instance_size = sizeof(MIPSCPU),
811 .instance_init = mips_cpu_initfn,
812 .abstract = true,
813 .class_size = sizeof(MIPSCPUClass),
814 .class_init = mips_cpu_class_init,
815 };
816
817 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
818 {
819 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
820 mcc->cpu_def = data;
821 }
822
823 static void mips_register_cpudef_type(const struct mips_def_t *def)
824 {
825 char *typename = mips_cpu_type_name(def->name);
826 TypeInfo ti = {
827 .name = typename,
828 .parent = TYPE_MIPS_CPU,
829 .class_init = mips_cpu_cpudef_class_init,
830 .class_data = (void *)def,
831 };
832
833 type_register(&ti);
834 g_free(typename);
835 }
836
837 static void mips_cpu_register_types(void)
838 {
839 int i;
840
841 type_register_static(&mips_cpu_type_info);
842 for (i = 0; i < mips_defs_number; i++) {
843 mips_register_cpudef_type(&mips_defs[i]);
844 }
845 }
846
847 type_init(mips_cpu_register_types)
848
849 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
850 {
851 ObjectClass *oc = data;
852 CpuDefinitionInfoList **cpu_list = user_data;
853 CpuDefinitionInfo *info;
854 const char *typename;
855
856 typename = object_class_get_name(oc);
857 info = g_malloc0(sizeof(*info));
858 info->name = g_strndup(typename,
859 strlen(typename) - strlen("-" TYPE_MIPS_CPU));
860 info->q_typename = g_strdup(typename);
861
862 QAPI_LIST_PREPEND(*cpu_list, info);
863 }
864
865 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
866 {
867 CpuDefinitionInfoList *cpu_list = NULL;
868 GSList *list;
869
870 list = object_class_get_list(TYPE_MIPS_CPU, false);
871 g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
872 g_slist_free(list);
873
874 return cpu_list;
875 }
876
877 /* Could be used by generic CPU object */
878 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
879 {
880 DeviceState *cpu;
881
882 cpu = DEVICE(object_new(cpu_type));
883 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
884 qdev_realize(cpu, NULL, &error_abort);
885
886 return MIPS_CPU(cpu);
887 }
888
889 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
890 {
891 return (env->cpu_model->insn_flags & isa_mask) != 0;
892 }
893
894 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
895 {
896 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
897 return (mcc->cpu_def->insn_flags & isa) != 0;
898 }
899
900 bool cpu_type_supports_cps_smp(const char *cpu_type)
901 {
902 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
903 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
904 }
AR7 emulation for QEMU