hw/pci-bridge/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/pci/pci_ids.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pcie.h"
  26 #include "xio3130_downstream.h"
  27 #include "qapi/error.h"
  28
  29 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  30 #define XIO3130_REVISION                0x1
  31 #define XIO3130_MSI_OFFSET              0x70
  32 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  33 #define XIO3130_MSI_NR_VECTOR           1
  34 #define XIO3130_SSVID_OFFSET            0x80
  35 #define XIO3130_SSVID_SVID              0
  36 #define XIO3130_SSVID_SSID              0
  37 #define XIO3130_EXP_OFFSET              0x90
  38 #define XIO3130_AER_OFFSET              0x100
  39
  40 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  41                                          uint32_t val, int len)
  42 {
  43     pci_bridge_write_config(d, address, val, len);
  44     pcie_cap_flr_write_config(d, address, val, len);
  45     pcie_cap_slot_write_config(d, address, val, len);
  46     pcie_aer_write_config(d, address, val, len);
  47 }
  48
  49 static void xio3130_downstream_reset(DeviceState *qdev)
  50 {
  51     PCIDevice *d = PCI_DEVICE(qdev);
  52
  53     pcie_cap_deverr_reset(d);
  54     pcie_cap_slot_reset(d);
  55     pcie_cap_arifwd_reset(d);
  56     pci_bridge_reset(qdev);
  57 }
  58
  59 static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
  60 {
  61     PCIEPort *p = PCIE_PORT(d);
  62     PCIESlot *s = PCIE_SLOT(d);
  63     int rc;
  64
  65     pci_bridge_initfn(d, TYPE_PCIE_BUS);
  66     pcie_port_init_reg(d);
  67
  68     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  69                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  70                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
  71                   errp);
  72     if (rc < 0) {
  73         assert(rc == -ENOTSUP);
  74         goto err_bridge;
  75     }
  76
  77     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  78                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
  79                                errp);
  80     if (rc < 0) {
  81         goto err_bridge;
  82     }
  83
  84     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  85                        p->port, errp);
  86     if (rc < 0) {
  87         goto err_msi;
  88     }
  89     pcie_cap_flr_init(d);
  90     pcie_cap_deverr_init(d);
  91     pcie_cap_slot_init(d, s->slot);
  92     pcie_cap_arifwd_init(d);
  93
  94     pcie_chassis_create(s->chassis);
  95     rc = pcie_chassis_add_slot(s);
  96     if (rc < 0) {
  97         error_setg(errp, "Can't add chassis slot, error %d", rc);
  98         goto err_pcie_cap;
  99     }
 100
 101     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
 102                        PCI_ERR_SIZEOF, errp);
 103     if (rc < 0) {
 104         goto err;
 105     }
 106
 107     return;
 108
 109 err:
 110     pcie_chassis_del_slot(s);
 111 err_pcie_cap:
 112     pcie_cap_exit(d);
 113 err_msi:
 114     msi_uninit(d);
 115 err_bridge:
 116     pci_bridge_exitfn(d);
 117 }
 118
 119 static void xio3130_downstream_exitfn(PCIDevice *d)
 120 {
 121     PCIESlot *s = PCIE_SLOT(d);
 122
 123     pcie_aer_exit(d);
 124     pcie_chassis_del_slot(s);
 125     pcie_cap_exit(d);
 126     msi_uninit(d);
 127     pci_bridge_exitfn(d);
 128 }
 129
 130 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
 131                                   const char *bus_name, pci_map_irq_fn map_irq,
 132                                   uint8_t port, uint8_t chassis,
 133                                   uint16_t slot)
 134 {
 135     PCIDevice *d;
 136     PCIBridge *br;
 137     DeviceState *qdev;
 138
 139     d = pci_create_multifunction(bus, devfn, multifunction,
 140                                  "xio3130-downstream");
 141     if (!d) {
 142         return NULL;
 143     }
 144     br = PCI_BRIDGE(d);
 145
 146     qdev = DEVICE(d);
 147     pci_bridge_map_irq(br, bus_name, map_irq);
 148     qdev_prop_set_uint8(qdev, "port", port);
 149     qdev_prop_set_uint8(qdev, "chassis", chassis);
 150     qdev_prop_set_uint16(qdev, "slot", slot);
 151     qdev_init_nofail(qdev);
 152
 153     return PCIE_SLOT(d);
 154 }
 155
 156 static Property xio3130_downstream_props[] = {
 157     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
 158                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 159     DEFINE_PROP_END_OF_LIST()
 160 };
 161
 162 static const VMStateDescription vmstate_xio3130_downstream = {
 163     .name = "xio3130-express-downstream-port",
 164     .priority = MIG_PRI_PCI_BUS,
 165     .version_id = 1,
 166     .minimum_version_id = 1,
 167     .post_load = pcie_cap_slot_post_load,
 168     .fields = (VMStateField[]) {
 169         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 170         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 171                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 172         VMSTATE_END_OF_LIST()
 173     }
 174 };
 175
 176 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
 177 {
 178     DeviceClass *dc = DEVICE_CLASS(klass);
 179     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 180
 181     k->is_bridge = 1;
 182     k->config_write = xio3130_downstream_write_config;
 183     k->realize = xio3130_downstream_realize;
 184     k->exit = xio3130_downstream_exitfn;
 185     k->vendor_id = PCI_VENDOR_ID_TI;
 186     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
 187     k->revision = XIO3130_REVISION;
 188     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 189     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
 190     dc->reset = xio3130_downstream_reset;
 191     dc->vmsd = &vmstate_xio3130_downstream;
 192     dc->props = xio3130_downstream_props;
 193 }
 194
 195 static const TypeInfo xio3130_downstream_info = {
 196     .name          = "xio3130-downstream",
 197     .parent        = TYPE_PCIE_SLOT,
 198     .class_init    = xio3130_downstream_class_init,
 199     .interfaces = (InterfaceInfo[]) {
 200         { INTERFACE_PCIE_DEVICE },
 201         { }
 202     },
 203 };
 204
 205 static void xio3130_downstream_register_types(void)
 206 {
 207     type_register_static(&xio3130_downstream_info);
 208 }
 209
 210 type_init(xio3130_downstream_register_types)