target-arm/kvm64.c

   1 /*
   2  * ARM implementation of KVM hooks, 64 bit specific code
   3  *
   4  * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "config-host.h"
  19 #include "qemu-common.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_arm.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "hw/arm/arm.h"
  27
  28 static inline void set_feature(uint64_t *features, int feature)
  29 {
  30     *features |= 1ULL << feature;
  31 }
  32
  33 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  34 {
  35     /* Identify the feature bits corresponding to the host CPU, and
  36      * fill out the ARMHostCPUClass fields accordingly. To do this
  37      * we have to create a scratch VM, create a single CPU inside it,
  38      * and then query that CPU for the relevant ID registers.
  39      * For AArch64 we currently don't care about ID registers at
  40      * all; we just want to know the CPU type.
  41      */
  42     int fdarray[3];
  43     uint64_t features = 0;
  44     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  45      * we know these will only support creating one kind of guest CPU,
  46      * which is its preferred CPU type. Fortunately these old kernels
  47      * support only a very limited number of CPUs.
  48      */
  49     static const uint32_t cpus_to_try[] = {
  50         KVM_ARM_TARGET_AEM_V8,
  51         KVM_ARM_TARGET_FOUNDATION_V8,
  52         KVM_ARM_TARGET_CORTEX_A57,
  53         QEMU_KVM_ARM_TARGET_NONE
  54     };
  55     struct kvm_vcpu_init init;
  56
  57     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  58         return false;
  59     }
  60
  61     ahcc->target = init.target;
  62     ahcc->dtb_compatible = "arm,arm-v8";
  63
  64     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  65
  66    /* We can assume any KVM supporting CPU is at least a v8
  67      * with VFPv4+Neon; this in turn implies most of the other
  68      * feature bits.
  69      */
  70     set_feature(&features, ARM_FEATURE_V8);
  71     set_feature(&features, ARM_FEATURE_VFP4);
  72     set_feature(&features, ARM_FEATURE_NEON);
  73     set_feature(&features, ARM_FEATURE_AARCH64);
  74
  75     ahcc->features = features;
  76
  77     return true;
  78 }
  79
  80 #define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFULL
  81 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
  82
  83 int kvm_arch_init_vcpu(CPUState *cs)
  84 {
  85     int ret;
  86     uint64_t mpidr;
  87     ARMCPU *cpu = ARM_CPU(cs);
  88
  89     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
  90         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
  91         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
  92         return -EINVAL;
  93     }
  94
  95     /* Determine init features for this CPU */
  96     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
  97     if (cpu->start_powered_off) {
  98         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
  99     }
 100     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 101         cpu->psci_version = 2;
 102         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 103     }
 104     if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 105         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
 106     }
 107
 108     /* Do KVM_ARM_VCPU_INIT ioctl */
 109     ret = kvm_arm_vcpu_init(cs);
 110     if (ret) {
 111         return ret;
 112     }
 113
 114     /*
 115      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 116      * Currently KVM has its own idea about MPIDR assignment, so we
 117      * override our defaults with what we get from KVM.
 118      */
 119     ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr);
 120     if (ret) {
 121         return ret;
 122     }
 123     cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
 124
 125     return kvm_arm_init_cpreg_list(cpu);
 126 }
 127
 128 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 129 {
 130     /* Return true if the regidx is a register we should synchronize
 131      * via the cpreg_tuples array (ie is not a core reg we sync by
 132      * hand in kvm_arch_get/put_registers())
 133      */
 134     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 135     case KVM_REG_ARM_CORE:
 136         return false;
 137     default:
 138         return true;
 139     }
 140 }
 141
 142 #define AARCH64_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 143                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 144
 145 #define AARCH64_SIMD_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
 146                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 147
 148 #define AARCH64_SIMD_CTRL_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
 149                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 150
 151 int kvm_arch_put_registers(CPUState *cs, int level)
 152 {
 153     struct kvm_one_reg reg;
 154     uint32_t fpr;
 155     uint64_t val;
 156     int i;
 157     int ret;
 158     unsigned int el;
 159
 160     ARMCPU *cpu = ARM_CPU(cs);
 161     CPUARMState *env = &cpu->env;
 162
 163     /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
 164      * AArch64 registers before pushing them out to 64-bit KVM.
 165      */
 166     if (!is_a64(env)) {
 167         aarch64_sync_32_to_64(env);
 168     }
 169
 170     for (i = 0; i < 31; i++) {
 171         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 172         reg.addr = (uintptr_t) &env->xregs[i];
 173         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 174         if (ret) {
 175             return ret;
 176         }
 177     }
 178
 179     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 180      * QEMU side we keep the current SP in xregs[31] as well.
 181      */
 182     aarch64_save_sp(env, 1);
 183
 184     reg.id = AARCH64_CORE_REG(regs.sp);
 185     reg.addr = (uintptr_t) &env->sp_el[0];
 186     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 187     if (ret) {
 188         return ret;
 189     }
 190
 191     reg.id = AARCH64_CORE_REG(sp_el1);
 192     reg.addr = (uintptr_t) &env->sp_el[1];
 193     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 194     if (ret) {
 195         return ret;
 196     }
 197
 198     /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
 199     if (is_a64(env)) {
 200         val = pstate_read(env);
 201     } else {
 202         val = cpsr_read(env);
 203     }
 204     reg.id = AARCH64_CORE_REG(regs.pstate);
 205     reg.addr = (uintptr_t) &val;
 206     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 207     if (ret) {
 208         return ret;
 209     }
 210
 211     reg.id = AARCH64_CORE_REG(regs.pc);
 212     reg.addr = (uintptr_t) &env->pc;
 213     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 214     if (ret) {
 215         return ret;
 216     }
 217
 218     reg.id = AARCH64_CORE_REG(elr_el1);
 219     reg.addr = (uintptr_t) &env->elr_el[1];
 220     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 221     if (ret) {
 222         return ret;
 223     }
 224
 225     /* Saved Program State Registers
 226      *
 227      * Before we restore from the banked_spsr[] array we need to
 228      * ensure that any modifications to env->spsr are correctly
 229      * reflected in the banks.
 230      */
 231     el = arm_current_el(env);
 232     if (el > 0 && !is_a64(env)) {
 233         i = bank_number(env->uncached_cpsr & CPSR_M);
 234         env->banked_spsr[i] = env->spsr;
 235     }
 236
 237     /* KVM 0-4 map to QEMU banks 1-5 */
 238     for (i = 0; i < KVM_NR_SPSR; i++) {
 239         reg.id = AARCH64_CORE_REG(spsr[i]);
 240         reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 241         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 242         if (ret) {
 243             return ret;
 244         }
 245     }
 246
 247     /* Advanced SIMD and FP registers
 248      * We map Qn = regs[2n+1]:regs[2n]
 249      */
 250     for (i = 0; i < 32; i++) {
 251         int rd = i << 1;
 252         uint64_t fp_val[2];
 253 #ifdef HOST_WORDS_BIGENDIAN
 254         fp_val[0] = env->vfp.regs[rd + 1];
 255         fp_val[1] = env->vfp.regs[rd];
 256 #else
 257         fp_val[1] = env->vfp.regs[rd + 1];
 258         fp_val[0] = env->vfp.regs[rd];
 259 #endif
 260         reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 261         reg.addr = (uintptr_t)(&fp_val);
 262         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 263         if (ret) {
 264             return ret;
 265         }
 266     }
 267
 268     reg.addr = (uintptr_t)(&fpr);
 269     fpr = vfp_get_fpsr(env);
 270     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 271     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 272     if (ret) {
 273         return ret;
 274     }
 275
 276     fpr = vfp_get_fpcr(env);
 277     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 278     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 279     if (ret) {
 280         return ret;
 281     }
 282
 283     if (!write_list_to_kvmstate(cpu)) {
 284         return EINVAL;
 285     }
 286
 287     kvm_arm_sync_mpstate_to_kvm(cpu);
 288
 289     return ret;
 290 }
 291
 292 int kvm_arch_get_registers(CPUState *cs)
 293 {
 294     struct kvm_one_reg reg;
 295     uint64_t val;
 296     uint32_t fpr;
 297     unsigned int el;
 298     int i;
 299     int ret;
 300
 301     ARMCPU *cpu = ARM_CPU(cs);
 302     CPUARMState *env = &cpu->env;
 303
 304     for (i = 0; i < 31; i++) {
 305         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 306         reg.addr = (uintptr_t) &env->xregs[i];
 307         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 308         if (ret) {
 309             return ret;
 310         }
 311     }
 312
 313     reg.id = AARCH64_CORE_REG(regs.sp);
 314     reg.addr = (uintptr_t) &env->sp_el[0];
 315     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 316     if (ret) {
 317         return ret;
 318     }
 319
 320     reg.id = AARCH64_CORE_REG(sp_el1);
 321     reg.addr = (uintptr_t) &env->sp_el[1];
 322     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 323     if (ret) {
 324         return ret;
 325     }
 326
 327     reg.id = AARCH64_CORE_REG(regs.pstate);
 328     reg.addr = (uintptr_t) &val;
 329     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 330     if (ret) {
 331         return ret;
 332     }
 333
 334     env->aarch64 = ((val & PSTATE_nRW) == 0);
 335     if (is_a64(env)) {
 336         pstate_write(env, val);
 337     } else {
 338         env->uncached_cpsr = val & CPSR_M;
 339         cpsr_write(env, val, 0xffffffff);
 340     }
 341
 342     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 343      * QEMU side we keep the current SP in xregs[31] as well.
 344      */
 345     aarch64_restore_sp(env, 1);
 346
 347     reg.id = AARCH64_CORE_REG(regs.pc);
 348     reg.addr = (uintptr_t) &env->pc;
 349     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 350     if (ret) {
 351         return ret;
 352     }
 353
 354     /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
 355      * incoming AArch64 regs received from 64-bit KVM.
 356      * We must perform this after all of the registers have been acquired from
 357      * the kernel.
 358      */
 359     if (!is_a64(env)) {
 360         aarch64_sync_64_to_32(env);
 361     }
 362
 363     reg.id = AARCH64_CORE_REG(elr_el1);
 364     reg.addr = (uintptr_t) &env->elr_el[1];
 365     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 366     if (ret) {
 367         return ret;
 368     }
 369
 370     /* Fetch the SPSR registers
 371      *
 372      * KVM SPSRs 0-4 map to QEMU banks 1-5
 373      */
 374     for (i = 0; i < KVM_NR_SPSR; i++) {
 375         reg.id = AARCH64_CORE_REG(spsr[i]);
 376         reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 377         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 378         if (ret) {
 379             return ret;
 380         }
 381     }
 382
 383     el = arm_current_el(env);
 384     if (el > 0 && !is_a64(env)) {
 385         i = bank_number(env->uncached_cpsr & CPSR_M);
 386         env->spsr = env->banked_spsr[i];
 387     }
 388
 389     /* Advanced SIMD and FP registers
 390      * We map Qn = regs[2n+1]:regs[2n]
 391      */
 392     for (i = 0; i < 32; i++) {
 393         uint64_t fp_val[2];
 394         reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 395         reg.addr = (uintptr_t)(&fp_val);
 396         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 397         if (ret) {
 398             return ret;
 399         } else {
 400             int rd = i << 1;
 401 #ifdef HOST_WORDS_BIGENDIAN
 402             env->vfp.regs[rd + 1] = fp_val[0];
 403             env->vfp.regs[rd] = fp_val[1];
 404 #else
 405             env->vfp.regs[rd + 1] = fp_val[1];
 406             env->vfp.regs[rd] = fp_val[0];
 407 #endif
 408         }
 409     }
 410
 411     reg.addr = (uintptr_t)(&fpr);
 412     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 413     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 414     if (ret) {
 415         return ret;
 416     }
 417     vfp_set_fpsr(env, fpr);
 418
 419     reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 420     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 421     if (ret) {
 422         return ret;
 423     }
 424     vfp_set_fpcr(env, fpr);
 425
 426     if (!write_kvmstate_to_list(cpu)) {
 427         return EINVAL;
 428     }
 429     /* Note that it's OK to have registers which aren't in CPUState,
 430      * so we can ignore a failure return here.
 431      */
 432     write_list_to_cpustate(cpu);
 433
 434     kvm_arm_sync_mpstate_to_qemu(cpu);
 435
 436     /* TODO: other registers */
 437     return ret;
 438 }