target-tilegx/cpu.h

   1 /*
   2  *  TILE-Gx virtual CPU header
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_TILEGX_H
  20 #define CPU_TILEGX_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 64
  26
  27 #define CPUArchState struct CPUTLGState
  28
  29 #include "exec/cpu-defs.h"
  30
  31
  32 /* TILE-Gx common register alias */
  33 #define TILEGX_R_RE    0   /*  0 register, for function/syscall return value */
  34 #define TILEGX_R_ERR   1   /*  1 register, for syscall errno flag */
  35 #define TILEGX_R_NR    10  /* 10 register, for syscall number */
  36 #define TILEGX_R_BP    52  /* 52 register, optional frame pointer */
  37 #define TILEGX_R_TP    53  /* TP register, thread local storage data */
  38 #define TILEGX_R_SP    54  /* SP register, stack pointer */
  39 #define TILEGX_R_LR    55  /* LR register, may save pc, but it is not pc */
  40 #define TILEGX_R_COUNT 56  /* Only 56 registers are really useful */
  41 #define TILEGX_R_SN    56  /* SN register, obsoleted, it likes zero register */
  42 #define TILEGX_R_IDN0  57  /* IDN0 register, cause IDN_ACCESS exception */
  43 #define TILEGX_R_IDN1  58  /* IDN1 register, cause IDN_ACCESS exception */
  44 #define TILEGX_R_UDN0  59  /* UDN0 register, cause UDN_ACCESS exception */
  45 #define TILEGX_R_UDN1  60  /* UDN1 register, cause UDN_ACCESS exception */
  46 #define TILEGX_R_UDN2  61  /* UDN2 register, cause UDN_ACCESS exception */
  47 #define TILEGX_R_UDN3  62  /* UDN3 register, cause UDN_ACCESS exception */
  48 #define TILEGX_R_ZERO  63  /* Zero register, always zero */
  49 #define TILEGX_R_NOREG 255 /* Invalid register value */
  50
  51 /* TILE-Gx special registers used by outside */
  52 enum {
  53     TILEGX_SPR_CMPEXCH = 0,
  54     TILEGX_SPR_CRITICAL_SEC = 1,
  55     TILEGX_SPR_SIM_CONTROL = 2,
  56     TILEGX_SPR_COUNT
  57 };
  58
  59 /* Exception numbers */
  60 typedef enum {
  61     TILEGX_EXCP_NONE = 0,
  62     TILEGX_EXCP_SYSCALL = 1,
  63     TILEGX_EXCP_SEGV = 2,
  64     TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
  65     TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
  66     TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
  67     TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
  68     TILEGX_EXCP_OPCODE_EXCH = 0x105,
  69     TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
  70     TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
  71     TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
  72     TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
  73     TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
  74     TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
  75     TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
  76     TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
  77     TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
  78     TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
  79     TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
  80     TILEGX_EXCP_UNALIGNMENT = 0x201,
  81     TILEGX_EXCP_DBUG_BREAK = 0x301
  82 } TileExcp;
  83
  84 typedef struct CPUTLGState {
  85     uint64_t regs[TILEGX_R_COUNT];     /* Common used registers by outside */
  86     uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
  87     uint64_t pc;                       /* Current pc */
  88
  89 #if defined(CONFIG_USER_ONLY)
  90     uint32_t excparam;                 /* exception parameter */
  91     uint64_t excaddr;                  /* exception address */
  92 #endif
  93
  94     CPU_COMMON
  95 } CPUTLGState;
  96
  97 #include "qom/cpu.h"
  98
  99 #define TYPE_TILEGX_CPU "tilegx-cpu"
 100
 101 #define TILEGX_CPU_CLASS(klass) \
 102     OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
 103 #define TILEGX_CPU(obj) \
 104     OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
 105 #define TILEGX_CPU_GET_CLASS(obj) \
 106     OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
 107
 108 /**
 109  * TileGXCPUClass:
 110  * @parent_realize: The parent class' realize handler.
 111  * @parent_reset: The parent class' reset handler.
 112  *
 113  * A Tile-Gx CPU model.
 114  */
 115 typedef struct TileGXCPUClass {
 116     /*< private >*/
 117     CPUClass parent_class;
 118     /*< public >*/
 119
 120     DeviceRealize parent_realize;
 121     void (*parent_reset)(CPUState *cpu);
 122 } TileGXCPUClass;
 123
 124 /**
 125  * TileGXCPU:
 126  * @env: #CPUTLGState
 127  *
 128  * A Tile-GX CPU.
 129  */
 130 typedef struct TileGXCPU {
 131     /*< private >*/
 132     CPUState parent_obj;
 133     /*< public >*/
 134
 135     CPUTLGState env;
 136 } TileGXCPU;
 137
 138 static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
 139 {
 140     return container_of(env, TileGXCPU, env);
 141 }
 142
 143 #define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
 144
 145 #define ENV_OFFSET offsetof(TileGXCPU, env)
 146
 147 /* TILE-Gx memory attributes */
 148 #define TARGET_PAGE_BITS 16  /* TILE-Gx uses 64KB page size */
 149 #define TARGET_PHYS_ADDR_SPACE_BITS 42
 150 #define TARGET_VIRT_ADDR_SPACE_BITS 64
 151 #define MMU_USER_IDX    0  /* Current memory operation is in user mode */
 152
 153 #include "exec/cpu-all.h"
 154
 155 void tilegx_tcg_init(void);
 156 int cpu_tilegx_exec(CPUState *s);
 157 int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
 158
 159 TileGXCPU *cpu_tilegx_init(const char *cpu_model);
 160
 161 #define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
 162
 163 #define cpu_exec cpu_tilegx_exec
 164 #define cpu_gen_code cpu_tilegx_gen_code
 165 #define cpu_signal_handler cpu_tilegx_signal_handler
 166
 167 static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
 168                                         target_ulong *cs_base, int *flags)
 169 {
 170     *pc = env->pc;
 171     *cs_base = 0;
 172     *flags = 0;
 173 }
 174
 175 #include "exec/exec-all.h"
 176
 177 #endif