hw/i386/microvm.c

   1 /*
   2  * Copyright (c) 2018 Intel Corporation
   3  * Copyright (c) 2019 Red Hat, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2 or later, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/cutils.h"
  21 #include "qemu/units.h"
  22 #include "qapi/error.h"
  23 #include "qapi/visitor.h"
  24 #include "qapi/qapi-visit-common.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/cpus.h"
  27 #include "sysemu/numa.h"
  28 #include "sysemu/reset.h"
  29 #include "sysemu/runstate.h"
  30 #include "acpi-microvm.h"
  31
  32 #include "hw/loader.h"
  33 #include "hw/irq.h"
  34 #include "hw/kvm/clock.h"
  35 #include "hw/i386/microvm.h"
  36 #include "hw/i386/x86.h"
  37 #include "target/i386/cpu.h"
  38 #include "hw/intc/i8259.h"
  39 #include "hw/timer/i8254.h"
  40 #include "hw/rtc/mc146818rtc.h"
  41 #include "hw/char/serial.h"
  42 #include "hw/display/ramfb.h"
  43 #include "hw/i386/topology.h"
  44 #include "hw/i386/e820_memory_layout.h"
  45 #include "hw/i386/fw_cfg.h"
  46 #include "hw/virtio/virtio-mmio.h"
  47 #include "hw/acpi/acpi.h"
  48 #include "hw/acpi/generic_event_device.h"
  49 #include "hw/pci-host/gpex.h"
  50 #include "hw/usb/xhci.h"
  51
  52 #include "cpu.h"
  53 #include "elf.h"
  54 #include "kvm_i386.h"
  55 #include "hw/xen/start_info.h"
  56
  57 #define MICROVM_QBOOT_FILENAME "qboot.rom"
  58 #define MICROVM_BIOS_FILENAME  "bios-microvm.bin"
  59
  60 static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
  61 {
  62     X86MachineState *x86ms = X86_MACHINE(mms);
  63     int val;
  64
  65     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
  66     rtc_set_memory(s, 0x15, val);
  67     rtc_set_memory(s, 0x16, val >> 8);
  68     /* extended memory (next 64MiB) */
  69     if (x86ms->below_4g_mem_size > 1 * MiB) {
  70         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
  71     } else {
  72         val = 0;
  73     }
  74     if (val > 65535) {
  75         val = 65535;
  76     }
  77     rtc_set_memory(s, 0x17, val);
  78     rtc_set_memory(s, 0x18, val >> 8);
  79     rtc_set_memory(s, 0x30, val);
  80     rtc_set_memory(s, 0x31, val >> 8);
  81     /* memory between 16MiB and 4GiB */
  82     if (x86ms->below_4g_mem_size > 16 * MiB) {
  83         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
  84     } else {
  85         val = 0;
  86     }
  87     if (val > 65535) {
  88         val = 65535;
  89     }
  90     rtc_set_memory(s, 0x34, val);
  91     rtc_set_memory(s, 0x35, val >> 8);
  92     /* memory above 4GiB */
  93     val = x86ms->above_4g_mem_size / 65536;
  94     rtc_set_memory(s, 0x5b, val);
  95     rtc_set_memory(s, 0x5c, val >> 8);
  96     rtc_set_memory(s, 0x5d, val >> 16);
  97 }
  98
  99 static void microvm_gsi_handler(void *opaque, int n, int level)
 100 {
 101     GSIState *s = opaque;
 102
 103     qemu_set_irq(s->ioapic_irq[n], level);
 104 }
 105
 106 static void create_gpex(MicrovmMachineState *mms)
 107 {
 108     X86MachineState *x86ms = X86_MACHINE(mms);
 109     MemoryRegion *mmio32_alias;
 110     MemoryRegion *mmio64_alias;
 111     MemoryRegion *mmio_reg;
 112     MemoryRegion *ecam_alias;
 113     MemoryRegion *ecam_reg;
 114     DeviceState *dev;
 115     int i;
 116
 117     dev = qdev_new(TYPE_GPEX_HOST);
 118     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 119
 120     /* Map only the first size_ecam bytes of ECAM space */
 121     ecam_alias = g_new0(MemoryRegion, 1);
 122     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 123     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 124                              ecam_reg, 0, mms->gpex.ecam.size);
 125     memory_region_add_subregion(get_system_memory(),
 126                                 mms->gpex.ecam.base, ecam_alias);
 127
 128     /* Map the MMIO window into system address space so as to expose
 129      * the section of PCI MMIO space which starts at the same base address
 130      * (ie 1:1 mapping for that part of PCI MMIO space visible through
 131      * the window).
 132      */
 133     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 134     if (mms->gpex.mmio32.size) {
 135         mmio32_alias = g_new0(MemoryRegion, 1);
 136         memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg,
 137                                  mms->gpex.mmio32.base, mms->gpex.mmio32.size);
 138         memory_region_add_subregion(get_system_memory(),
 139                                     mms->gpex.mmio32.base, mmio32_alias);
 140     }
 141     if (mms->gpex.mmio64.size) {
 142         mmio64_alias = g_new0(MemoryRegion, 1);
 143         memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg,
 144                                  mms->gpex.mmio64.base, mms->gpex.mmio64.size);
 145         memory_region_add_subregion(get_system_memory(),
 146                                     mms->gpex.mmio64.base, mmio64_alias);
 147     }
 148
 149     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 150         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 151                            x86ms->gsi[mms->gpex.irq + i]);
 152     }
 153 }
 154
 155 static void microvm_devices_init(MicrovmMachineState *mms)
 156 {
 157     X86MachineState *x86ms = X86_MACHINE(mms);
 158     ISABus *isa_bus;
 159     ISADevice *rtc_state;
 160     GSIState *gsi_state;
 161     int i;
 162
 163     /* Core components */
 164
 165     gsi_state = g_malloc0(sizeof(*gsi_state));
 166     if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
 167         x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 168     } else {
 169         x86ms->gsi = qemu_allocate_irqs(microvm_gsi_handler,
 170                                         gsi_state, GSI_NUM_PINS);
 171     }
 172
 173     isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
 174                           &error_abort);
 175     isa_bus_irqs(isa_bus, x86ms->gsi);
 176
 177     ioapic_init_gsi(gsi_state, "machine");
 178
 179     kvmclock_create(true);
 180
 181     mms->virtio_irq_base = 5;
 182     mms->virtio_num_transports = 8;
 183     if (x86_machine_is_acpi_enabled(x86ms)) {
 184         mms->virtio_irq_base = 16;
 185     }
 186
 187     for (i = 0; i < mms->virtio_num_transports; i++) {
 188         sysbus_create_simple("virtio-mmio",
 189                              VIRTIO_MMIO_BASE + i * 512,
 190                              x86ms->gsi[mms->virtio_irq_base + i]);
 191     }
 192
 193     /* Optional and legacy devices */
 194     if (x86_machine_is_acpi_enabled(x86ms)) {
 195         DeviceState *dev = qdev_new(TYPE_ACPI_GED_X86);
 196         qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT);
 197         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE);
 198         /* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */
 199         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, GED_MMIO_BASE_REGS);
 200         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 201                            x86ms->gsi[GED_MMIO_IRQ]);
 202         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 203         x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
 204     }
 205
 206     if (x86_machine_is_acpi_enabled(x86ms) && machine_usb(MACHINE(mms))) {
 207         DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
 208         qdev_prop_set_uint32(dev, "intrs", 1);
 209         qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
 210         qdev_prop_set_uint32(dev, "p2", 8);
 211         qdev_prop_set_uint32(dev, "p3", 8);
 212         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 213         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MICROVM_XHCI_BASE);
 214         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 215                            x86ms->gsi[MICROVM_XHCI_IRQ]);
 216     }
 217
 218     if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
 219         /* use topmost 25% of the address space available */
 220         hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
 221         if (phys_size > 0x1000000ll) {
 222             mms->gpex.mmio64.size = phys_size / 4;
 223             mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
 224         }
 225         mms->gpex.mmio32.base = PCIE_MMIO_BASE;
 226         mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
 227         mms->gpex.ecam.base   = PCIE_ECAM_BASE;
 228         mms->gpex.ecam.size   = PCIE_ECAM_SIZE;
 229         mms->gpex.irq         = PCIE_IRQ_BASE;
 230         create_gpex(mms);
 231         x86ms->pci_irq_mask = ((1 << (PCIE_IRQ_BASE + 0)) |
 232                                (1 << (PCIE_IRQ_BASE + 1)) |
 233                                (1 << (PCIE_IRQ_BASE + 2)) |
 234                                (1 << (PCIE_IRQ_BASE + 3)));
 235     } else {
 236         x86ms->pci_irq_mask = 0;
 237     }
 238
 239     if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
 240         qemu_irq *i8259;
 241
 242         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
 243         for (i = 0; i < ISA_NUM_IRQS; i++) {
 244             gsi_state->i8259_irq[i] = i8259[i];
 245         }
 246         g_free(i8259);
 247     }
 248
 249     if (mms->pit == ON_OFF_AUTO_ON || mms->pit == ON_OFF_AUTO_AUTO) {
 250         if (kvm_pit_in_kernel()) {
 251             kvm_pit_init(isa_bus, 0x40);
 252         } else {
 253             i8254_pit_init(isa_bus, 0x40, 0, NULL);
 254         }
 255     }
 256
 257     if (mms->rtc == ON_OFF_AUTO_ON ||
 258         (mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
 259         rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
 260         microvm_set_rtc(mms, rtc_state);
 261     }
 262
 263     if (mms->isa_serial) {
 264         serial_hds_isa_init(isa_bus, 0, 1);
 265     }
 266
 267     if (bios_name == NULL) {
 268         bios_name = x86_machine_is_acpi_enabled(x86ms)
 269             ? MICROVM_BIOS_FILENAME
 270             : MICROVM_QBOOT_FILENAME;
 271     }
 272     x86_bios_rom_init(get_system_memory(), true);
 273 }
 274
 275 static void microvm_memory_init(MicrovmMachineState *mms)
 276 {
 277     MachineState *machine = MACHINE(mms);
 278     X86MachineState *x86ms = X86_MACHINE(mms);
 279     MemoryRegion *ram_below_4g, *ram_above_4g;
 280     MemoryRegion *system_memory = get_system_memory();
 281     FWCfgState *fw_cfg;
 282     ram_addr_t lowmem = 0xc0000000; /* 3G */
 283     int i;
 284
 285     if (machine->ram_size > lowmem) {
 286         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 287         x86ms->below_4g_mem_size = lowmem;
 288     } else {
 289         x86ms->above_4g_mem_size = 0;
 290         x86ms->below_4g_mem_size = machine->ram_size;
 291     }
 292
 293     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 294     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
 295                              0, x86ms->below_4g_mem_size);
 296     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 297
 298     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
 299
 300     if (x86ms->above_4g_mem_size > 0) {
 301         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 302         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
 303                                  machine->ram,
 304                                  x86ms->below_4g_mem_size,
 305                                  x86ms->above_4g_mem_size);
 306         memory_region_add_subregion(system_memory, 0x100000000ULL,
 307                                     ram_above_4g);
 308         e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
 309     }
 310
 311     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 312                                 &address_space_memory);
 313
 314     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus);
 315     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus);
 316     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 317     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
 318     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 319                      &e820_reserve, sizeof(e820_reserve));
 320     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 321                     sizeof(struct e820_entry) * e820_get_num_entries());
 322
 323     rom_set_fw(fw_cfg);
 324
 325     if (machine->kernel_filename != NULL) {
 326         x86_load_linux(x86ms, fw_cfg, 0, true, true);
 327     }
 328
 329     if (mms->option_roms) {
 330         for (i = 0; i < nb_option_roms; i++) {
 331             rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 332         }
 333     }
 334
 335     x86ms->fw_cfg = fw_cfg;
 336     x86ms->ioapic_as = &address_space_memory;
 337 }
 338
 339 static gchar *microvm_get_mmio_cmdline(gchar *name, uint32_t virtio_irq_base)
 340 {
 341     gchar *cmdline;
 342     gchar *separator;
 343     long int index;
 344     int ret;
 345
 346     separator = g_strrstr(name, ".");
 347     if (!separator) {
 348         return NULL;
 349     }
 350
 351     if (qemu_strtol(separator + 1, NULL, 10, &index) != 0) {
 352         return NULL;
 353     }
 354
 355     cmdline = g_malloc0(VIRTIO_CMDLINE_MAXLEN);
 356     ret = g_snprintf(cmdline, VIRTIO_CMDLINE_MAXLEN,
 357                      " virtio_mmio.device=512@0x%lx:%ld",
 358                      VIRTIO_MMIO_BASE + index * 512,
 359                      virtio_irq_base + index);
 360     if (ret < 0 || ret >= VIRTIO_CMDLINE_MAXLEN) {
 361         g_free(cmdline);
 362         return NULL;
 363     }
 364
 365     return cmdline;
 366 }
 367
 368 static void microvm_fix_kernel_cmdline(MachineState *machine)
 369 {
 370     X86MachineState *x86ms = X86_MACHINE(machine);
 371     MicrovmMachineState *mms = MICROVM_MACHINE(machine);
 372     BusState *bus;
 373     BusChild *kid;
 374     char *cmdline;
 375
 376     /*
 377      * Find MMIO transports with attached devices, and add them to the kernel
 378      * command line.
 379      *
 380      * Yes, this is a hack, but one that heavily improves the UX without
 381      * introducing any significant issues.
 382      */
 383     cmdline = g_strdup(machine->kernel_cmdline);
 384     bus = sysbus_get_default();
 385     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 386         DeviceState *dev = kid->child;
 387         ObjectClass *class = object_get_class(OBJECT(dev));
 388
 389         if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) {
 390             VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
 391             VirtioBusState *mmio_virtio_bus = &mmio->bus;
 392             BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
 393
 394             if (!QTAILQ_EMPTY(&mmio_bus->children)) {
 395                 gchar *mmio_cmdline = microvm_get_mmio_cmdline
 396                     (mmio_bus->name, mms->virtio_irq_base);
 397                 if (mmio_cmdline) {
 398                     char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
 399                     g_free(mmio_cmdline);
 400                     g_free(cmdline);
 401                     cmdline = newcmd;
 402                 }
 403             }
 404         }
 405     }
 406
 407     fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
 408     fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
 409
 410     g_free(cmdline);
 411 }
 412
 413 static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
 414                                        DeviceState *dev, Error **errp)
 415 {
 416     X86CPU *cpu = X86_CPU(dev);
 417
 418     cpu->host_phys_bits = true; /* need reliable phys-bits */
 419     x86_cpu_pre_plug(hotplug_dev, dev, errp);
 420 }
 421
 422 static void microvm_device_plug_cb(HotplugHandler *hotplug_dev,
 423                                    DeviceState *dev, Error **errp)
 424 {
 425     x86_cpu_plug(hotplug_dev, dev, errp);
 426 }
 427
 428 static void microvm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 429                                              DeviceState *dev, Error **errp)
 430 {
 431     error_setg(errp, "unplug not supported by microvm");
 432 }
 433
 434 static void microvm_device_unplug_cb(HotplugHandler *hotplug_dev,
 435                                      DeviceState *dev, Error **errp)
 436 {
 437     error_setg(errp, "unplug not supported by microvm");
 438 }
 439
 440 static HotplugHandler *microvm_get_hotplug_handler(MachineState *machine,
 441                                                    DeviceState *dev)
 442 {
 443     if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 444         return HOTPLUG_HANDLER(machine);
 445     }
 446     return NULL;
 447 }
 448
 449 static void microvm_machine_state_init(MachineState *machine)
 450 {
 451     MicrovmMachineState *mms = MICROVM_MACHINE(machine);
 452     X86MachineState *x86ms = X86_MACHINE(machine);
 453     Error *local_err = NULL;
 454
 455     microvm_memory_init(mms);
 456
 457     x86_cpus_init(x86ms, CPU_VERSION_LATEST);
 458     if (local_err) {
 459         error_report_err(local_err);
 460         exit(1);
 461     }
 462
 463     microvm_devices_init(mms);
 464 }
 465
 466 static void microvm_machine_reset(MachineState *machine)
 467 {
 468     MicrovmMachineState *mms = MICROVM_MACHINE(machine);
 469     CPUState *cs;
 470     X86CPU *cpu;
 471
 472     if (!x86_machine_is_acpi_enabled(X86_MACHINE(machine)) &&
 473         machine->kernel_filename != NULL &&
 474         mms->auto_kernel_cmdline && !mms->kernel_cmdline_fixed) {
 475         microvm_fix_kernel_cmdline(machine);
 476         mms->kernel_cmdline_fixed = true;
 477     }
 478
 479     qemu_devices_reset();
 480
 481     CPU_FOREACH(cs) {
 482         cpu = X86_CPU(cs);
 483
 484         if (cpu->apic_state) {
 485             device_legacy_reset(cpu->apic_state);
 486         }
 487     }
 488 }
 489
 490 static void microvm_machine_get_pic(Object *obj, Visitor *v, const char *name,
 491                                     void *opaque, Error **errp)
 492 {
 493     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 494     OnOffAuto pic = mms->pic;
 495
 496     visit_type_OnOffAuto(v, name, &pic, errp);
 497 }
 498
 499 static void microvm_machine_set_pic(Object *obj, Visitor *v, const char *name,
 500                                     void *opaque, Error **errp)
 501 {
 502     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 503
 504     visit_type_OnOffAuto(v, name, &mms->pic, errp);
 505 }
 506
 507 static void microvm_machine_get_pit(Object *obj, Visitor *v, const char *name,
 508                                     void *opaque, Error **errp)
 509 {
 510     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 511     OnOffAuto pit = mms->pit;
 512
 513     visit_type_OnOffAuto(v, name, &pit, errp);
 514 }
 515
 516 static void microvm_machine_set_pit(Object *obj, Visitor *v, const char *name,
 517                                     void *opaque, Error **errp)
 518 {
 519     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 520
 521     visit_type_OnOffAuto(v, name, &mms->pit, errp);
 522 }
 523
 524 static void microvm_machine_get_rtc(Object *obj, Visitor *v, const char *name,
 525                                     void *opaque, Error **errp)
 526 {
 527     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 528     OnOffAuto rtc = mms->rtc;
 529
 530     visit_type_OnOffAuto(v, name, &rtc, errp);
 531 }
 532
 533 static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
 534                                     void *opaque, Error **errp)
 535 {
 536     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 537
 538     visit_type_OnOffAuto(v, name, &mms->rtc, errp);
 539 }
 540
 541 static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name,
 542                                      void *opaque, Error **errp)
 543 {
 544     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 545     OnOffAuto pcie = mms->pcie;
 546
 547     visit_type_OnOffAuto(v, name, &pcie, errp);
 548 }
 549
 550 static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name,
 551                                      void *opaque, Error **errp)
 552 {
 553     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 554
 555     visit_type_OnOffAuto(v, name, &mms->pcie, errp);
 556 }
 557
 558 static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
 559 {
 560     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 561
 562     return mms->isa_serial;
 563 }
 564
 565 static void microvm_machine_set_isa_serial(Object *obj, bool value,
 566                                            Error **errp)
 567 {
 568     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 569
 570     mms->isa_serial = value;
 571 }
 572
 573 static bool microvm_machine_get_option_roms(Object *obj, Error **errp)
 574 {
 575     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 576
 577     return mms->option_roms;
 578 }
 579
 580 static void microvm_machine_set_option_roms(Object *obj, bool value,
 581                                             Error **errp)
 582 {
 583     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 584
 585     mms->option_roms = value;
 586 }
 587
 588 static bool microvm_machine_get_auto_kernel_cmdline(Object *obj, Error **errp)
 589 {
 590     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 591
 592     return mms->auto_kernel_cmdline;
 593 }
 594
 595 static void microvm_machine_set_auto_kernel_cmdline(Object *obj, bool value,
 596                                                     Error **errp)
 597 {
 598     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 599
 600     mms->auto_kernel_cmdline = value;
 601 }
 602
 603 static void microvm_machine_done(Notifier *notifier, void *data)
 604 {
 605     MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
 606                                             machine_done);
 607
 608     acpi_setup_microvm(mms);
 609 }
 610
 611 static void microvm_powerdown_req(Notifier *notifier, void *data)
 612 {
 613     MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
 614                                             powerdown_req);
 615     X86MachineState *x86ms = X86_MACHINE(mms);
 616
 617     if (x86ms->acpi_dev) {
 618         Object *obj = OBJECT(x86ms->acpi_dev);
 619         AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(obj);
 620         adevc->send_event(ACPI_DEVICE_IF(x86ms->acpi_dev),
 621                           ACPI_POWER_DOWN_STATUS);
 622     }
 623 }
 624
 625 static void microvm_machine_initfn(Object *obj)
 626 {
 627     MicrovmMachineState *mms = MICROVM_MACHINE(obj);
 628
 629     /* Configuration */
 630     mms->pic = ON_OFF_AUTO_AUTO;
 631     mms->pit = ON_OFF_AUTO_AUTO;
 632     mms->rtc = ON_OFF_AUTO_AUTO;
 633     mms->pcie = ON_OFF_AUTO_AUTO;
 634     mms->isa_serial = true;
 635     mms->option_roms = true;
 636     mms->auto_kernel_cmdline = true;
 637
 638     /* State */
 639     mms->kernel_cmdline_fixed = false;
 640
 641     mms->machine_done.notify = microvm_machine_done;
 642     qemu_add_machine_init_done_notifier(&mms->machine_done);
 643     mms->powerdown_req.notify = microvm_powerdown_req;
 644     qemu_register_powerdown_notifier(&mms->powerdown_req);
 645 }
 646
 647 static void microvm_class_init(ObjectClass *oc, void *data)
 648 {
 649     MachineClass *mc = MACHINE_CLASS(oc);
 650     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 651
 652     mc->init = microvm_machine_state_init;
 653
 654     mc->family = "microvm_i386";
 655     mc->desc = "microvm (i386)";
 656     mc->units_per_default_bus = 1;
 657     mc->no_floppy = 1;
 658     mc->max_cpus = 288;
 659     mc->has_hotpluggable_cpus = false;
 660     mc->auto_enable_numa_with_memhp = false;
 661     mc->auto_enable_numa_with_memdev = false;
 662     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
 663     mc->nvdimm_supported = false;
 664     mc->default_ram_id = "microvm.ram";
 665
 666     /* Avoid relying too much on kernel components */
 667     mc->default_kernel_irqchip_split = true;
 668
 669     /* Machine class handlers */
 670     mc->reset = microvm_machine_reset;
 671
 672     /* hotplug (for cpu coldplug) */
 673     mc->get_hotplug_handler = microvm_get_hotplug_handler;
 674     hc->pre_plug = microvm_device_pre_plug_cb;
 675     hc->plug = microvm_device_plug_cb;
 676     hc->unplug_request = microvm_device_unplug_request_cb;
 677     hc->unplug = microvm_device_unplug_cb;
 678
 679     object_class_property_add(oc, MICROVM_MACHINE_PIC, "OnOffAuto",
 680                               microvm_machine_get_pic,
 681                               microvm_machine_set_pic,
 682                               NULL, NULL);
 683     object_class_property_set_description(oc, MICROVM_MACHINE_PIC,
 684         "Enable i8259 PIC");
 685
 686     object_class_property_add(oc, MICROVM_MACHINE_PIT, "OnOffAuto",
 687                               microvm_machine_get_pit,
 688                               microvm_machine_set_pit,
 689                               NULL, NULL);
 690     object_class_property_set_description(oc, MICROVM_MACHINE_PIT,
 691         "Enable i8254 PIT");
 692
 693     object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto",
 694                               microvm_machine_get_rtc,
 695                               microvm_machine_set_rtc,
 696                               NULL, NULL);
 697     object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
 698         "Enable MC146818 RTC");
 699
 700     object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto",
 701                               microvm_machine_get_pcie,
 702                               microvm_machine_set_pcie,
 703                               NULL, NULL);
 704     object_class_property_set_description(oc, MICROVM_MACHINE_PCIE,
 705         "Enable PCIe");
 706
 707     object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
 708                                    microvm_machine_get_isa_serial,
 709                                    microvm_machine_set_isa_serial);
 710     object_class_property_set_description(oc, MICROVM_MACHINE_ISA_SERIAL,
 711         "Set off to disable the instantiation an ISA serial port");
 712
 713     object_class_property_add_bool(oc, MICROVM_MACHINE_OPTION_ROMS,
 714                                    microvm_machine_get_option_roms,
 715                                    microvm_machine_set_option_roms);
 716     object_class_property_set_description(oc, MICROVM_MACHINE_OPTION_ROMS,
 717         "Set off to disable loading option ROMs");
 718
 719     object_class_property_add_bool(oc, MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
 720                                    microvm_machine_get_auto_kernel_cmdline,
 721                                    microvm_machine_set_auto_kernel_cmdline);
 722     object_class_property_set_description(oc,
 723         MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
 724         "Set off to disable adding virtio-mmio devices to the kernel cmdline");
 725
 726     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 727 }
 728
 729 static const TypeInfo microvm_machine_info = {
 730     .name          = TYPE_MICROVM_MACHINE,
 731     .parent        = TYPE_X86_MACHINE,
 732     .instance_size = sizeof(MicrovmMachineState),
 733     .instance_init = microvm_machine_initfn,
 734     .class_size    = sizeof(MicrovmMachineClass),
 735     .class_init    = microvm_class_init,
 736     .interfaces = (InterfaceInfo[]) {
 737          { TYPE_HOTPLUG_HANDLER },
 738          { }
 739     },
 740 };
 741
 742 static void microvm_machine_init(void)
 743 {
 744     type_register_static(&microvm_machine_info);
 745 }
 746 type_init(microvm_machine_init);