2 * QEMU CG3 Frame buffer
4 * Copyright (c) 2012 Bob Breuer
5 * Copyright (c) 2013 Mark Cave-Ayland
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "ui/console.h"
31 #include "hw/sysbus.h"
32 #include "hw/loader.h"
34 #include "qemu/module.h"
36 /* Change to 1 to enable debugging */
39 #define CG3_ROM_FILE "QEMU,cgthree.bin"
40 #define FCODE_MAX_ROM_SIZE 0x10000
42 #define CG3_REG_SIZE 0x20
44 #define CG3_REG_BT458_ADDR 0x0
45 #define CG3_REG_BT458_COLMAP 0x4
46 #define CG3_REG_FBC_CTRL 0x10
47 #define CG3_REG_FBC_STATUS 0x11
48 #define CG3_REG_FBC_CURSTART 0x12
49 #define CG3_REG_FBC_CUREND 0x13
50 #define CG3_REG_FBC_VCTRL 0x14
52 /* Control register flags */
53 #define CG3_CR_ENABLE_INTS 0x80
55 /* Status register flags */
56 #define CG3_SR_PENDING_INT 0x80
57 #define CG3_SR_1152_900_76_B 0x60
58 #define CG3_SR_ID_COLOR 0x01
60 #define CG3_VRAM_SIZE 0x100000
61 #define CG3_VRAM_OFFSET 0x800000
63 #define DPRINTF(fmt, ...) do { \
65 printf("CG3: " fmt , ## __VA_ARGS__); \
69 #define TYPE_CG3 "cgthree"
70 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
72 typedef struct CG3State
{
73 SysBusDevice parent_obj
;
78 MemoryRegion vram_mem
;
84 uint8_t r
[256], g
[256], b
[256];
85 uint16_t width
, height
, depth
;
86 uint8_t dac_index
, dac_state
;
89 static void cg3_update_display(void *opaque
)
92 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
97 unsigned int width
, height
;
99 DirtyBitmapSnapshot
*snap
= NULL
;
101 if (surface_bits_per_pixel(surface
) != 32) {
108 pix
= memory_region_get_ram_ptr(&s
->vram_mem
);
109 data
= (uint32_t *)surface_data(surface
);
111 if (!s
->full_update
) {
112 snap
= memory_region_snapshot_and_clear_dirty(&s
->vram_mem
, 0x0,
113 memory_region_size(&s
->vram_mem
),
117 for (y
= 0; y
< height
; y
++) {
120 page
= (ram_addr_t
)y
* width
;
122 if (s
->full_update
) {
125 update
= memory_region_snapshot_get_dirty(&s
->vram_mem
, snap
, page
,
134 for (x
= 0; x
< width
; x
++) {
136 dval
= (s
->r
[dval
] << 16) | (s
->g
[dval
] << 8) | s
->b
[dval
];
141 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
150 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
152 /* vsync interrupt? */
153 if (s
->regs
[0] & CG3_CR_ENABLE_INTS
) {
154 s
->regs
[1] |= CG3_SR_PENDING_INT
;
155 qemu_irq_raise(s
->irq
);
160 static void cg3_invalidate_display(void *opaque
)
162 CG3State
*s
= opaque
;
164 memory_region_set_dirty(&s
->vram_mem
, 0, CG3_VRAM_SIZE
);
167 static uint64_t cg3_reg_read(void *opaque
, hwaddr addr
, unsigned size
)
169 CG3State
*s
= opaque
;
173 case CG3_REG_BT458_ADDR
:
174 case CG3_REG_BT458_COLMAP
:
177 case CG3_REG_FBC_CTRL
:
180 case CG3_REG_FBC_STATUS
:
181 /* monitor ID 6, board type = 1 (color) */
182 val
= s
->regs
[1] | CG3_SR_1152_900_76_B
| CG3_SR_ID_COLOR
;
184 case CG3_REG_FBC_CURSTART
... CG3_REG_SIZE
- 1:
185 val
= s
->regs
[addr
- 0x10];
188 qemu_log_mask(LOG_UNIMP
,
189 "cg3: Unimplemented register read "
190 "reg 0x%" HWADDR_PRIx
" size 0x%x\n",
195 DPRINTF("read %02x from reg %" HWADDR_PRIx
"\n", val
, addr
);
199 static void cg3_reg_write(void *opaque
, hwaddr addr
, uint64_t val
,
202 CG3State
*s
= opaque
;
206 DPRINTF("write %" PRIx64
" to reg %" HWADDR_PRIx
" size %d\n",
210 case CG3_REG_BT458_ADDR
:
214 case CG3_REG_BT458_COLMAP
:
215 /* This register can be written to as either a long word or a byte */
220 for (i
= 0; i
< size
; i
++) {
223 switch (s
->dac_state
) {
225 s
->r
[s
->dac_index
] = regval
;
229 s
->g
[s
->dac_index
] = regval
;
233 s
->b
[s
->dac_index
] = regval
;
234 /* Index autoincrement */
235 s
->dac_index
= (s
->dac_index
+ 1) & 0xff;
245 case CG3_REG_FBC_CTRL
:
248 case CG3_REG_FBC_STATUS
:
249 if (s
->regs
[1] & CG3_SR_PENDING_INT
) {
250 /* clear interrupt */
251 s
->regs
[1] &= ~CG3_SR_PENDING_INT
;
252 qemu_irq_lower(s
->irq
);
255 case CG3_REG_FBC_CURSTART
... CG3_REG_SIZE
- 1:
256 s
->regs
[addr
- 0x10] = val
;
259 qemu_log_mask(LOG_UNIMP
,
260 "cg3: Unimplemented register write "
261 "reg 0x%" HWADDR_PRIx
" size 0x%x value 0x%" PRIx64
"\n",
267 static const MemoryRegionOps cg3_reg_ops
= {
268 .read
= cg3_reg_read
,
269 .write
= cg3_reg_write
,
270 .endianness
= DEVICE_NATIVE_ENDIAN
,
272 .min_access_size
= 1,
273 .max_access_size
= 4,
277 static const GraphicHwOps cg3_ops
= {
278 .invalidate
= cg3_invalidate_display
,
279 .gfx_update
= cg3_update_display
,
282 static void cg3_initfn(Object
*obj
)
284 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
285 CG3State
*s
= CG3(obj
);
287 memory_region_init_ram_nomigrate(&s
->rom
, obj
, "cg3.prom", FCODE_MAX_ROM_SIZE
,
289 memory_region_set_readonly(&s
->rom
, true);
290 sysbus_init_mmio(sbd
, &s
->rom
);
292 memory_region_init_io(&s
->reg
, obj
, &cg3_reg_ops
, s
, "cg3.reg",
294 sysbus_init_mmio(sbd
, &s
->reg
);
297 static void cg3_realizefn(DeviceState
*dev
, Error
**errp
)
299 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
300 CG3State
*s
= CG3(dev
);
302 char *fcode_filename
;
305 vmstate_register_ram_global(&s
->rom
);
306 fcode_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, CG3_ROM_FILE
);
307 if (fcode_filename
) {
308 ret
= load_image_mr(fcode_filename
, &s
->rom
);
309 g_free(fcode_filename
);
310 if (ret
< 0 || ret
> FCODE_MAX_ROM_SIZE
) {
311 warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE
);
315 memory_region_init_ram(&s
->vram_mem
, NULL
, "cg3.vram", s
->vram_size
,
317 memory_region_set_log(&s
->vram_mem
, true, DIRTY_MEMORY_VGA
);
318 sysbus_init_mmio(sbd
, &s
->vram_mem
);
320 sysbus_init_irq(sbd
, &s
->irq
);
322 s
->con
= graphic_console_init(DEVICE(dev
), 0, &cg3_ops
, s
);
323 qemu_console_resize(s
->con
, s
->width
, s
->height
);
326 static int vmstate_cg3_post_load(void *opaque
, int version_id
)
328 CG3State
*s
= opaque
;
330 cg3_invalidate_display(s
);
335 static const VMStateDescription vmstate_cg3
= {
338 .minimum_version_id
= 1,
339 .post_load
= vmstate_cg3_post_load
,
340 .fields
= (VMStateField
[]) {
341 VMSTATE_UINT16(height
, CG3State
),
342 VMSTATE_UINT16(width
, CG3State
),
343 VMSTATE_UINT16(depth
, CG3State
),
344 VMSTATE_BUFFER(r
, CG3State
),
345 VMSTATE_BUFFER(g
, CG3State
),
346 VMSTATE_BUFFER(b
, CG3State
),
347 VMSTATE_UINT8(dac_index
, CG3State
),
348 VMSTATE_UINT8(dac_state
, CG3State
),
349 VMSTATE_END_OF_LIST()
353 static void cg3_reset(DeviceState
*d
)
355 CG3State
*s
= CG3(d
);
357 /* Initialize palette */
358 memset(s
->r
, 0, 256);
359 memset(s
->g
, 0, 256);
360 memset(s
->b
, 0, 256);
364 qemu_irq_lower(s
->irq
);
367 static Property cg3_properties
[] = {
368 DEFINE_PROP_UINT32("vram-size", CG3State
, vram_size
, -1),
369 DEFINE_PROP_UINT16("width", CG3State
, width
, -1),
370 DEFINE_PROP_UINT16("height", CG3State
, height
, -1),
371 DEFINE_PROP_UINT16("depth", CG3State
, depth
, -1),
372 DEFINE_PROP_END_OF_LIST(),
375 static void cg3_class_init(ObjectClass
*klass
, void *data
)
377 DeviceClass
*dc
= DEVICE_CLASS(klass
);
379 dc
->realize
= cg3_realizefn
;
380 dc
->reset
= cg3_reset
;
381 dc
->vmsd
= &vmstate_cg3
;
382 dc
->props
= cg3_properties
;
385 static const TypeInfo cg3_info
= {
387 .parent
= TYPE_SYS_BUS_DEVICE
,
388 .instance_size
= sizeof(CG3State
),
389 .instance_init
= cg3_initfn
,
390 .class_init
= cg3_class_init
,
393 static void cg3_register_types(void)
395 type_register_static(&cg3_info
);
398 type_init(cg3_register_types
)