2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "kvm-consts.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
35 #define CPUArchState struct CPUARMState
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
40 #include "fpu/softfloat.h"
42 #define EXCP_UDEF 1 /* undefined instruction */
43 #define EXCP_SWI 2 /* software interrupt */
44 #define EXCP_PREFETCH_ABORT 3
45 #define EXCP_DATA_ABORT 4
49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
52 #define EXCP_HVC 11 /* HyperVisor Call */
53 #define EXCP_HYP_TRAP 12
54 #define EXCP_SMC 13 /* Secure Monitor Call */
58 #define ARMV7M_EXCP_RESET 1
59 #define ARMV7M_EXCP_NMI 2
60 #define ARMV7M_EXCP_HARD 3
61 #define ARMV7M_EXCP_MEM 4
62 #define ARMV7M_EXCP_BUS 5
63 #define ARMV7M_EXCP_USAGE 6
64 #define ARMV7M_EXCP_SVC 11
65 #define ARMV7M_EXCP_DEBUG 12
66 #define ARMV7M_EXCP_PENDSV 14
67 #define ARMV7M_EXCP_SYSTICK 15
69 /* ARM-specific interrupt pending bits. */
70 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
71 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
72 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
74 /* The usual mapping for an AArch64 system register to its AArch32
75 * counterpart is for the 32 bit world to have access to the lower
76 * half only (with writes leaving the upper half untouched). It's
77 * therefore useful to be able to pass TCG the offset of the least
78 * significant half of a uint64_t struct member.
80 #ifdef HOST_WORDS_BIGENDIAN
81 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
82 #define offsetofhigh32(S, M) offsetof(S, M)
84 #define offsetoflow32(S, M) offsetof(S, M)
85 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
88 /* Meanings of the ARMCPU object's four inbound GPIO lines */
91 #define ARM_CPU_VIRQ 2
92 #define ARM_CPU_VFIQ 3
94 typedef void ARMWriteCPFunc(void *opaque
, int cp_info
,
95 int srcreg
, int operand
, uint32_t value
);
96 typedef uint32_t ARMReadCPFunc(void *opaque
, int cp_info
,
97 int dstreg
, int operand
);
101 #define NB_MMU_MODES 7
103 /* We currently assume float and double are IEEE single and double
104 precision respectively.
105 Doing runtime conversions is tricky because VFP registers may contain
106 integer values (eg. as the result of a FTOSI instruction).
107 s<2n> maps to the least significant half of d<n>
108 s<2n+1> maps to the most significant half of d<n>
111 /* CPU state for each instance of a generic timer (in cp15 c14) */
112 typedef struct ARMGenericTimer
{
113 uint64_t cval
; /* Timer CompareValue register */
114 uint64_t ctl
; /* Timer Control register */
117 #define GTIMER_PHYS 0
118 #define GTIMER_VIRT 1
119 #define NUM_GTIMERS 2
127 typedef struct CPUARMState
{
128 /* Regs for current mode. */
131 /* 32/64 switch only happens when taking and returning from
132 * exceptions so the overlap semantics are taken care of then
133 * instead of having a complicated union.
135 /* Regs for A64 mode. */
138 /* PSTATE isn't an architectural register for ARMv8. However, it is
139 * convenient for us to assemble the underlying state into a 32 bit format
140 * identical to the architectural format used for the SPSR. (This is also
141 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
142 * 'pstate' register are.) Of the PSTATE bits:
143 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
144 * semantics as for AArch32, as described in the comments on each field)
145 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
146 * DAIF (exception masks) are kept in env->daif
147 * all other bits are stored in their correct places in env->pstate
150 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
152 /* Frequently accessed CPSR bits are stored separately for efficiency.
153 This contains all the other bits. Use cpsr_{read,write} to access
155 uint32_t uncached_cpsr
;
158 /* Banked registers. */
159 uint64_t banked_spsr
[8];
160 uint32_t banked_r13
[8];
161 uint32_t banked_r14
[8];
163 /* These hold r8-r12. */
164 uint32_t usr_regs
[5];
165 uint32_t fiq_regs
[5];
167 /* cpsr flag cache for faster execution */
168 uint32_t CF
; /* 0 or 1 */
169 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
170 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
171 uint32_t ZF
; /* Z set if zero. */
172 uint32_t QF
; /* 0 or 1 */
173 uint32_t GE
; /* cpsr[19:16] */
174 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
175 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
176 uint64_t daif
; /* exception masks, in the bits they are in in PSTATE */
178 uint64_t elr_el
[4]; /* AArch64 exception link regs */
179 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
181 /* System control coprocessor (cp15) */
184 union { /* Cache size selection */
186 uint64_t _unused_csselr0
;
188 uint64_t _unused_csselr1
;
191 uint64_t csselr_el
[4];
193 union { /* System control register. */
195 uint64_t _unused_sctlr
;
200 uint64_t sctlr_el
[4];
202 uint64_t c1_coproc
; /* Coprocessor access register. */
203 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
204 uint64_t sder
; /* Secure debug enable register. */
205 uint32_t nsacr
; /* Non-secure access control register. */
206 union { /* MMU translation table base 0. */
208 uint64_t _unused_ttbr0_0
;
210 uint64_t _unused_ttbr0_1
;
213 uint64_t ttbr0_el
[4];
215 union { /* MMU translation table base 1. */
217 uint64_t _unused_ttbr1_0
;
219 uint64_t _unused_ttbr1_1
;
222 uint64_t ttbr1_el
[4];
224 /* MMU translation table base control. */
226 uint32_t c2_data
; /* MPU data cachable bits. */
227 uint32_t c2_insn
; /* MPU instruction cachable bits. */
228 union { /* MMU domain access control register
229 * MPU write buffer control.
239 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
240 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
241 uint64_t hcr_el2
; /* Hypervisor configuration register */
242 uint64_t scr_el3
; /* Secure configuration register. */
243 union { /* Fault status registers. */
254 uint64_t _unused_dfsr
;
261 uint32_t c6_region
[8]; /* MPU base/size registers. */
262 union { /* Fault address registers. */
264 uint64_t _unused_far0
;
265 #ifdef HOST_WORDS_BIGENDIAN
276 uint64_t _unused_far3
;
280 union { /* Translation result. */
282 uint64_t _unused_par_0
;
284 uint64_t _unused_par_1
;
289 uint32_t c9_insn
; /* Cache lockdown registers. */
291 uint64_t c9_pmcr
; /* performance monitor control register */
292 uint64_t c9_pmcnten
; /* perf monitor counter enables */
293 uint32_t c9_pmovsr
; /* perf monitor overflow status */
294 uint32_t c9_pmxevtyper
; /* perf monitor event type */
295 uint32_t c9_pmuserenr
; /* perf monitor user enable */
296 uint32_t c9_pminten
; /* perf monitor interrupt enables */
297 union { /* Memory attribute redirection */
299 #ifdef HOST_WORDS_BIGENDIAN
300 uint64_t _unused_mair_0
;
303 uint64_t _unused_mair_1
;
307 uint64_t _unused_mair_0
;
310 uint64_t _unused_mair_1
;
317 union { /* vector base address register */
319 uint64_t _unused_vbar
;
326 uint32_t mvbar
; /* (monitor) vector base address register */
327 struct { /* FCSE PID. */
331 union { /* Context ID. */
333 uint64_t _unused_contextidr_0
;
334 uint64_t contextidr_ns
;
335 uint64_t _unused_contextidr_1
;
336 uint64_t contextidr_s
;
338 uint64_t contextidr_el
[4];
340 union { /* User RW Thread register. */
342 uint64_t tpidrurw_ns
;
343 uint64_t tpidrprw_ns
;
347 uint64_t tpidr_el
[4];
349 /* The secure banks of these registers don't map anywhere */
354 union { /* User RO Thread register. */
355 uint64_t tpidruro_ns
;
356 uint64_t tpidrro_el
[1];
358 uint64_t c14_cntfrq
; /* Counter Frequency register */
359 uint64_t c14_cntkctl
; /* Timer Control register */
360 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
361 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
362 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
363 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
364 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
365 uint32_t c15_threadid
; /* TI debugger thread-ID. */
366 uint32_t c15_config_base_address
; /* SCU base address. */
367 uint32_t c15_diagnostic
; /* diagnostic register */
368 uint32_t c15_power_diagnostic
;
369 uint32_t c15_power_control
; /* power control */
370 uint64_t dbgbvr
[16]; /* breakpoint value registers */
371 uint64_t dbgbcr
[16]; /* breakpoint control registers */
372 uint64_t dbgwvr
[16]; /* watchpoint value registers */
373 uint64_t dbgwcr
[16]; /* watchpoint control registers */
375 /* If the counter is enabled, this stores the last time the counter
376 * was reset. Otherwise it stores the counter value
379 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
389 int pending_exception
;
392 /* Information associated with an exception about to be taken:
393 * code which raises an exception must set cs->exception_index and
394 * the relevant parts of this structure; the cpu_do_interrupt function
395 * will then set the guest-visible registers as part of the exception
399 uint32_t syndrome
; /* AArch64 format syndrome register */
400 uint32_t fsr
; /* AArch32 format fault status register info */
401 uint64_t vaddress
; /* virtual addr associated with exception, if any */
402 /* If we implement EL2 we will also need to store information
403 * about the intermediate physical address for stage 2 faults.
407 /* Thumb-2 EE state. */
411 /* VFP coprocessor state. */
413 /* VFP/Neon register state. Note that the mapping between S, D and Q
414 * views of the register bank differs between AArch64 and AArch32:
416 * Qn = regs[2n+1]:regs[2n]
418 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
419 * (and regs[32] to regs[63] are inaccessible)
421 * Qn = regs[2n+1]:regs[2n]
423 * Sn = regs[2n] bits 31..0
424 * This corresponds to the architecturally defined mapping between
425 * the two execution states, and means we do not need to explicitly
426 * map these registers when changing states.
431 /* We store these fpcsr fields separately for convenience. */
435 /* scratch space when Tn are not sufficient. */
438 /* fp_status is the "normal" fp status. standard_fp_status retains
439 * values corresponding to the ARM "Standard FPSCR Value", ie
440 * default-NaN, flush-to-zero, round-to-nearest and is used by
441 * any operations (generally Neon) which the architecture defines
442 * as controlled by the standard FPSCR value rather than the FPSCR.
444 * To avoid having to transfer exception bits around, we simply
445 * say that the FPSCR cumulative exception flags are the logical
446 * OR of the flags in the two fp statuses. This relies on the
447 * only thing which needs to read the exception flags being
448 * an explicit FPSCR read.
450 float_status fp_status
;
451 float_status standard_fp_status
;
453 uint64_t exclusive_addr
;
454 uint64_t exclusive_val
;
455 uint64_t exclusive_high
;
456 #if defined(CONFIG_USER_ONLY)
457 uint64_t exclusive_test
;
458 uint32_t exclusive_info
;
461 /* iwMMXt coprocessor state. */
469 /* For mixed endian mode. */
472 #if defined(CONFIG_USER_ONLY)
473 /* For usermode syscall translation. */
477 struct CPUBreakpoint
*cpu_breakpoint
[16];
478 struct CPUWatchpoint
*cpu_watchpoint
[16];
482 /* These fields after the common ones so they are preserved on reset. */
484 /* Internal CPU feature flags. */
488 const struct arm_boot_info
*boot_info
;
493 ARMCPU
*cpu_arm_init(const char *cpu_model
);
494 int cpu_arm_exec(CPUARMState
*s
);
495 uint32_t do_arm_semihosting(CPUARMState
*env
);
497 static inline bool is_a64(CPUARMState
*env
)
502 /* you can call this signal handler from your SIGBUS and SIGSEGV
503 signal handlers to inform the virtual CPU of exceptions. non zero
504 is returned if the signal was handled by the virtual CPU. */
505 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
507 int arm_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
514 * Synchronises the counter in the PMCCNTR. This must always be called twice,
515 * once before any action that might affect the timer and again afterwards.
516 * The function is used to swap the state of the register if required.
517 * This only happens when not in user mode (!CONFIG_USER_ONLY)
519 void pmccntr_sync(CPUARMState
*env
);
521 /* SCTLR bit meanings. Several bits have been reused in newer
522 * versions of the architecture; in that case we define constants
523 * for both old and new bit meanings. Code which tests against those
524 * bits should probably check or otherwise arrange that the CPU
525 * is the architectural version it expects.
527 #define SCTLR_M (1U << 0)
528 #define SCTLR_A (1U << 1)
529 #define SCTLR_C (1U << 2)
530 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
531 #define SCTLR_SA (1U << 3)
532 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
533 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
534 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
535 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
536 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
537 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
538 #define SCTLR_ITD (1U << 7) /* v8 onward */
539 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
540 #define SCTLR_SED (1U << 8) /* v8 onward */
541 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
542 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
543 #define SCTLR_F (1U << 10) /* up to v6 */
544 #define SCTLR_SW (1U << 10) /* v7 onward */
545 #define SCTLR_Z (1U << 11)
546 #define SCTLR_I (1U << 12)
547 #define SCTLR_V (1U << 13)
548 #define SCTLR_RR (1U << 14) /* up to v7 */
549 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
550 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
551 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
552 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
553 #define SCTLR_nTWI (1U << 16) /* v8 onward */
554 #define SCTLR_HA (1U << 17)
555 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
556 #define SCTLR_nTWE (1U << 18) /* v8 onward */
557 #define SCTLR_WXN (1U << 19)
558 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
559 #define SCTLR_UWXN (1U << 20) /* v7 onward */
560 #define SCTLR_FI (1U << 21)
561 #define SCTLR_U (1U << 22)
562 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
563 #define SCTLR_VE (1U << 24) /* up to v7 */
564 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
565 #define SCTLR_EE (1U << 25)
566 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
567 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
568 #define SCTLR_NMFI (1U << 27)
569 #define SCTLR_TRE (1U << 28)
570 #define SCTLR_AFE (1U << 29)
571 #define SCTLR_TE (1U << 30)
573 #define CPSR_M (0x1fU)
574 #define CPSR_T (1U << 5)
575 #define CPSR_F (1U << 6)
576 #define CPSR_I (1U << 7)
577 #define CPSR_A (1U << 8)
578 #define CPSR_E (1U << 9)
579 #define CPSR_IT_2_7 (0xfc00U)
580 #define CPSR_GE (0xfU << 16)
581 #define CPSR_IL (1U << 20)
582 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
583 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
584 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
585 * where it is live state but not accessible to the AArch32 code.
587 #define CPSR_RESERVED (0x7U << 21)
588 #define CPSR_J (1U << 24)
589 #define CPSR_IT_0_1 (3U << 25)
590 #define CPSR_Q (1U << 27)
591 #define CPSR_V (1U << 28)
592 #define CPSR_C (1U << 29)
593 #define CPSR_Z (1U << 30)
594 #define CPSR_N (1U << 31)
595 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
596 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
598 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
599 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
601 /* Bits writable in user mode. */
602 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
603 /* Execution state bits. MRS read as zero, MSR writes ignored. */
604 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
605 /* Mask of bits which may be set by exception return copying them from SPSR */
606 #define CPSR_ERET_MASK (~CPSR_RESERVED)
608 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
609 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
610 #define TTBCR_PD0 (1U << 4)
611 #define TTBCR_PD1 (1U << 5)
612 #define TTBCR_EPD0 (1U << 7)
613 #define TTBCR_IRGN0 (3U << 8)
614 #define TTBCR_ORGN0 (3U << 10)
615 #define TTBCR_SH0 (3U << 12)
616 #define TTBCR_T1SZ (3U << 16)
617 #define TTBCR_A1 (1U << 22)
618 #define TTBCR_EPD1 (1U << 23)
619 #define TTBCR_IRGN1 (3U << 24)
620 #define TTBCR_ORGN1 (3U << 26)
621 #define TTBCR_SH1 (1U << 28)
622 #define TTBCR_EAE (1U << 31)
624 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
625 * Only these are valid when in AArch64 mode; in
626 * AArch32 mode SPSRs are basically CPSR-format.
628 #define PSTATE_SP (1U)
629 #define PSTATE_M (0xFU)
630 #define PSTATE_nRW (1U << 4)
631 #define PSTATE_F (1U << 6)
632 #define PSTATE_I (1U << 7)
633 #define PSTATE_A (1U << 8)
634 #define PSTATE_D (1U << 9)
635 #define PSTATE_IL (1U << 20)
636 #define PSTATE_SS (1U << 21)
637 #define PSTATE_V (1U << 28)
638 #define PSTATE_C (1U << 29)
639 #define PSTATE_Z (1U << 30)
640 #define PSTATE_N (1U << 31)
641 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
642 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
643 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
644 /* Mode values for AArch64 */
645 #define PSTATE_MODE_EL3h 13
646 #define PSTATE_MODE_EL3t 12
647 #define PSTATE_MODE_EL2h 9
648 #define PSTATE_MODE_EL2t 8
649 #define PSTATE_MODE_EL1h 5
650 #define PSTATE_MODE_EL1t 4
651 #define PSTATE_MODE_EL0t 0
653 /* Map EL and handler into a PSTATE_MODE. */
654 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
656 return (el
<< 2) | handler
;
659 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
660 * interprocessing, so we don't attempt to sync with the cpsr state used by
661 * the 32 bit decoder.
663 static inline uint32_t pstate_read(CPUARMState
*env
)
668 return (env
->NF
& 0x80000000) | (ZF
<< 30)
669 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
670 | env
->pstate
| env
->daif
;
673 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
675 env
->ZF
= (~val
) & PSTATE_Z
;
677 env
->CF
= (val
>> 29) & 1;
678 env
->VF
= (val
<< 3) & 0x80000000;
679 env
->daif
= val
& PSTATE_DAIF
;
680 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
683 /* Return the current CPSR value. */
684 uint32_t cpsr_read(CPUARMState
*env
);
685 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
686 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
);
688 /* Return the current xPSR value. */
689 static inline uint32_t xpsr_read(CPUARMState
*env
)
693 return (env
->NF
& 0x80000000) | (ZF
<< 30)
694 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
695 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
696 | ((env
->condexec_bits
& 0xfc) << 8)
697 | env
->v7m
.exception
;
700 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
701 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
703 if (mask
& CPSR_NZCV
) {
704 env
->ZF
= (~val
) & CPSR_Z
;
706 env
->CF
= (val
>> 29) & 1;
707 env
->VF
= (val
<< 3) & 0x80000000;
710 env
->QF
= ((val
& CPSR_Q
) != 0);
711 if (mask
& (1 << 24))
712 env
->thumb
= ((val
& (1 << 24)) != 0);
713 if (mask
& CPSR_IT_0_1
) {
714 env
->condexec_bits
&= ~3;
715 env
->condexec_bits
|= (val
>> 25) & 3;
717 if (mask
& CPSR_IT_2_7
) {
718 env
->condexec_bits
&= 3;
719 env
->condexec_bits
|= (val
>> 8) & 0xfc;
722 env
->v7m
.exception
= val
& 0x1ff;
726 #define HCR_VM (1ULL << 0)
727 #define HCR_SWIO (1ULL << 1)
728 #define HCR_PTW (1ULL << 2)
729 #define HCR_FMO (1ULL << 3)
730 #define HCR_IMO (1ULL << 4)
731 #define HCR_AMO (1ULL << 5)
732 #define HCR_VF (1ULL << 6)
733 #define HCR_VI (1ULL << 7)
734 #define HCR_VSE (1ULL << 8)
735 #define HCR_FB (1ULL << 9)
736 #define HCR_BSU_MASK (3ULL << 10)
737 #define HCR_DC (1ULL << 12)
738 #define HCR_TWI (1ULL << 13)
739 #define HCR_TWE (1ULL << 14)
740 #define HCR_TID0 (1ULL << 15)
741 #define HCR_TID1 (1ULL << 16)
742 #define HCR_TID2 (1ULL << 17)
743 #define HCR_TID3 (1ULL << 18)
744 #define HCR_TSC (1ULL << 19)
745 #define HCR_TIDCP (1ULL << 20)
746 #define HCR_TACR (1ULL << 21)
747 #define HCR_TSW (1ULL << 22)
748 #define HCR_TPC (1ULL << 23)
749 #define HCR_TPU (1ULL << 24)
750 #define HCR_TTLB (1ULL << 25)
751 #define HCR_TVM (1ULL << 26)
752 #define HCR_TGE (1ULL << 27)
753 #define HCR_TDZ (1ULL << 28)
754 #define HCR_HCD (1ULL << 29)
755 #define HCR_TRVM (1ULL << 30)
756 #define HCR_RW (1ULL << 31)
757 #define HCR_CD (1ULL << 32)
758 #define HCR_ID (1ULL << 33)
759 #define HCR_MASK ((1ULL << 34) - 1)
761 #define SCR_NS (1U << 0)
762 #define SCR_IRQ (1U << 1)
763 #define SCR_FIQ (1U << 2)
764 #define SCR_EA (1U << 3)
765 #define SCR_FW (1U << 4)
766 #define SCR_AW (1U << 5)
767 #define SCR_NET (1U << 6)
768 #define SCR_SMD (1U << 7)
769 #define SCR_HCE (1U << 8)
770 #define SCR_SIF (1U << 9)
771 #define SCR_RW (1U << 10)
772 #define SCR_ST (1U << 11)
773 #define SCR_TWI (1U << 12)
774 #define SCR_TWE (1U << 13)
775 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
776 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
778 /* Return the current FPSCR value. */
779 uint32_t vfp_get_fpscr(CPUARMState
*env
);
780 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
782 /* For A64 the FPSCR is split into two logically distinct registers,
783 * FPCR and FPSR. However since they still use non-overlapping bits
784 * we store the underlying state in fpscr and just mask on read/write.
786 #define FPSR_MASK 0xf800009f
787 #define FPCR_MASK 0x07f79f00
788 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
790 return vfp_get_fpscr(env
) & FPSR_MASK
;
793 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
795 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
796 vfp_set_fpscr(env
, new_fpscr
);
799 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
801 return vfp_get_fpscr(env
) & FPCR_MASK
;
804 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
806 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
807 vfp_set_fpscr(env
, new_fpscr
);
811 ARM_CPU_MODE_USR
= 0x10,
812 ARM_CPU_MODE_FIQ
= 0x11,
813 ARM_CPU_MODE_IRQ
= 0x12,
814 ARM_CPU_MODE_SVC
= 0x13,
815 ARM_CPU_MODE_MON
= 0x16,
816 ARM_CPU_MODE_ABT
= 0x17,
817 ARM_CPU_MODE_HYP
= 0x1a,
818 ARM_CPU_MODE_UND
= 0x1b,
819 ARM_CPU_MODE_SYS
= 0x1f
822 /* VFP system registers. */
823 #define ARM_VFP_FPSID 0
824 #define ARM_VFP_FPSCR 1
825 #define ARM_VFP_MVFR2 5
826 #define ARM_VFP_MVFR1 6
827 #define ARM_VFP_MVFR0 7
828 #define ARM_VFP_FPEXC 8
829 #define ARM_VFP_FPINST 9
830 #define ARM_VFP_FPINST2 10
832 /* iwMMXt coprocessor control registers. */
833 #define ARM_IWMMXT_wCID 0
834 #define ARM_IWMMXT_wCon 1
835 #define ARM_IWMMXT_wCSSF 2
836 #define ARM_IWMMXT_wCASF 3
837 #define ARM_IWMMXT_wCGR0 8
838 #define ARM_IWMMXT_wCGR1 9
839 #define ARM_IWMMXT_wCGR2 10
840 #define ARM_IWMMXT_wCGR3 11
842 /* If adding a feature bit which corresponds to a Linux ELF
843 * HWCAP bit, remember to update the feature-bit-to-hwcap
844 * mapping in linux-user/elfload.c:get_elf_hwcap().
848 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
849 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
850 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
855 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
857 ARM_FEATURE_VFP_FP16
,
859 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
860 ARM_FEATURE_M
, /* Microcontroller profile. */
861 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
862 ARM_FEATURE_THUMB2EE
,
863 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
866 ARM_FEATURE_STRONGARM
,
867 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
868 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
869 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
870 ARM_FEATURE_GENERIC_TIMER
,
871 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
872 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
873 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
874 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
875 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
876 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
877 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
878 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
880 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
881 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
882 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
883 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
884 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
885 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
886 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
887 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
888 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
889 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
892 static inline int arm_feature(CPUARMState
*env
, int feature
)
894 return (env
->features
& (1ULL << feature
)) != 0;
897 #if !defined(CONFIG_USER_ONLY)
898 /* Return true if exception levels below EL3 are in secure state,
899 * or would be following an exception return to that level.
900 * Unlike arm_is_secure() (which is always a question about the
901 * _current_ state of the CPU) this doesn't care about the current
904 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
906 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
907 return !(env
->cp15
.scr_el3
& SCR_NS
);
909 /* If EL2 is not supported then the secure state is implementation
910 * defined, in which case QEMU defaults to non-secure.
916 /* Return true if the processor is in secure state */
917 static inline bool arm_is_secure(CPUARMState
*env
)
919 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
920 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
921 /* CPU currently in AArch64 state and EL3 */
923 } else if (!is_a64(env
) &&
924 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
925 /* CPU currently in AArch32 state and monitor mode */
929 return arm_is_secure_below_el3(env
);
933 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
938 static inline bool arm_is_secure(CPUARMState
*env
)
944 /* Return true if the specified exception level is running in AArch64 state. */
945 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
947 /* We don't currently support EL2, and this isn't valid for EL0
948 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
949 * then the state of EL0 isn't well defined.)
951 assert(el
== 1 || el
== 3);
953 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
954 * is a QEMU-imposed simplification which we may wish to change later.
955 * If we in future support EL2 and/or EL3, then the state of lower
956 * exception levels is controlled by the HCR.RW and SCR.RW bits.
958 return arm_feature(env
, ARM_FEATURE_AARCH64
);
961 /* Function for determing whether guest cp register reads and writes should
962 * access the secure or non-secure bank of a cp register. When EL3 is
963 * operating in AArch32 state, the NS-bit determines whether the secure
964 * instance of a cp register should be used. When EL3 is AArch64 (or if
965 * it doesn't exist at all) then there is no register banking, and all
966 * accesses are to the non-secure version.
968 static inline bool access_secure_reg(CPUARMState
*env
)
970 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
971 !arm_el_is_aa64(env
, 3) &&
972 !(env
->cp15
.scr_el3
& SCR_NS
));
977 /* Macros for accessing a specified CP register bank */
978 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
979 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
981 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
984 (_env)->cp15._regname##_s = (_val); \
986 (_env)->cp15._regname##_ns = (_val); \
990 /* Macros for automatically accessing a specific CP register bank depending on
991 * the current secure state of the system. These macros are not intended for
992 * supporting instruction translation reads/writes as these are dependent
993 * solely on the SCR.NS bit and not the mode.
995 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
996 A32_BANKED_REG_GET((_env), _regname, \
997 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
999 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1000 A32_BANKED_REG_SET((_env), _regname, \
1001 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
1004 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1005 unsigned int arm_excp_target_el(CPUState
*cs
, unsigned int excp_idx
);
1007 /* Interface between CPU and Interrupt controller. */
1008 void armv7m_nvic_set_pending(void *opaque
, int irq
);
1009 int armv7m_nvic_acknowledge_irq(void *opaque
);
1010 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
1012 /* Interface for defining coprocessor registers.
1013 * Registers are defined in tables of arm_cp_reginfo structs
1014 * which are passed to define_arm_cp_regs().
1017 /* When looking up a coprocessor register we look for it
1018 * via an integer which encodes all of:
1019 * coprocessor number
1020 * Crn, Crm, opc1, opc2 fields
1021 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1022 * or via MRRC/MCRR?)
1023 * non-secure/secure bank (AArch32 only)
1024 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1025 * (In this case crn and opc2 should be zero.)
1026 * For AArch64, there is no 32/64 bit size distinction;
1027 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1028 * and 4 bit CRn and CRm. The encoding patterns are chosen
1029 * to be easy to convert to and from the KVM encodings, and also
1030 * so that the hashtable can contain both AArch32 and AArch64
1031 * registers (to allow for interprocessing where we might run
1032 * 32 bit code on a 64 bit core).
1034 /* This bit is private to our hashtable cpreg; in KVM register
1035 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1036 * in the upper bits of the 64 bit ID.
1038 #define CP_REG_AA64_SHIFT 28
1039 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1041 /* To enable banking of coprocessor registers depending on ns-bit we
1042 * add a bit to distinguish between secure and non-secure cpregs in the
1045 #define CP_REG_NS_SHIFT 29
1046 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1048 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1049 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1050 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1052 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1053 (CP_REG_AA64_MASK | \
1054 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1055 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1056 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1057 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1058 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1059 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1061 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1062 * version used as a key for the coprocessor register hashtable
1064 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1066 uint32_t cpregid
= kvmid
;
1067 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1068 cpregid
|= CP_REG_AA64_MASK
;
1070 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1071 cpregid
|= (1 << 15);
1074 /* KVM is always non-secure so add the NS flag on AArch32 register
1077 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1082 /* Convert a truncated 32 bit hashtable key into the full
1083 * 64 bit KVM register ID.
1085 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1089 if (cpregid
& CP_REG_AA64_MASK
) {
1090 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1091 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1093 kvmid
= cpregid
& ~(1 << 15);
1094 if (cpregid
& (1 << 15)) {
1095 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1097 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1103 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1104 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1105 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1106 * TCG can assume the value to be constant (ie load at translate time)
1107 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1108 * indicates that the TB should not be ended after a write to this register
1109 * (the default is that the TB ends after cp writes). OVERRIDE permits
1110 * a register definition to override a previous definition for the
1111 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1112 * old must have the OVERRIDE bit set.
1113 * ALIAS indicates that this register is an alias view of some underlying
1114 * state which is also visible via another register, and that the other
1115 * register is handling migration; registers marked ALIAS will not be migrated
1116 * but may have their state set by syncing of register state from KVM.
1117 * NO_RAW indicates that this register has no underlying state and does not
1118 * support raw access for state saving/loading; it will not be used for either
1119 * migration or KVM state synchronization. (Typically this is for "registers"
1120 * which are actually used as instructions for cache maintenance and so on.)
1121 * IO indicates that this register does I/O and therefore its accesses
1122 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1123 * registers which implement clocks or timers require this.
1125 #define ARM_CP_SPECIAL 1
1126 #define ARM_CP_CONST 2
1127 #define ARM_CP_64BIT 4
1128 #define ARM_CP_SUPPRESS_TB_END 8
1129 #define ARM_CP_OVERRIDE 16
1130 #define ARM_CP_ALIAS 32
1131 #define ARM_CP_IO 64
1132 #define ARM_CP_NO_RAW 128
1133 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1134 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1135 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1136 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1137 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1138 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1139 /* Used only as a terminator for ARMCPRegInfo lists */
1140 #define ARM_CP_SENTINEL 0xffff
1141 /* Mask of only the flag bits in a type field */
1142 #define ARM_CP_FLAG_MASK 0xff
1144 /* Valid values for ARMCPRegInfo state field, indicating which of
1145 * the AArch32 and AArch64 execution states this register is visible in.
1146 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1147 * If the reginfo is declared to be visible in both states then a second
1148 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1149 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1150 * Note that we rely on the values of these enums as we iterate through
1151 * the various states in some places.
1154 ARM_CP_STATE_AA32
= 0,
1155 ARM_CP_STATE_AA64
= 1,
1156 ARM_CP_STATE_BOTH
= 2,
1159 /* ARM CP register secure state flags. These flags identify security state
1160 * attributes for a given CP register entry.
1161 * The existence of both or neither secure and non-secure flags indicates that
1162 * the register has both a secure and non-secure hash entry. A single one of
1163 * these flags causes the register to only be hashed for the specified
1165 * Although definitions may have any combination of the S/NS bits, each
1166 * registered entry will only have one to identify whether the entry is secure
1170 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1171 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1174 /* Return true if cptype is a valid type field. This is used to try to
1175 * catch errors where the sentinel has been accidentally left off the end
1176 * of a list of registers.
1178 static inline bool cptype_valid(int cptype
)
1180 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1181 || ((cptype
& ARM_CP_SPECIAL
) &&
1182 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1186 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1187 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1188 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1189 * (ie any of the privileged modes in Secure state, or Monitor mode).
1190 * If a register is accessible in one privilege level it's always accessible
1191 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1192 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1193 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1194 * terminology a little and call this PL3.
1195 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1196 * with the ELx exception levels.
1198 * If access permissions for a register are more complex than can be
1199 * described with these bits, then use a laxer set of restrictions, and
1200 * do the more restrictive/complex check inside a helper function.
1204 #define PL2_R (0x20 | PL3_R)
1205 #define PL2_W (0x10 | PL3_W)
1206 #define PL1_R (0x08 | PL2_R)
1207 #define PL1_W (0x04 | PL2_W)
1208 #define PL0_R (0x02 | PL1_R)
1209 #define PL0_W (0x01 | PL1_W)
1211 #define PL3_RW (PL3_R | PL3_W)
1212 #define PL2_RW (PL2_R | PL2_W)
1213 #define PL1_RW (PL1_R | PL1_W)
1214 #define PL0_RW (PL0_R | PL0_W)
1216 /* Return the current Exception Level (as per ARMv8; note that this differs
1217 * from the ARMv7 Privilege Level).
1219 static inline int arm_current_el(CPUARMState
*env
)
1221 if (arm_feature(env
, ARM_FEATURE_M
)) {
1222 return !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1226 return extract32(env
->pstate
, 2, 2);
1229 switch (env
->uncached_cpsr
& 0x1f) {
1230 case ARM_CPU_MODE_USR
:
1232 case ARM_CPU_MODE_HYP
:
1234 case ARM_CPU_MODE_MON
:
1237 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1238 /* If EL3 is 32-bit then all secure privileged modes run in
1248 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1250 typedef enum CPAccessResult
{
1251 /* Access is permitted */
1253 /* Access fails due to a configurable trap or enable which would
1254 * result in a categorized exception syndrome giving information about
1255 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1259 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1260 * Note that this is not a catch-all case -- the set of cases which may
1261 * result in this failure is specifically defined by the architecture.
1263 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1266 /* Access functions for coprocessor registers. These cannot fail and
1267 * may not raise exceptions.
1269 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1270 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1272 /* Access permission check functions for coprocessor registers. */
1273 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1274 /* Hook function for register reset */
1275 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1279 /* Definition of an ARM coprocessor register */
1280 struct ARMCPRegInfo
{
1281 /* Name of register (useful mainly for debugging, need not be unique) */
1283 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1284 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1285 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1286 * will be decoded to this register. The register read and write
1287 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1288 * used by the program, so it is possible to register a wildcard and
1289 * then behave differently on read/write if necessary.
1290 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1291 * must both be zero.
1292 * For AArch64-visible registers, opc0 is also used.
1293 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1294 * way to distinguish (for KVM's benefit) guest-visible system registers
1295 * from demuxed ones provided to preserve the "no side effects on
1296 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1297 * visible (to match KVM's encoding); cp==0 will be converted to
1298 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1306 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1308 /* Register type: ARM_CP_* bits/values */
1310 /* Access rights: PL*_[RW] */
1312 /* Security state: ARM_CP_SECSTATE_* bits/values */
1314 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1315 * this register was defined: can be used to hand data through to the
1316 * register read/write functions, since they are passed the ARMCPRegInfo*.
1319 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1320 * fieldoffset is non-zero, the reset value of the register.
1322 uint64_t resetvalue
;
1323 /* Offset of the field in CPUARMState for this register.
1325 * This is not needed if either:
1326 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1327 * 2. both readfn and writefn are specified
1329 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1331 /* Offsets of the secure and non-secure fields in CPUARMState for the
1332 * register if it is banked. These fields are only used during the static
1333 * registration of a register. During hashing the bank associated
1334 * with a given security state is copied to fieldoffset which is used from
1337 * It is expected that register definitions use either fieldoffset or
1338 * bank_fieldoffsets in the definition but not both. It is also expected
1339 * that both bank offsets are set when defining a banked register. This
1340 * use indicates that a register is banked.
1342 ptrdiff_t bank_fieldoffsets
[2];
1344 /* Function for making any access checks for this register in addition to
1345 * those specified by the 'access' permissions bits. If NULL, no extra
1346 * checks required. The access check is performed at runtime, not at
1349 CPAccessFn
*accessfn
;
1350 /* Function for handling reads of this register. If NULL, then reads
1351 * will be done by loading from the offset into CPUARMState specified
1355 /* Function for handling writes of this register. If NULL, then writes
1356 * will be done by writing to the offset into CPUARMState specified
1360 /* Function for doing a "raw" read; used when we need to copy
1361 * coprocessor state to the kernel for KVM or out for
1362 * migration. This only needs to be provided if there is also a
1363 * readfn and it has side effects (for instance clear-on-read bits).
1365 CPReadFn
*raw_readfn
;
1366 /* Function for doing a "raw" write; used when we need to copy KVM
1367 * kernel coprocessor state into userspace, or for inbound
1368 * migration. This only needs to be provided if there is also a
1369 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1370 * or similar behaviour.
1372 CPWriteFn
*raw_writefn
;
1373 /* Function for resetting the register. If NULL, then reset will be done
1374 * by writing resetvalue to the field specified in fieldoffset. If
1375 * fieldoffset is 0 then no reset will be done.
1380 /* Macros which are lvalues for the field in CPUARMState for the
1383 #define CPREG_FIELD32(env, ri) \
1384 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1385 #define CPREG_FIELD64(env, ri) \
1386 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1388 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1390 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1391 const ARMCPRegInfo
*regs
, void *opaque
);
1392 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1393 const ARMCPRegInfo
*regs
, void *opaque
);
1394 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1396 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
1398 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1400 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
1402 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1404 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1405 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1407 /* CPReadFn that can be used for read-as-zero behaviour */
1408 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1410 /* CPResetFn that does nothing, for use if no reset is required even
1411 * if fieldoffset is non zero.
1413 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1415 /* Return true if this reginfo struct's field in the cpu state struct
1418 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1420 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1423 static inline bool cp_access_ok(int current_el
,
1424 const ARMCPRegInfo
*ri
, int isread
)
1426 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
1430 * write_list_to_cpustate
1433 * For each register listed in the ARMCPU cpreg_indexes list, write
1434 * its value from the cpreg_values list into the ARMCPUState structure.
1435 * This updates TCG's working data structures from KVM data or
1436 * from incoming migration state.
1438 * Returns: true if all register values were updated correctly,
1439 * false if some register was unknown or could not be written.
1440 * Note that we do not stop early on failure -- we will attempt
1441 * writing all registers in the list.
1443 bool write_list_to_cpustate(ARMCPU
*cpu
);
1446 * write_cpustate_to_list:
1449 * For each register listed in the ARMCPU cpreg_indexes list, write
1450 * its value from the ARMCPUState structure into the cpreg_values list.
1451 * This is used to copy info from TCG's working data structures into
1452 * KVM or for outbound migration.
1454 * Returns: true if all register values were read correctly,
1455 * false if some register was unknown or could not be read.
1456 * Note that we do not stop early on failure -- we will attempt
1457 * reading all registers in the list.
1459 bool write_cpustate_to_list(ARMCPU
*cpu
);
1461 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
1462 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1463 conventional cores (ie. Application or Realtime profile). */
1465 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1467 #define ARM_CPUID_TI915T 0x54029152
1468 #define ARM_CPUID_TI925T 0x54029252
1470 #if defined(CONFIG_USER_ONLY)
1471 #define TARGET_PAGE_BITS 12
1473 /* The ARM MMU allows 1k pages. */
1474 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1475 architecture revisions. Maybe a configure option to disable them. */
1476 #define TARGET_PAGE_BITS 10
1479 #if defined(TARGET_AARCH64)
1480 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1481 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1483 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1484 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1487 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
)
1489 CPUARMState
*env
= cs
->env_ptr
;
1490 unsigned int cur_el
= arm_current_el(env
);
1491 unsigned int target_el
= arm_excp_target_el(cs
, excp_idx
);
1492 bool secure
= arm_is_secure(env
);
1495 bool pstate_unmasked
;
1496 int8_t unmasked
= 0;
1498 /* Don't take exceptions if they target a lower EL.
1499 * This check should catch any exceptions that would not be taken but left
1502 if (cur_el
> target_el
) {
1508 /* If FIQs are routed to EL3 or EL2 then there are cases where we
1509 * override the CPSR.F in determining if the exception is masked or
1510 * not. If neither of these are set then we fall back to the CPSR.F
1511 * setting otherwise we further assess the state below.
1513 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
1514 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
1516 /* When EL3 is 32-bit, the SCR.FW bit controls whether the CPSR.F bit
1517 * masks FIQ interrupts when taken in non-secure state. If SCR.FW is
1518 * set then FIQs can be masked by CPSR.F when non-secure but only
1519 * when FIQs are only routed to EL3.
1521 scr
&= !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
1522 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
1526 /* When EL3 execution state is 32-bit, if HCR.IMO is set then we may
1527 * override the CPSR.I masking when in non-secure state. The SCR.IRQ
1528 * setting has already been taken into consideration when setting the
1529 * target EL, so it does not have a further affect here.
1531 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
1533 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
1537 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
1538 /* VFIQs are only taken when hypervized and non-secure. */
1541 return !(env
->daif
& PSTATE_F
);
1543 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
1544 /* VIRQs are only taken when hypervized and non-secure. */
1547 return !(env
->daif
& PSTATE_I
);
1549 g_assert_not_reached();
1552 /* Use the target EL, current execution state and SCR/HCR settings to
1553 * determine whether the corresponding CPSR bit is used to mask the
1556 if ((target_el
> cur_el
) && (target_el
!= 1)) {
1557 if (arm_el_is_aa64(env
, 3) || ((scr
|| hcr
) && (!secure
))) {
1562 /* The PSTATE bits only mask the interrupt if we have not overriden the
1565 return unmasked
|| pstate_unmasked
;
1568 static inline CPUARMState
*cpu_init(const char *cpu_model
)
1570 ARMCPU
*cpu
= cpu_arm_init(cpu_model
);
1577 #define cpu_exec cpu_arm_exec
1578 #define cpu_gen_code cpu_arm_gen_code
1579 #define cpu_signal_handler cpu_arm_signal_handler
1580 #define cpu_list arm_cpu_list
1582 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1585 * + NonSecure EL1 & 0 stage 1
1586 * + NonSecure EL1 & 0 stage 2
1588 * + Secure EL1 & EL0
1591 * + NonSecure PL1 & 0 stage 1
1592 * + NonSecure PL1 & 0 stage 2
1594 * + Secure PL0 & PL1
1595 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1597 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1598 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1599 * may differ in access permissions even if the VA->PA map is the same
1600 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1601 * translation, which means that we have one mmu_idx that deals with two
1602 * concatenated translation regimes [this sort of combined s1+2 TLB is
1603 * architecturally permitted]
1604 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1605 * handling via the TLB. The only way to do a stage 1 translation without
1606 * the immediate stage 2 translation is via the ATS or AT system insns,
1607 * which can be slow-pathed and always do a page table walk.
1608 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1609 * translation regimes, because they map reasonably well to each other
1610 * and they can't both be active at the same time.
1611 * This gives us the following list of mmu_idx values:
1613 * NS EL0 (aka NS PL0) stage 1+2
1614 * NS EL1 (aka NS PL1) stage 1+2
1615 * NS EL2 (aka NS PL2)
1618 * S EL1 (not used if EL3 is 32 bit)
1621 * (The last of these is an mmu_idx because we want to be able to use the TLB
1622 * for the accesses done as part of a stage 1 page table walk, rather than
1623 * having to walk the stage 2 page table over and over.)
1625 * Our enumeration includes at the end some entries which are not "true"
1626 * mmu_idx values in that they don't have corresponding TLBs and are only
1627 * valid for doing slow path page table walks.
1629 * The constant names here are patterned after the general style of the names
1630 * of the AT/ATS operations.
1631 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1633 typedef enum ARMMMUIdx
{
1634 ARMMMUIdx_S12NSE0
= 0,
1635 ARMMMUIdx_S12NSE1
= 1,
1638 ARMMMUIdx_S1SE0
= 4,
1639 ARMMMUIdx_S1SE1
= 5,
1641 /* Indexes below here don't have TLBs and are used only for AT system
1642 * instructions or for the first stage of an S12 page table walk.
1644 ARMMMUIdx_S1NSE0
= 7,
1645 ARMMMUIdx_S1NSE1
= 8,
1648 #define MMU_MODE0_SUFFIX _user
1649 #define MMU_MODE1_SUFFIX _kernel
1650 #define MMU_USER_IDX 0
1652 /* Return the exception level we're running at if this is our mmu_idx */
1653 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
1655 assert(mmu_idx
< ARMMMUIdx_S2NS
);
1659 /* Determine the current mmu_idx to use for normal loads/stores */
1660 static inline int cpu_mmu_index(CPUARMState
*env
)
1662 int el
= arm_current_el(env
);
1664 if (el
< 2 && arm_is_secure_below_el3(env
)) {
1665 return ARMMMUIdx_S1SE0
+ el
;
1670 /* Return the Exception Level targeted by debug exceptions;
1671 * currently always EL1 since we don't implement EL2 or EL3.
1673 static inline int arm_debug_target_el(CPUARMState
*env
)
1678 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
1680 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
1681 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
1682 || (env
->daif
& PSTATE_D
)) {
1689 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
1691 if (arm_current_el(env
) == 0 && arm_el_is_aa64(env
, 1)) {
1692 return aa64_generate_debug_exceptions(env
);
1694 return arm_current_el(env
) != 2;
1697 /* Return true if debugging exceptions are currently enabled.
1698 * This corresponds to what in ARM ARM pseudocode would be
1699 * if UsingAArch32() then
1700 * return AArch32.GenerateDebugExceptions()
1702 * return AArch64.GenerateDebugExceptions()
1703 * We choose to push the if() down into this function for clarity,
1704 * since the pseudocode has it at all callsites except for the one in
1705 * CheckSoftwareStep(), where it is elided because both branches would
1706 * always return the same value.
1708 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1709 * don't yet implement those exception levels or their associated trap bits.
1711 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
1714 return aa64_generate_debug_exceptions(env
);
1716 return aa32_generate_debug_exceptions(env
);
1720 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1721 * implicitly means this always returns false in pre-v8 CPUs.)
1723 static inline bool arm_singlestep_active(CPUARMState
*env
)
1725 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
1726 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
1727 && arm_generate_debug_exceptions(env
);
1730 #include "exec/cpu-all.h"
1732 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1733 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1734 * We put flags which are shared between 32 and 64 bit mode at the top
1735 * of the word, and flags which apply to only one mode at the bottom.
1737 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1738 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1739 #define ARM_TBFLAG_MMUIDX_SHIFT 28
1740 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1742 /* Bit usage when in AArch32 state: */
1743 #define ARM_TBFLAG_THUMB_SHIFT 0
1744 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1745 #define ARM_TBFLAG_VECLEN_SHIFT 1
1746 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1747 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1748 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1749 #define ARM_TBFLAG_VFPEN_SHIFT 7
1750 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1751 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1752 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1753 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1754 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1755 #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
1756 #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
1757 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
1758 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1759 #define ARM_TBFLAG_PSTATE_SS_SHIFT 19
1760 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1761 /* We store the bottom two bits of the CPAR as TB flags and handle
1762 * checks on the other bits at runtime
1764 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
1765 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1766 /* Indicates whether cp register reads and writes by guest code should access
1767 * the secure or nonsecure bank of banked registers; note that this is not
1768 * the same thing as the current security state of the processor!
1770 #define ARM_TBFLAG_NS_SHIFT 22
1771 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1773 /* Bit usage when in AArch64 state */
1774 #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
1775 #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
1776 #define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
1777 #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1778 #define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
1779 #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1781 /* some convenience accessor macros */
1782 #define ARM_TBFLAG_AARCH64_STATE(F) \
1783 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1784 #define ARM_TBFLAG_MMUIDX(F) \
1785 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
1786 #define ARM_TBFLAG_THUMB(F) \
1787 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1788 #define ARM_TBFLAG_VECLEN(F) \
1789 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1790 #define ARM_TBFLAG_VECSTRIDE(F) \
1791 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1792 #define ARM_TBFLAG_VFPEN(F) \
1793 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1794 #define ARM_TBFLAG_CONDEXEC(F) \
1795 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1796 #define ARM_TBFLAG_BSWAP_CODE(F) \
1797 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1798 #define ARM_TBFLAG_CPACR_FPEN(F) \
1799 (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
1800 #define ARM_TBFLAG_SS_ACTIVE(F) \
1801 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1802 #define ARM_TBFLAG_PSTATE_SS(F) \
1803 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1804 #define ARM_TBFLAG_XSCALE_CPAR(F) \
1805 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1806 #define ARM_TBFLAG_AA64_FPEN(F) \
1807 (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
1808 #define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
1809 (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1810 #define ARM_TBFLAG_AA64_PSTATE_SS(F) \
1811 (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1812 #define ARM_TBFLAG_NS(F) \
1813 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
1815 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
1816 target_ulong
*cs_base
, int *flags
)
1820 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1821 fpen
= extract32(env
->cp15
.c1_coproc
, 20, 2);
1823 /* CPACR doesn't exist before v6, so VFP is always accessible */
1829 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
1830 if (fpen
== 3 || (fpen
== 1 && arm_current_el(env
) != 0)) {
1831 *flags
|= ARM_TBFLAG_AA64_FPEN_MASK
;
1833 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1834 * states defined in the ARM ARM for software singlestep:
1835 * SS_ACTIVE PSTATE.SS State
1836 * 0 x Inactive (the TB flag for SS is always 0)
1837 * 1 0 Active-pending
1838 * 1 1 Active-not-pending
1840 if (arm_singlestep_active(env
)) {
1841 *flags
|= ARM_TBFLAG_AA64_SS_ACTIVE_MASK
;
1842 if (env
->pstate
& PSTATE_SS
) {
1843 *flags
|= ARM_TBFLAG_AA64_PSTATE_SS_MASK
;
1847 *pc
= env
->regs
[15];
1848 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
1849 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
1850 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
1851 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
1852 | (env
->bswap_code
<< ARM_TBFLAG_BSWAP_CODE_SHIFT
);
1853 if (!(access_secure_reg(env
))) {
1854 *flags
|= ARM_TBFLAG_NS_MASK
;
1856 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
1857 || arm_el_is_aa64(env
, 1)) {
1858 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
1860 if (fpen
== 3 || (fpen
== 1 && arm_current_el(env
) != 0)) {
1861 *flags
|= ARM_TBFLAG_CPACR_FPEN_MASK
;
1863 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1864 * states defined in the ARM ARM for software singlestep:
1865 * SS_ACTIVE PSTATE.SS State
1866 * 0 x Inactive (the TB flag for SS is always 0)
1867 * 1 0 Active-pending
1868 * 1 1 Active-not-pending
1870 if (arm_singlestep_active(env
)) {
1871 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
1872 if (env
->uncached_cpsr
& PSTATE_SS
) {
1873 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
1876 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
1877 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
1880 *flags
|= (cpu_mmu_index(env
) << ARM_TBFLAG_MMUIDX_SHIFT
);
1885 #include "exec/exec-all.h"
1887 static inline void cpu_pc_from_tb(CPUARMState
*env
, TranslationBlock
*tb
)
1889 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
1892 env
->regs
[15] = tb
->pc
;
1897 QEMU_PSCI_CONDUIT_DISABLED
= 0,
1898 QEMU_PSCI_CONDUIT_SMC
= 1,
1899 QEMU_PSCI_CONDUIT_HVC
= 2,