target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5 #include "internals.h"
   6
   7
   8 /* internal defines */
   9 typedef struct DisasContext {
  10     DisasContextBase base;
  11     const ARMISARegisters *isar;
  12
  13     target_ulong pc;
  14     target_ulong page_start;
  15     uint32_t insn;
  16     /* Nonzero if this instruction has been conditionally skipped.  */
  17     int condjmp;
  18     /* The label that will be jumped to when the instruction is skipped.  */
  19     TCGLabel *condlabel;
  20     /* Thumb-2 conditional execution bits.  */
  21     int condexec_mask;
  22     int condexec_cond;
  23     int thumb;
  24     int sctlr_b;
  25     TCGMemOp be_data;
  26 #if !defined(CONFIG_USER_ONLY)
  27     int user;
  28 #endif
  29     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  30     uint8_t tbii;      /* TBI1|TBI0 for insns */
  31     uint8_t tbid;      /* TBI1|TBI0 for data */
  32     bool ns;        /* Use non-secure CPREG bank on access */
  33     int fp_excp_el; /* FP exception EL or 0 if enabled */
  34     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  35     int sve_len;     /* SVE vector length in bytes */
  36     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  37     bool secure_routed_to_el3;
  38     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  39     int vec_len;
  40     int vec_stride;
  41     bool v7m_handler_mode;
  42     bool v8m_secure; /* true if v8M and we're in Secure mode */
  43     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  44     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  45     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
  46     bool v7m_lspact; /* FPCCR.LSPACT set */
  47     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  48      * so that top level loop can generate correct syndrome information.
  49      */
  50     uint32_t svc_imm;
  51     int aarch64;
  52     int current_el;
  53     GHashTable *cp_regs;
  54     uint64_t features; /* CPU features bits */
  55     /* Because unallocated encodings generate different exception syndrome
  56      * information from traps due to FP being disabled, we can't do a single
  57      * "is fp access disabled" check at a high level in the decode tree.
  58      * To help in catching bugs where the access check was forgotten in some
  59      * code path, we set this flag when the access check is done, and assert
  60      * that it is set at the point where we actually touch the FP regs.
  61      */
  62     bool fp_access_checked;
  63     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  64      * single-step support).
  65      */
  66     bool ss_active;
  67     bool pstate_ss;
  68     /* True if the insn just emitted was a load-exclusive instruction
  69      * (necessary for syndrome information for single step exceptions),
  70      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  71      */
  72     bool is_ldex;
  73     /* True if a single-step exception will be taken to the current EL */
  74     bool ss_same_el;
  75     /* True if v8.3-PAuth is active.  */
  76     bool pauth_active;
  77     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  78     bool bt;
  79     /*
  80      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
  81      *  < 0, set by the current instruction.
  82      */
  83     int8_t btype;
  84     /* True if this page is guarded.  */
  85     bool guarded_page;
  86     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  87     int c15_cpar;
  88     /* TCG op of the current insn_start.  */
  89     TCGOp *insn_start;
  90 #define TMP_A64_MAX 16
  91     int tmp_a64_count;
  92     TCGv_i64 tmp_a64[TMP_A64_MAX];
  93 } DisasContext;
  94
  95 typedef struct DisasCompare {
  96     TCGCond cond;
  97     TCGv_i32 value;
  98     bool value_global;
  99 } DisasCompare;
 100
 101 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
 102 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 103 extern TCGv_i64 cpu_exclusive_addr;
 104 extern TCGv_i64 cpu_exclusive_val;
 105
 106 static inline int arm_dc_feature(DisasContext *dc, int feature)
 107 {
 108     return (dc->features & (1ULL << feature)) != 0;
 109 }
 110
 111 static inline int get_mem_index(DisasContext *s)
 112 {
 113     return arm_to_core_mmu_idx(s->mmu_idx);
 114 }
 115
 116 /* Function used to determine the target exception EL when otherwise not known
 117  * or default.
 118  */
 119 static inline int default_exception_el(DisasContext *s)
 120 {
 121     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 122      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 123      * exceptions can only be routed to ELs above 1, so we target the higher of
 124      * 1 or the current EL.
 125      */
 126     return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 127             ? 3 : MAX(1, s->current_el);
 128 }
 129
 130 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 131 {
 132     /* We don't need to save all of the syndrome so we mask and shift
 133      * out unneeded bits to help the sleb128 encoder do a better job.
 134      */
 135     syn &= ARM_INSN_START_WORD2_MASK;
 136     syn >>= ARM_INSN_START_WORD2_SHIFT;
 137
 138     /* We check and clear insn_start_idx to catch multiple updates.  */
 139     assert(s->insn_start != NULL);
 140     tcg_set_insn_start_param(s->insn_start, 2, syn);
 141     s->insn_start = NULL;
 142 }
 143
 144 /* is_jmp field values */
 145 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 146 #define DISAS_UPDATE    DISAS_TARGET_1 /* cpu state was modified dynamically */
 147 /* These instructions trap after executing, so the A32/T32 decoder must
 148  * defer them until after the conditional execution state has been updated.
 149  * WFI also needs special handling when single-stepping.
 150  */
 151 #define DISAS_WFI       DISAS_TARGET_2
 152 #define DISAS_SWI       DISAS_TARGET_3
 153 /* WFE */
 154 #define DISAS_WFE       DISAS_TARGET_4
 155 #define DISAS_HVC       DISAS_TARGET_5
 156 #define DISAS_SMC       DISAS_TARGET_6
 157 #define DISAS_YIELD     DISAS_TARGET_7
 158 /* M profile branch which might be an exception return (and so needs
 159  * custom end-of-TB code)
 160  */
 161 #define DISAS_BX_EXCRET DISAS_TARGET_8
 162 /* For instructions which want an immediate exit to the main loop,
 163  * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 164  * DISAS_UPDATE this doesn't write the PC on exiting the translation
 165  * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 166  * helper) has done so before we reach return from cpu_tb_exec.
 167  */
 168 #define DISAS_EXIT      DISAS_TARGET_9
 169
 170 #ifdef TARGET_AARCH64
 171 void a64_translate_init(void);
 172 void gen_a64_set_pc_im(uint64_t val);
 173 extern const TranslatorOps aarch64_translator_ops;
 174 #else
 175 static inline void a64_translate_init(void)
 176 {
 177 }
 178
 179 static inline void gen_a64_set_pc_im(uint64_t val)
 180 {
 181 }
 182 #endif
 183
 184 void arm_test_cc(DisasCompare *cmp, int cc);
 185 void arm_free_cc(DisasCompare *cmp);
 186 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 187 void arm_gen_test_cc(int cc, TCGLabel *label);
 188
 189 /* Return state of Alternate Half-precision flag, caller frees result */
 190 static inline TCGv_i32 get_ahp_flag(void)
 191 {
 192     TCGv_i32 ret = tcg_temp_new_i32();
 193
 194     tcg_gen_ld_i32(ret, cpu_env,
 195                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 196     tcg_gen_extract_i32(ret, ret, 26, 1);
 197
 198     return ret;
 199 }
 200
 201 /* Set bits within PSTATE.  */
 202 static inline void set_pstate_bits(uint32_t bits)
 203 {
 204     TCGv_i32 p = tcg_temp_new_i32();
 205
 206     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 207
 208     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 209     tcg_gen_ori_i32(p, p, bits);
 210     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 211     tcg_temp_free_i32(p);
 212 }
 213
 214 /* Clear bits within PSTATE.  */
 215 static inline void clear_pstate_bits(uint32_t bits)
 216 {
 217     TCGv_i32 p = tcg_temp_new_i32();
 218
 219     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 220
 221     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 222     tcg_gen_andi_i32(p, p, ~bits);
 223     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 224     tcg_temp_free_i32(p);
 225 }
 226
 227 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 228 static inline void gen_ss_advance(DisasContext *s)
 229 {
 230     if (s->ss_active) {
 231         s->pstate_ss = 0;
 232         clear_pstate_bits(PSTATE_SS);
 233     }
 234 }
 235
 236 static inline void gen_exception(int excp, uint32_t syndrome,
 237                                  uint32_t target_el)
 238 {
 239     TCGv_i32 tcg_excp = tcg_const_i32(excp);
 240     TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
 241     TCGv_i32 tcg_el = tcg_const_i32(target_el);
 242
 243     gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
 244                                        tcg_syn, tcg_el);
 245
 246     tcg_temp_free_i32(tcg_el);
 247     tcg_temp_free_i32(tcg_syn);
 248     tcg_temp_free_i32(tcg_excp);
 249 }
 250
 251 /* Generate an architectural singlestep exception */
 252 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 253 {
 254     gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
 255                   default_exception_el(s));
 256 }
 257
 258 /*
 259  * Given a VFP floating point constant encoded into an 8 bit immediate in an
 260  * instruction, expand it to the actual constant value of the specified
 261  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
 262  */
 263 uint64_t vfp_expand_imm(int size, uint8_t imm8);
 264
 265 /* Vector operations shared between ARM and AArch64.  */
 266 extern const GVecGen3 mla_op[4];
 267 extern const GVecGen3 mls_op[4];
 268 extern const GVecGen3 cmtst_op[4];
 269 extern const GVecGen2i ssra_op[4];
 270 extern const GVecGen2i usra_op[4];
 271 extern const GVecGen2i sri_op[4];
 272 extern const GVecGen2i sli_op[4];
 273 extern const GVecGen4 uqadd_op[4];
 274 extern const GVecGen4 sqadd_op[4];
 275 extern const GVecGen4 uqsub_op[4];
 276 extern const GVecGen4 sqsub_op[4];
 277 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 278
 279 /*
 280  * Forward to the isar_feature_* tests given a DisasContext pointer.
 281  */
 282 #define dc_isar_feature(name, ctx) \
 283     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 284
 285 #endif /* TARGET_ARM_TRANSLATE_H */