target-openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu-common.h"
  22
  23 /* CPUClass::reset() */
  24 static void openrisc_cpu_reset(CPUState *s)
  25 {
  26     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  27     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  28
  29     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  30         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  31         log_cpu_state(&cpu->env, 0);
  32     }
  33
  34     occ->parent_reset(s);
  35
  36     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
  37
  38     tlb_flush(&cpu->env, 1);
  39     /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
  40
  41     cpu->env.pc = 0x100;
  42     cpu->env.sr = SR_FO | SR_SM;
  43     cpu->env.exception_index = -1;
  44
  45     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  46     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  47     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  48     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  49
  50 #ifndef CONFIG_USER_ONLY
  51     cpu->env.picmr = 0x00000000;
  52     cpu->env.picsr = 0x00000000;
  53
  54     cpu->env.ttmr = 0x00000000;
  55     cpu->env.ttcr = 0x00000000;
  56 #endif
  57 }
  58
  59 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  60 {
  61     cpu->feature |= feature;
  62     cpu->env.cpucfgr = cpu->feature;
  63 }
  64
  65 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  66 {
  67     OpenRISCCPU *cpu = OPENRISC_CPU(dev);
  68     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  69
  70     qemu_init_vcpu(&cpu->env);
  71     cpu_reset(CPU(cpu));
  72
  73     occ->parent_realize(dev, errp);
  74 }
  75
  76 static void openrisc_cpu_initfn(Object *obj)
  77 {
  78     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  79     static int inited;
  80
  81     cpu_exec_init(&cpu->env);
  82
  83 #ifndef CONFIG_USER_ONLY
  84     cpu_openrisc_mmu_init(cpu);
  85 #endif
  86
  87     if (tcg_enabled() && !inited) {
  88         inited = 1;
  89         openrisc_translate_init();
  90     }
  91 }
  92
  93 /* CPU models */
  94
  95 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
  96 {
  97     ObjectClass *oc;
  98
  99     if (cpu_model == NULL) {
 100         return NULL;
 101     }
 102
 103     oc = object_class_by_name(cpu_model);
 104     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 105                        object_class_is_abstract(oc))) {
 106         return NULL;
 107     }
 108     return oc;
 109 }
 110
 111 static void or1200_initfn(Object *obj)
 112 {
 113     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 114
 115     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 116     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 117 }
 118
 119 static void openrisc_any_initfn(Object *obj)
 120 {
 121     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 122
 123     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 124 }
 125
 126 typedef struct OpenRISCCPUInfo {
 127     const char *name;
 128     void (*initfn)(Object *obj);
 129 } OpenRISCCPUInfo;
 130
 131 static const OpenRISCCPUInfo openrisc_cpus[] = {
 132     { .name = "or1200",      .initfn = or1200_initfn },
 133     { .name = "any",         .initfn = openrisc_any_initfn },
 134 };
 135
 136 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 137 {
 138     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 139     CPUClass *cc = CPU_CLASS(occ);
 140     DeviceClass *dc = DEVICE_CLASS(oc);
 141
 142     occ->parent_realize = dc->realize;
 143     dc->realize = openrisc_cpu_realizefn;
 144
 145     occ->parent_reset = cc->reset;
 146     cc->reset = openrisc_cpu_reset;
 147
 148     cc->class_by_name = openrisc_cpu_class_by_name;
 149 }
 150
 151 static void cpu_register(const OpenRISCCPUInfo *info)
 152 {
 153     TypeInfo type_info = {
 154         .parent = TYPE_OPENRISC_CPU,
 155         .instance_size = sizeof(OpenRISCCPU),
 156         .instance_init = info->initfn,
 157         .class_size = sizeof(OpenRISCCPUClass),
 158     };
 159
 160     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 161     type_register(&type_info);
 162     g_free((void *)type_info.name);
 163 }
 164
 165 static const TypeInfo openrisc_cpu_type_info = {
 166     .name = TYPE_OPENRISC_CPU,
 167     .parent = TYPE_CPU,
 168     .instance_size = sizeof(OpenRISCCPU),
 169     .instance_init = openrisc_cpu_initfn,
 170     .abstract = true,
 171     .class_size = sizeof(OpenRISCCPUClass),
 172     .class_init = openrisc_cpu_class_init,
 173 };
 174
 175 static void openrisc_cpu_register_types(void)
 176 {
 177     int i;
 178
 179     type_register_static(&openrisc_cpu_type_info);
 180     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 181         cpu_register(&openrisc_cpus[i]);
 182     }
 183 }
 184
 185 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 186 {
 187     OpenRISCCPU *cpu;
 188     ObjectClass *oc;
 189
 190     oc = openrisc_cpu_class_by_name(cpu_model);
 191     if (oc == NULL) {
 192         return NULL;
 193     }
 194     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
 195     cpu->env.cpu_model_str = cpu_model;
 196
 197     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 198
 199     return cpu;
 200 }
 201
 202 /* Sort alphabetically by type name, except for "any". */
 203 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 204 {
 205     ObjectClass *class_a = (ObjectClass *)a;
 206     ObjectClass *class_b = (ObjectClass *)b;
 207     const char *name_a, *name_b;
 208
 209     name_a = object_class_get_name(class_a);
 210     name_b = object_class_get_name(class_b);
 211     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 212         return 1;
 213     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 214         return -1;
 215     } else {
 216         return strcmp(name_a, name_b);
 217     }
 218 }
 219
 220 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 221 {
 222     ObjectClass *oc = data;
 223     CPUListState *s = user_data;
 224     const char *typename;
 225     char *name;
 226
 227     typename = object_class_get_name(oc);
 228     name = g_strndup(typename,
 229                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 230     (*s->cpu_fprintf)(s->file, "  %s\n",
 231                       name);
 232     g_free(name);
 233 }
 234
 235 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 236 {
 237     CPUListState s = {
 238         .file = f,
 239         .cpu_fprintf = cpu_fprintf,
 240     };
 241     GSList *list;
 242
 243     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 244     list = g_slist_sort(list, openrisc_cpu_list_compare);
 245     (*cpu_fprintf)(f, "Available CPUs:\n");
 246     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 247     g_slist_free(list);
 248 }
 249
 250 type_init(openrisc_cpu_register_types)