target-mips: Introduce QOM realizefn for MIPSCPU
[qemu/ar7.git] / hw / serial.h
blob98ee4241be05eee51918a69cc2c163c28f89ee0c
1 /*
2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
25 #ifndef HW_SERIAL_H
26 #define HW_SERIAL_H 1
28 #include "hw.h"
29 #include "sysemu/sysemu.h"
30 #include "exec/memory.h"
32 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
34 typedef struct SerialFIFO {
35 uint8_t data[UART_FIFO_LENGTH];
36 uint8_t count;
37 uint8_t itl; /* Interrupt Trigger Level */
38 uint8_t tail;
39 uint8_t head;
40 } SerialFIFO;
42 struct SerialState {
43 uint16_t divider;
44 uint8_t rbr; /* receive register */
45 uint8_t thr; /* transmit holding register */
46 uint8_t tsr; /* transmit shift register */
47 uint8_t ier;
48 uint8_t iir; /* read only */
49 uint8_t lcr;
50 uint8_t mcr;
51 uint8_t lsr; /* read only */
52 uint8_t msr; /* read only */
53 uint8_t scr;
54 uint8_t fcr;
55 uint8_t fcr_vmstate; /* we can't write directly this value
56 it has side effects */
57 /* NOTE: this hidden state is necessary for tx irq generation as
58 it can be reset while reading iir */
59 int thr_ipending;
60 qemu_irq irq;
61 CharDriverState *chr;
62 int last_break_enable;
63 int it_shift;
64 int baudbase;
65 int tsr_retry;
66 uint32_t wakeup;
68 /* Time when the last byte was successfully sent out of the tsr */
69 uint64_t last_xmit_ts;
70 SerialFIFO recv_fifo;
71 SerialFIFO xmit_fifo;
73 struct QEMUTimer *fifo_timeout_timer;
74 int timeout_ipending; /* timeout interrupt pending state */
75 struct QEMUTimer *transmit_timer;
78 uint64_t char_transmit_time; /* time to transmit a char in ticks */
79 int poll_msl;
81 struct QEMUTimer *modem_status_poll;
82 MemoryRegion io;
85 extern const VMStateDescription vmstate_serial;
86 extern const MemoryRegionOps serial_io_ops;
88 void serial_init_core(SerialState *s);
89 void serial_exit_core(SerialState *s);
90 void serial_set_frequency(SerialState *s, uint32_t frequency);
92 /* legacy pre qom */
93 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
94 CharDriverState *chr, MemoryRegion *system_io);
95 SerialState *serial_mm_init(MemoryRegion *address_space,
96 hwaddr base, int it_shift,
97 qemu_irq irq, int baudbase,
98 CharDriverState *chr, enum device_endian end);
100 /* serial-isa.c */
101 bool serial_isa_init(ISABus *bus, int index, CharDriverState *chr);
103 #endif