2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/timer.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
27 #include "sysemu/dma.h"
29 /* --------------------------------------------------------------------- */
32 static Property hda_props
[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice
, cad
, -1),
34 DEFINE_PROP_END_OF_LIST()
37 static const TypeInfo hda_codec_bus_info
= {
40 .instance_size
= sizeof(HDACodecBus
),
43 void hda_codec_bus_init(DeviceState
*dev
, HDACodecBus
*bus
,
44 hda_codec_response_func response
,
45 hda_codec_xfer_func xfer
)
47 qbus_create_inplace(&bus
->qbus
, TYPE_HDA_BUS
, dev
, NULL
);
48 bus
->response
= response
;
52 static int hda_codec_dev_init(DeviceState
*qdev
)
54 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, qdev
->parent_bus
);
55 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
56 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
59 dev
->cad
= bus
->next_cad
;
64 bus
->next_cad
= dev
->cad
+ 1;
65 return cdc
->init(dev
);
68 static int hda_codec_dev_exit(DeviceState
*qdev
)
70 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
71 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
79 HDACodecDevice
*hda_codec_find(HDACodecBus
*bus
, uint32_t cad
)
84 QTAILQ_FOREACH(kid
, &bus
->qbus
.children
, sibling
) {
85 DeviceState
*qdev
= kid
->child
;
86 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
87 if (cdev
->cad
== cad
) {
94 void hda_codec_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
96 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
97 bus
->response(dev
, solicited
, response
);
100 bool hda_codec_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
101 uint8_t *buf
, uint32_t len
)
103 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
104 return bus
->xfer(dev
, stnr
, output
, buf
, len
);
107 /* --------------------------------------------------------------------- */
108 /* intel hda emulation */
110 typedef struct IntelHDAStream IntelHDAStream
;
111 typedef struct IntelHDAState IntelHDAState
;
112 typedef struct IntelHDAReg IntelHDAReg
;
120 struct IntelHDAStream
{
133 uint32_t bsize
, be
, bp
;
136 struct IntelHDAState
{
173 IntelHDAStream st
[8];
178 int64_t wall_base_ns
;
181 const IntelHDAReg
*last_reg
;
185 uint32_t repeat_count
;
193 const char *name
; /* register name */
194 uint32_t size
; /* size in bytes */
195 uint32_t reset
; /* reset value */
196 uint32_t wmask
; /* write mask */
197 uint32_t wclear
; /* write 1 to clear bits */
198 uint32_t offset
; /* location in IntelHDAState */
199 uint32_t shift
; /* byte access entries for dwords */
201 void (*whandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
);
202 void (*rhandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
);
205 static void intel_hda_reset(DeviceState
*dev
);
207 /* --------------------------------------------------------------------- */
209 static hwaddr
intel_hda_addr(uint32_t lbase
, uint32_t ubase
)
213 addr
= ((uint64_t)ubase
<< 32) | lbase
;
217 static void intel_hda_update_int_sts(IntelHDAState
*d
)
222 /* update controller status */
223 if (d
->rirb_sts
& ICH6_RBSTS_IRQ
) {
226 if (d
->rirb_sts
& ICH6_RBSTS_OVERRUN
) {
229 if (d
->state_sts
& d
->wake_en
) {
233 /* update stream status */
234 for (i
= 0; i
< 8; i
++) {
235 /* buffer completion interrupt */
236 if (d
->st
[i
].ctl
& (1 << 26)) {
241 /* update global status */
242 if (sts
& d
->int_ctl
) {
249 static void intel_hda_update_irq(IntelHDAState
*d
)
251 int msi
= d
->msi
&& msi_enabled(&d
->pci
);
254 intel_hda_update_int_sts(d
);
255 if (d
->int_sts
& (1 << 31) && d
->int_ctl
& (1 << 31)) {
260 dprint(d
, 2, "%s: level %d [%s]\n", __FUNCTION__
,
261 level
, msi
? "msi" : "intx");
264 msi_notify(&d
->pci
, 0);
267 qemu_set_irq(d
->pci
.irq
[0], level
);
271 static int intel_hda_send_command(IntelHDAState
*d
, uint32_t verb
)
273 uint32_t cad
, nid
, data
;
274 HDACodecDevice
*codec
;
275 HDACodecDeviceClass
*cdc
;
277 cad
= (verb
>> 28) & 0x0f;
278 if (verb
& (1 << 27)) {
279 /* indirect node addressing, not specified in HDA 1.0 */
280 dprint(d
, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__
);
283 nid
= (verb
>> 20) & 0x7f;
284 data
= verb
& 0xfffff;
286 codec
= hda_codec_find(&d
->codecs
, cad
);
288 dprint(d
, 1, "%s: addressed non-existing codec\n", __FUNCTION__
);
291 cdc
= HDA_CODEC_DEVICE_GET_CLASS(codec
);
292 cdc
->command(codec
, nid
, data
);
296 static void intel_hda_corb_run(IntelHDAState
*d
)
301 if (d
->ics
& ICH6_IRS_BUSY
) {
302 dprint(d
, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__
, d
->icw
);
303 intel_hda_send_command(d
, d
->icw
);
308 if (!(d
->corb_ctl
& ICH6_CORBCTL_RUN
)) {
309 dprint(d
, 2, "%s: !run\n", __FUNCTION__
);
312 if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
313 dprint(d
, 2, "%s: corb ring empty\n", __FUNCTION__
);
316 if (d
->rirb_count
== d
->rirb_cnt
) {
317 dprint(d
, 2, "%s: rirb count reached\n", __FUNCTION__
);
321 rp
= (d
->corb_rp
+ 1) & 0xff;
322 addr
= intel_hda_addr(d
->corb_lbase
, d
->corb_ubase
);
323 verb
= ldl_le_pci_dma(&d
->pci
, addr
+ 4*rp
);
326 dprint(d
, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__
, rp
, verb
);
327 intel_hda_send_command(d
, verb
);
331 static void intel_hda_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
333 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
334 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
338 if (d
->ics
& ICH6_IRS_BUSY
) {
339 dprint(d
, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
340 __FUNCTION__
, response
, dev
->cad
);
342 d
->ics
&= ~(ICH6_IRS_BUSY
| 0xf0);
343 d
->ics
|= (ICH6_IRS_VALID
| (dev
->cad
<< 4));
347 if (!(d
->rirb_ctl
& ICH6_RBCTL_DMA_EN
)) {
348 dprint(d
, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__
);
352 ex
= (solicited
? 0 : (1 << 4)) | dev
->cad
;
353 wp
= (d
->rirb_wp
+ 1) & 0xff;
354 addr
= intel_hda_addr(d
->rirb_lbase
, d
->rirb_ubase
);
355 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
, response
);
356 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
+ 4, ex
);
359 dprint(d
, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
360 __FUNCTION__
, wp
, response
, ex
);
363 if (d
->rirb_count
== d
->rirb_cnt
) {
364 dprint(d
, 2, "%s: rirb count reached (%d)\n", __FUNCTION__
, d
->rirb_count
);
365 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
366 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
367 intel_hda_update_irq(d
);
369 } else if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
370 dprint(d
, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__
,
371 d
->rirb_count
, d
->rirb_cnt
);
372 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
373 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
374 intel_hda_update_irq(d
);
379 static bool intel_hda_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
380 uint8_t *buf
, uint32_t len
)
382 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
383 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
385 uint32_t s
, copy
, left
;
389 st
= output
? d
->st
+ 4 : d
->st
;
390 for (s
= 0; s
< 4; s
++) {
391 if (stnr
== ((st
[s
].ctl
>> 20) & 0x0f)) {
399 if (st
->bpl
== NULL
) {
402 if (st
->ctl
& (1 << 26)) {
404 * Wait with the next DMA xfer until the guest
405 * has acked the buffer completion interrupt
413 if (copy
> st
->bsize
- st
->lpib
)
414 copy
= st
->bsize
- st
->lpib
;
415 if (copy
> st
->bpl
[st
->be
].len
- st
->bp
)
416 copy
= st
->bpl
[st
->be
].len
- st
->bp
;
418 dprint(d
, 3, "dma: entry %d, pos %d/%d, copy %d\n",
419 st
->be
, st
->bp
, st
->bpl
[st
->be
].len
, copy
);
421 pci_dma_rw(&d
->pci
, st
->bpl
[st
->be
].addr
+ st
->bp
, buf
, copy
, !output
);
427 if (st
->bpl
[st
->be
].len
== st
->bp
) {
428 /* bpl entry filled */
429 if (st
->bpl
[st
->be
].flags
& 0x01) {
434 if (st
->be
== st
->bentries
) {
435 /* bpl wrap around */
441 if (d
->dp_lbase
& 0x01) {
442 addr
= intel_hda_addr(d
->dp_lbase
& ~0x01, d
->dp_ubase
);
443 stl_le_pci_dma(&d
->pci
, addr
+ 8*s
, st
->lpib
);
445 dprint(d
, 3, "dma: --\n");
448 st
->ctl
|= (1 << 26); /* buffer completion interrupt */
449 intel_hda_update_irq(d
);
454 static void intel_hda_parse_bdl(IntelHDAState
*d
, IntelHDAStream
*st
)
460 addr
= intel_hda_addr(st
->bdlp_lbase
, st
->bdlp_ubase
);
461 st
->bentries
= st
->lvi
+1;
463 st
->bpl
= g_malloc(sizeof(bpl
) * st
->bentries
);
464 for (i
= 0; i
< st
->bentries
; i
++, addr
+= 16) {
465 pci_dma_read(&d
->pci
, addr
, buf
, 16);
466 st
->bpl
[i
].addr
= le64_to_cpu(*(uint64_t *)buf
);
467 st
->bpl
[i
].len
= le32_to_cpu(*(uint32_t *)(buf
+ 8));
468 st
->bpl
[i
].flags
= le32_to_cpu(*(uint32_t *)(buf
+ 12));
469 dprint(d
, 1, "bdl/%d: 0x%" PRIx64
" +0x%x, 0x%x\n",
470 i
, st
->bpl
[i
].addr
, st
->bpl
[i
].len
, st
->bpl
[i
].flags
);
479 static void intel_hda_notify_codecs(IntelHDAState
*d
, uint32_t stream
, bool running
, bool output
)
482 HDACodecDevice
*cdev
;
484 QTAILQ_FOREACH(kid
, &d
->codecs
.qbus
.children
, sibling
) {
485 DeviceState
*qdev
= kid
->child
;
486 HDACodecDeviceClass
*cdc
;
488 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
489 cdc
= HDA_CODEC_DEVICE_GET_CLASS(cdev
);
491 cdc
->stream(cdev
, stream
, running
, output
);
496 /* --------------------------------------------------------------------- */
498 static void intel_hda_set_g_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
500 if ((d
->g_ctl
& ICH6_GCTL_RESET
) == 0) {
501 intel_hda_reset(&d
->pci
.qdev
);
505 static void intel_hda_set_wake_en(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
507 intel_hda_update_irq(d
);
510 static void intel_hda_set_state_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
512 intel_hda_update_irq(d
);
515 static void intel_hda_set_int_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
517 intel_hda_update_irq(d
);
520 static void intel_hda_get_wall_clk(IntelHDAState
*d
, const IntelHDAReg
*reg
)
524 ns
= qemu_get_clock_ns(vm_clock
) - d
->wall_base_ns
;
525 d
->wall_clk
= (uint32_t)(ns
* 24 / 1000); /* 24 MHz */
528 static void intel_hda_set_corb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
530 intel_hda_corb_run(d
);
533 static void intel_hda_set_corb_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
535 intel_hda_corb_run(d
);
538 static void intel_hda_set_rirb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
540 if (d
->rirb_wp
& ICH6_RIRBWP_RST
) {
545 static void intel_hda_set_rirb_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
547 intel_hda_update_irq(d
);
549 if ((old
& ICH6_RBSTS_IRQ
) && !(d
->rirb_sts
& ICH6_RBSTS_IRQ
)) {
550 /* cleared ICH6_RBSTS_IRQ */
552 intel_hda_corb_run(d
);
556 static void intel_hda_set_ics(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
558 if (d
->ics
& ICH6_IRS_BUSY
) {
559 intel_hda_corb_run(d
);
563 static void intel_hda_set_st_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
565 bool output
= reg
->stream
>= 4;
566 IntelHDAStream
*st
= d
->st
+ reg
->stream
;
568 if (st
->ctl
& 0x01) {
570 dprint(d
, 1, "st #%d: reset\n", reg
->stream
);
573 if ((st
->ctl
& 0x02) != (old
& 0x02)) {
574 uint32_t stnr
= (st
->ctl
>> 20) & 0x0f;
575 /* run bit flipped */
576 if (st
->ctl
& 0x02) {
578 dprint(d
, 1, "st #%d: start %d (ring buf %d bytes)\n",
579 reg
->stream
, stnr
, st
->cbl
);
580 intel_hda_parse_bdl(d
, st
);
581 intel_hda_notify_codecs(d
, stnr
, true, output
);
584 dprint(d
, 1, "st #%d: stop %d\n", reg
->stream
, stnr
);
585 intel_hda_notify_codecs(d
, stnr
, false, output
);
588 intel_hda_update_irq(d
);
591 /* --------------------------------------------------------------------- */
593 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
595 static const struct IntelHDAReg regtab
[] = {
597 [ ICH6_REG_GCAP
] = {
602 [ ICH6_REG_VMIN
] = {
606 [ ICH6_REG_VMAJ
] = {
611 [ ICH6_REG_OUTPAY
] = {
616 [ ICH6_REG_INPAY
] = {
621 [ ICH6_REG_GCTL
] = {
625 .offset
= offsetof(IntelHDAState
, g_ctl
),
626 .whandler
= intel_hda_set_g_ctl
,
628 [ ICH6_REG_WAKEEN
] = {
632 .offset
= offsetof(IntelHDAState
, wake_en
),
633 .whandler
= intel_hda_set_wake_en
,
635 [ ICH6_REG_STATESTS
] = {
640 .offset
= offsetof(IntelHDAState
, state_sts
),
641 .whandler
= intel_hda_set_state_sts
,
645 [ ICH6_REG_INTCTL
] = {
649 .offset
= offsetof(IntelHDAState
, int_ctl
),
650 .whandler
= intel_hda_set_int_ctl
,
652 [ ICH6_REG_INTSTS
] = {
656 .wclear
= 0xc00000ff,
657 .offset
= offsetof(IntelHDAState
, int_sts
),
661 [ ICH6_REG_WALLCLK
] = {
664 .offset
= offsetof(IntelHDAState
, wall_clk
),
665 .rhandler
= intel_hda_get_wall_clk
,
667 [ ICH6_REG_WALLCLK
+ 0x2000 ] = {
668 .name
= "WALLCLK(alias)",
670 .offset
= offsetof(IntelHDAState
, wall_clk
),
671 .rhandler
= intel_hda_get_wall_clk
,
675 [ ICH6_REG_CORBLBASE
] = {
679 .offset
= offsetof(IntelHDAState
, corb_lbase
),
681 [ ICH6_REG_CORBUBASE
] = {
685 .offset
= offsetof(IntelHDAState
, corb_ubase
),
687 [ ICH6_REG_CORBWP
] = {
691 .offset
= offsetof(IntelHDAState
, corb_wp
),
692 .whandler
= intel_hda_set_corb_wp
,
694 [ ICH6_REG_CORBRP
] = {
698 .offset
= offsetof(IntelHDAState
, corb_rp
),
700 [ ICH6_REG_CORBCTL
] = {
704 .offset
= offsetof(IntelHDAState
, corb_ctl
),
705 .whandler
= intel_hda_set_corb_ctl
,
707 [ ICH6_REG_CORBSTS
] = {
712 .offset
= offsetof(IntelHDAState
, corb_sts
),
714 [ ICH6_REG_CORBSIZE
] = {
718 .offset
= offsetof(IntelHDAState
, corb_size
),
720 [ ICH6_REG_RIRBLBASE
] = {
724 .offset
= offsetof(IntelHDAState
, rirb_lbase
),
726 [ ICH6_REG_RIRBUBASE
] = {
730 .offset
= offsetof(IntelHDAState
, rirb_ubase
),
732 [ ICH6_REG_RIRBWP
] = {
736 .offset
= offsetof(IntelHDAState
, rirb_wp
),
737 .whandler
= intel_hda_set_rirb_wp
,
739 [ ICH6_REG_RINTCNT
] = {
743 .offset
= offsetof(IntelHDAState
, rirb_cnt
),
745 [ ICH6_REG_RIRBCTL
] = {
749 .offset
= offsetof(IntelHDAState
, rirb_ctl
),
751 [ ICH6_REG_RIRBSTS
] = {
756 .offset
= offsetof(IntelHDAState
, rirb_sts
),
757 .whandler
= intel_hda_set_rirb_sts
,
759 [ ICH6_REG_RIRBSIZE
] = {
763 .offset
= offsetof(IntelHDAState
, rirb_size
),
766 [ ICH6_REG_DPLBASE
] = {
770 .offset
= offsetof(IntelHDAState
, dp_lbase
),
772 [ ICH6_REG_DPUBASE
] = {
776 .offset
= offsetof(IntelHDAState
, dp_ubase
),
783 .offset
= offsetof(IntelHDAState
, icw
),
788 .offset
= offsetof(IntelHDAState
, irr
),
795 .offset
= offsetof(IntelHDAState
, ics
),
796 .whandler
= intel_hda_set_ics
,
799 #define HDA_STREAM(_t, _i) \
800 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
802 .name = _t stringify(_i) " CTL", \
804 .wmask = 0x1cff001f, \
805 .offset = offsetof(IntelHDAState, st[_i].ctl), \
806 .whandler = intel_hda_set_st_ctl, \
808 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
810 .name = _t stringify(_i) " CTL(stnr)", \
813 .wmask = 0x00ff0000, \
814 .offset = offsetof(IntelHDAState, st[_i].ctl), \
815 .whandler = intel_hda_set_st_ctl, \
817 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
819 .name = _t stringify(_i) " CTL(sts)", \
822 .wmask = 0x1c000000, \
823 .wclear = 0x1c000000, \
824 .offset = offsetof(IntelHDAState, st[_i].ctl), \
825 .whandler = intel_hda_set_st_ctl, \
827 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
829 .name = _t stringify(_i) " LPIB", \
831 .offset = offsetof(IntelHDAState, st[_i].lpib), \
833 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
835 .name = _t stringify(_i) " LPIB(alias)", \
837 .offset = offsetof(IntelHDAState, st[_i].lpib), \
839 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
841 .name = _t stringify(_i) " CBL", \
843 .wmask = 0xffffffff, \
844 .offset = offsetof(IntelHDAState, st[_i].cbl), \
846 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
848 .name = _t stringify(_i) " LVI", \
851 .offset = offsetof(IntelHDAState, st[_i].lvi), \
853 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
855 .name = _t stringify(_i) " FIFOS", \
857 .reset = HDA_BUFFER_SIZE, \
859 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
861 .name = _t stringify(_i) " FMT", \
864 .offset = offsetof(IntelHDAState, st[_i].fmt), \
866 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
868 .name = _t stringify(_i) " BDLPL", \
870 .wmask = 0xffffff80, \
871 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
873 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
875 .name = _t stringify(_i) " BDLPU", \
877 .wmask = 0xffffffff, \
878 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
893 static const IntelHDAReg
*intel_hda_reg_find(IntelHDAState
*d
, hwaddr addr
)
895 const IntelHDAReg
*reg
;
897 if (addr
>= sizeof(regtab
)/sizeof(regtab
[0])) {
901 if (reg
->name
== NULL
) {
907 dprint(d
, 1, "unknown register, addr 0x%x\n", (int) addr
);
911 static uint32_t *intel_hda_reg_addr(IntelHDAState
*d
, const IntelHDAReg
*reg
)
913 uint8_t *addr
= (void*)d
;
916 return (uint32_t*)addr
;
919 static void intel_hda_reg_write(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t val
,
930 time_t now
= time(NULL
);
931 if (d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== val
) {
933 if (d
->last_sec
!= now
) {
934 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
939 if (d
->repeat_count
) {
940 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
942 dprint(d
, 2, "write %-16s: 0x%x (%x)\n", reg
->name
, val
, wmask
);
950 assert(reg
->offset
!= 0);
952 addr
= intel_hda_reg_addr(d
, reg
);
957 wmask
<<= reg
->shift
;
961 *addr
|= wmask
& val
;
962 *addr
&= ~(val
& reg
->wclear
);
965 reg
->whandler(d
, reg
, old
);
969 static uint32_t intel_hda_reg_read(IntelHDAState
*d
, const IntelHDAReg
*reg
,
979 reg
->rhandler(d
, reg
);
982 if (reg
->offset
== 0) {
983 /* constant read-only register */
986 addr
= intel_hda_reg_addr(d
, reg
);
994 time_t now
= time(NULL
);
995 if (!d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== ret
) {
997 if (d
->last_sec
!= now
) {
998 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1000 d
->repeat_count
= 0;
1003 if (d
->repeat_count
) {
1004 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1006 dprint(d
, 2, "read %-16s: 0x%x (%x)\n", reg
->name
, ret
, rmask
);
1011 d
->repeat_count
= 0;
1017 static void intel_hda_regs_reset(IntelHDAState
*d
)
1022 for (i
= 0; i
< sizeof(regtab
)/sizeof(regtab
[0]); i
++) {
1023 if (regtab
[i
].name
== NULL
) {
1026 if (regtab
[i
].offset
== 0) {
1029 addr
= intel_hda_reg_addr(d
, regtab
+ i
);
1030 *addr
= regtab
[i
].reset
;
1034 /* --------------------------------------------------------------------- */
1036 static void intel_hda_mmio_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
1038 IntelHDAState
*d
= opaque
;
1039 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1041 intel_hda_reg_write(d
, reg
, val
, 0xff);
1044 static void intel_hda_mmio_writew(void *opaque
, hwaddr addr
, uint32_t val
)
1046 IntelHDAState
*d
= opaque
;
1047 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1049 intel_hda_reg_write(d
, reg
, val
, 0xffff);
1052 static void intel_hda_mmio_writel(void *opaque
, hwaddr addr
, uint32_t val
)
1054 IntelHDAState
*d
= opaque
;
1055 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1057 intel_hda_reg_write(d
, reg
, val
, 0xffffffff);
1060 static uint32_t intel_hda_mmio_readb(void *opaque
, hwaddr addr
)
1062 IntelHDAState
*d
= opaque
;
1063 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1065 return intel_hda_reg_read(d
, reg
, 0xff);
1068 static uint32_t intel_hda_mmio_readw(void *opaque
, hwaddr addr
)
1070 IntelHDAState
*d
= opaque
;
1071 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1073 return intel_hda_reg_read(d
, reg
, 0xffff);
1076 static uint32_t intel_hda_mmio_readl(void *opaque
, hwaddr addr
)
1078 IntelHDAState
*d
= opaque
;
1079 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1081 return intel_hda_reg_read(d
, reg
, 0xffffffff);
1084 static const MemoryRegionOps intel_hda_mmio_ops
= {
1087 intel_hda_mmio_readb
,
1088 intel_hda_mmio_readw
,
1089 intel_hda_mmio_readl
,
1092 intel_hda_mmio_writeb
,
1093 intel_hda_mmio_writew
,
1094 intel_hda_mmio_writel
,
1097 .endianness
= DEVICE_NATIVE_ENDIAN
,
1100 /* --------------------------------------------------------------------- */
1102 static void intel_hda_reset(DeviceState
*dev
)
1105 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
.qdev
, dev
);
1106 HDACodecDevice
*cdev
;
1108 intel_hda_regs_reset(d
);
1109 d
->wall_base_ns
= qemu_get_clock_ns(vm_clock
);
1112 QTAILQ_FOREACH(kid
, &d
->codecs
.qbus
.children
, sibling
) {
1113 DeviceState
*qdev
= kid
->child
;
1114 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
1115 device_reset(DEVICE(cdev
));
1116 d
->state_sts
|= (1 << cdev
->cad
);
1118 intel_hda_update_irq(d
);
1121 static int intel_hda_init(PCIDevice
*pci
)
1123 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1124 uint8_t *conf
= d
->pci
.config
;
1126 d
->name
= object_get_typename(OBJECT(d
));
1128 pci_config_set_interrupt_pin(conf
, 1);
1130 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1133 memory_region_init_io(&d
->mmio
, &intel_hda_mmio_ops
, d
,
1134 "intel-hda", 0x4000);
1135 pci_register_bar(&d
->pci
, 0, 0, &d
->mmio
);
1137 msi_init(&d
->pci
, 0x50, 1, true, false);
1140 hda_codec_bus_init(&d
->pci
.qdev
, &d
->codecs
,
1141 intel_hda_response
, intel_hda_xfer
);
1146 static void intel_hda_exit(PCIDevice
*pci
)
1148 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1150 msi_uninit(&d
->pci
);
1151 memory_region_destroy(&d
->mmio
);
1154 static int intel_hda_post_load(void *opaque
, int version
)
1156 IntelHDAState
* d
= opaque
;
1159 dprint(d
, 1, "%s\n", __FUNCTION__
);
1160 for (i
= 0; i
< ARRAY_SIZE(d
->st
); i
++) {
1161 if (d
->st
[i
].ctl
& 0x02) {
1162 intel_hda_parse_bdl(d
, &d
->st
[i
]);
1165 intel_hda_update_irq(d
);
1169 static const VMStateDescription vmstate_intel_hda_stream
= {
1170 .name
= "intel-hda-stream",
1172 .fields
= (VMStateField
[]) {
1173 VMSTATE_UINT32(ctl
, IntelHDAStream
),
1174 VMSTATE_UINT32(lpib
, IntelHDAStream
),
1175 VMSTATE_UINT32(cbl
, IntelHDAStream
),
1176 VMSTATE_UINT32(lvi
, IntelHDAStream
),
1177 VMSTATE_UINT32(fmt
, IntelHDAStream
),
1178 VMSTATE_UINT32(bdlp_lbase
, IntelHDAStream
),
1179 VMSTATE_UINT32(bdlp_ubase
, IntelHDAStream
),
1180 VMSTATE_END_OF_LIST()
1184 static const VMStateDescription vmstate_intel_hda
= {
1185 .name
= "intel-hda",
1187 .post_load
= intel_hda_post_load
,
1188 .fields
= (VMStateField
[]) {
1189 VMSTATE_PCI_DEVICE(pci
, IntelHDAState
),
1192 VMSTATE_UINT32(g_ctl
, IntelHDAState
),
1193 VMSTATE_UINT32(wake_en
, IntelHDAState
),
1194 VMSTATE_UINT32(state_sts
, IntelHDAState
),
1195 VMSTATE_UINT32(int_ctl
, IntelHDAState
),
1196 VMSTATE_UINT32(int_sts
, IntelHDAState
),
1197 VMSTATE_UINT32(wall_clk
, IntelHDAState
),
1198 VMSTATE_UINT32(corb_lbase
, IntelHDAState
),
1199 VMSTATE_UINT32(corb_ubase
, IntelHDAState
),
1200 VMSTATE_UINT32(corb_rp
, IntelHDAState
),
1201 VMSTATE_UINT32(corb_wp
, IntelHDAState
),
1202 VMSTATE_UINT32(corb_ctl
, IntelHDAState
),
1203 VMSTATE_UINT32(corb_sts
, IntelHDAState
),
1204 VMSTATE_UINT32(corb_size
, IntelHDAState
),
1205 VMSTATE_UINT32(rirb_lbase
, IntelHDAState
),
1206 VMSTATE_UINT32(rirb_ubase
, IntelHDAState
),
1207 VMSTATE_UINT32(rirb_wp
, IntelHDAState
),
1208 VMSTATE_UINT32(rirb_cnt
, IntelHDAState
),
1209 VMSTATE_UINT32(rirb_ctl
, IntelHDAState
),
1210 VMSTATE_UINT32(rirb_sts
, IntelHDAState
),
1211 VMSTATE_UINT32(rirb_size
, IntelHDAState
),
1212 VMSTATE_UINT32(dp_lbase
, IntelHDAState
),
1213 VMSTATE_UINT32(dp_ubase
, IntelHDAState
),
1214 VMSTATE_UINT32(icw
, IntelHDAState
),
1215 VMSTATE_UINT32(irr
, IntelHDAState
),
1216 VMSTATE_UINT32(ics
, IntelHDAState
),
1217 VMSTATE_STRUCT_ARRAY(st
, IntelHDAState
, 8, 0,
1218 vmstate_intel_hda_stream
,
1221 /* additional state info */
1222 VMSTATE_UINT32(rirb_count
, IntelHDAState
),
1223 VMSTATE_INT64(wall_base_ns
, IntelHDAState
),
1225 VMSTATE_END_OF_LIST()
1229 static Property intel_hda_properties
[] = {
1230 DEFINE_PROP_UINT32("debug", IntelHDAState
, debug
, 0),
1231 DEFINE_PROP_UINT32("msi", IntelHDAState
, msi
, 1),
1232 DEFINE_PROP_END_OF_LIST(),
1235 static void intel_hda_class_init_common(ObjectClass
*klass
)
1237 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1238 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1240 k
->init
= intel_hda_init
;
1241 k
->exit
= intel_hda_exit
;
1242 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1243 k
->class_id
= PCI_CLASS_MULTIMEDIA_HD_AUDIO
;
1244 dc
->reset
= intel_hda_reset
;
1245 dc
->vmsd
= &vmstate_intel_hda
;
1246 dc
->props
= intel_hda_properties
;
1249 static void intel_hda_class_init_ich6(ObjectClass
*klass
, void *data
)
1251 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1252 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1254 intel_hda_class_init_common(klass
);
1255 k
->device_id
= 0x2668;
1257 dc
->desc
= "Intel HD Audio Controller (ich6)";
1260 static void intel_hda_class_init_ich9(ObjectClass
*klass
, void *data
)
1262 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1263 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1265 intel_hda_class_init_common(klass
);
1266 k
->device_id
= 0x293e;
1268 dc
->desc
= "Intel HD Audio Controller (ich9)";
1271 static const TypeInfo intel_hda_info_ich6
= {
1272 .name
= "intel-hda",
1273 .parent
= TYPE_PCI_DEVICE
,
1274 .instance_size
= sizeof(IntelHDAState
),
1275 .class_init
= intel_hda_class_init_ich6
,
1278 static const TypeInfo intel_hda_info_ich9
= {
1279 .name
= "ich9-intel-hda",
1280 .parent
= TYPE_PCI_DEVICE
,
1281 .instance_size
= sizeof(IntelHDAState
),
1282 .class_init
= intel_hda_class_init_ich9
,
1285 static void hda_codec_device_class_init(ObjectClass
*klass
, void *data
)
1287 DeviceClass
*k
= DEVICE_CLASS(klass
);
1288 k
->init
= hda_codec_dev_init
;
1289 k
->exit
= hda_codec_dev_exit
;
1290 k
->bus_type
= TYPE_HDA_BUS
;
1291 k
->props
= hda_props
;
1294 static const TypeInfo hda_codec_device_type_info
= {
1295 .name
= TYPE_HDA_CODEC_DEVICE
,
1296 .parent
= TYPE_DEVICE
,
1297 .instance_size
= sizeof(HDACodecDevice
),
1299 .class_size
= sizeof(HDACodecDeviceClass
),
1300 .class_init
= hda_codec_device_class_init
,
1303 static void intel_hda_register_types(void)
1305 type_register_static(&hda_codec_bus_info
);
1306 type_register_static(&intel_hda_info_ich6
);
1307 type_register_static(&intel_hda_info_ich9
);
1308 type_register_static(&hda_codec_device_type_info
);
1311 type_init(intel_hda_register_types
)
1314 * create intel hda controller with codec attached to it,
1315 * so '-soundhw hda' works.
1317 int intel_hda_and_codec_init(PCIBus
*bus
)
1319 PCIDevice
*controller
;
1323 controller
= pci_create_simple(bus
, -1, "intel-hda");
1324 hdabus
= QLIST_FIRST(&controller
->qdev
.child_bus
);
1325 codec
= qdev_create(hdabus
, "hda-duplex");
1326 qdev_init_nofail(codec
);