target-mips: Introduce QOM realizefn for MIPSCPU
[qemu/ar7.git] / hw / alpha_typhoon.c
blobbf9aabfc08405300129072d1426bc006fb2bd9ac
1 /*
2 * DEC 21272 (TSUNAMI/TYPHOON) chipset emulation.
4 * Written by Richard Henderson.
6 * This work is licensed under the GNU GPL license version 2 or later.
7 */
9 #include "cpu.h"
10 #include "exec/exec-all.h"
11 #include "hw.h"
12 #include "devices.h"
13 #include "sysemu/sysemu.h"
14 #include "alpha_sys.h"
15 #include "exec/address-spaces.h"
18 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
20 typedef struct TyphoonCchip {
21 MemoryRegion region;
22 uint64_t misc;
23 uint64_t drir;
24 uint64_t dim[4];
25 uint32_t iic[4];
26 AlphaCPU *cpu[4];
27 } TyphoonCchip;
29 typedef struct TyphoonWindow {
30 uint32_t base_addr;
31 uint32_t mask;
32 uint32_t translated_base_pfn;
33 } TyphoonWindow;
35 typedef struct TyphoonPchip {
36 MemoryRegion region;
37 MemoryRegion reg_iack;
38 MemoryRegion reg_mem;
39 MemoryRegion reg_io;
40 MemoryRegion reg_conf;
41 uint64_t ctl;
42 TyphoonWindow win[4];
43 } TyphoonPchip;
45 #define TYPHOON_PCI_HOST_BRIDGE(obj) \
46 OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
48 typedef struct TyphoonState {
49 PCIHostState parent_obj;
51 TyphoonCchip cchip;
52 TyphoonPchip pchip;
53 MemoryRegion dchip_region;
54 MemoryRegion ram_region;
56 /* QEMU emulation state. */
57 uint32_t latch_tmp;
58 } TyphoonState;
60 /* Called when one of DRIR or DIM changes. */
61 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
63 /* If there are any non-masked interrupts, tell the cpu. */
64 if (cpu != NULL) {
65 CPUAlphaState *env = &cpu->env;
66 if (req) {
67 cpu_interrupt(env, CPU_INTERRUPT_HARD);
68 } else {
69 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
74 static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
76 CPUAlphaState *env = cpu_single_env;
77 TyphoonState *s = opaque;
78 CPUState *cpu;
79 uint64_t ret = 0;
81 if (addr & 4) {
82 return s->latch_tmp;
85 switch (addr) {
86 case 0x0000:
87 /* CSC: Cchip System Configuration Register. */
88 /* All sorts of data here; probably the only thing relevant is
89 PIP<14> Pchip 1 Present = 0. */
90 break;
92 case 0x0040:
93 /* MTR: Memory Timing Register. */
94 /* All sorts of stuff related to real DRAM. */
95 break;
97 case 0x0080:
98 /* MISC: Miscellaneous Register. */
99 cpu = ENV_GET_CPU(env);
100 ret = s->cchip.misc | (cpu->cpu_index & 3);
101 break;
103 case 0x00c0:
104 /* MPD: Memory Presence Detect Register. */
105 break;
107 case 0x0100: /* AAR0 */
108 case 0x0140: /* AAR1 */
109 case 0x0180: /* AAR2 */
110 case 0x01c0: /* AAR3 */
111 /* AAR: Array Address Register. */
112 /* All sorts of information about DRAM. */
113 break;
115 case 0x0200:
116 /* DIM0: Device Interrupt Mask Register, CPU0. */
117 ret = s->cchip.dim[0];
118 break;
119 case 0x0240:
120 /* DIM1: Device Interrupt Mask Register, CPU1. */
121 ret = s->cchip.dim[1];
122 break;
123 case 0x0280:
124 /* DIR0: Device Interrupt Request Register, CPU0. */
125 ret = s->cchip.dim[0] & s->cchip.drir;
126 break;
127 case 0x02c0:
128 /* DIR1: Device Interrupt Request Register, CPU1. */
129 ret = s->cchip.dim[1] & s->cchip.drir;
130 break;
131 case 0x0300:
132 /* DRIR: Device Raw Interrupt Request Register. */
133 ret = s->cchip.drir;
134 break;
136 case 0x0340:
137 /* PRBEN: Probe Enable Register. */
138 break;
140 case 0x0380:
141 /* IIC0: Interval Ignore Count Register, CPU0. */
142 ret = s->cchip.iic[0];
143 break;
144 case 0x03c0:
145 /* IIC1: Interval Ignore Count Register, CPU1. */
146 ret = s->cchip.iic[1];
147 break;
149 case 0x0400: /* MPR0 */
150 case 0x0440: /* MPR1 */
151 case 0x0480: /* MPR2 */
152 case 0x04c0: /* MPR3 */
153 /* MPR: Memory Programming Register. */
154 break;
156 case 0x0580:
157 /* TTR: TIGbus Timing Register. */
158 /* All sorts of stuff related to interrupt delivery timings. */
159 break;
160 case 0x05c0:
161 /* TDR: TIGbug Device Timing Register. */
162 break;
164 case 0x0600:
165 /* DIM2: Device Interrupt Mask Register, CPU2. */
166 ret = s->cchip.dim[2];
167 break;
168 case 0x0640:
169 /* DIM3: Device Interrupt Mask Register, CPU3. */
170 ret = s->cchip.dim[3];
171 break;
172 case 0x0680:
173 /* DIR2: Device Interrupt Request Register, CPU2. */
174 ret = s->cchip.dim[2] & s->cchip.drir;
175 break;
176 case 0x06c0:
177 /* DIR3: Device Interrupt Request Register, CPU3. */
178 ret = s->cchip.dim[3] & s->cchip.drir;
179 break;
181 case 0x0700:
182 /* IIC2: Interval Ignore Count Register, CPU2. */
183 ret = s->cchip.iic[2];
184 break;
185 case 0x0740:
186 /* IIC3: Interval Ignore Count Register, CPU3. */
187 ret = s->cchip.iic[3];
188 break;
190 case 0x0780:
191 /* PWR: Power Management Control. */
192 break;
194 case 0x0c00: /* CMONCTLA */
195 case 0x0c40: /* CMONCTLB */
196 case 0x0c80: /* CMONCNT01 */
197 case 0x0cc0: /* CMONCNT23 */
198 break;
200 default:
201 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
202 return -1;
205 s->latch_tmp = ret >> 32;
206 return ret;
209 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
211 /* Skip this. It's all related to DRAM timing and setup. */
212 return 0;
215 static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
217 TyphoonState *s = opaque;
218 uint64_t ret = 0;
220 if (addr & 4) {
221 return s->latch_tmp;
224 switch (addr) {
225 case 0x0000:
226 /* WSBA0: Window Space Base Address Register. */
227 ret = s->pchip.win[0].base_addr;
228 break;
229 case 0x0040:
230 /* WSBA1 */
231 ret = s->pchip.win[1].base_addr;
232 break;
233 case 0x0080:
234 /* WSBA2 */
235 ret = s->pchip.win[2].base_addr;
236 break;
237 case 0x00c0:
238 /* WSBA3 */
239 ret = s->pchip.win[3].base_addr;
240 break;
242 case 0x0100:
243 /* WSM0: Window Space Mask Register. */
244 ret = s->pchip.win[0].mask;
245 break;
246 case 0x0140:
247 /* WSM1 */
248 ret = s->pchip.win[1].mask;
249 break;
250 case 0x0180:
251 /* WSM2 */
252 ret = s->pchip.win[2].mask;
253 break;
254 case 0x01c0:
255 /* WSM3 */
256 ret = s->pchip.win[3].mask;
257 break;
259 case 0x0200:
260 /* TBA0: Translated Base Address Register. */
261 ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10;
262 break;
263 case 0x0240:
264 /* TBA1 */
265 ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10;
266 break;
267 case 0x0280:
268 /* TBA2 */
269 ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10;
270 break;
271 case 0x02c0:
272 /* TBA3 */
273 ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10;
274 break;
276 case 0x0300:
277 /* PCTL: Pchip Control Register. */
278 ret = s->pchip.ctl;
279 break;
280 case 0x0340:
281 /* PLAT: Pchip Master Latency Register. */
282 break;
283 case 0x03c0:
284 /* PERROR: Pchip Error Register. */
285 break;
286 case 0x0400:
287 /* PERRMASK: Pchip Error Mask Register. */
288 break;
289 case 0x0440:
290 /* PERRSET: Pchip Error Set Register. */
291 break;
292 case 0x0480:
293 /* TLBIV: Translation Buffer Invalidate Virtual Register (WO). */
294 break;
295 case 0x04c0:
296 /* TLBIA: Translation Buffer Invalidate All Register (WO). */
297 break;
298 case 0x0500: /* PMONCTL */
299 case 0x0540: /* PMONCNT */
300 case 0x0800: /* SPRST */
301 break;
303 default:
304 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
305 return -1;
308 s->latch_tmp = ret >> 32;
309 return ret;
312 static void cchip_write(void *opaque, hwaddr addr,
313 uint64_t v32, unsigned size)
315 TyphoonState *s = opaque;
316 uint64_t val, oldval, newval;
318 if (addr & 4) {
319 val = v32 << 32 | s->latch_tmp;
320 addr ^= 4;
321 } else {
322 s->latch_tmp = v32;
323 return;
326 switch (addr) {
327 case 0x0000:
328 /* CSC: Cchip System Configuration Register. */
329 /* All sorts of data here; nothing relevant RW. */
330 break;
332 case 0x0040:
333 /* MTR: Memory Timing Register. */
334 /* All sorts of stuff related to real DRAM. */
335 break;
337 case 0x0080:
338 /* MISC: Miscellaneous Register. */
339 newval = oldval = s->cchip.misc;
340 newval &= ~(val & 0x10000ff0); /* W1C fields */
341 if (val & 0x100000) {
342 newval &= ~0xff0000ull; /* ACL clears ABT and ABW */
343 } else {
344 newval |= val & 0x00f00000; /* ABT field is W1S */
345 if ((newval & 0xf0000) == 0) {
346 newval |= val & 0xf0000; /* ABW field is W1S iff zero */
349 newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */
351 newval &= ~0xf0000000000ull; /* WO and RW fields */
352 newval |= val & 0xf0000000000ull;
353 s->cchip.misc = newval;
355 /* Pass on changes to IPI and ITI state. */
356 if ((newval ^ oldval) & 0xff0) {
357 int i;
358 for (i = 0; i < 4; ++i) {
359 AlphaCPU *cpu = s->cchip.cpu[i];
360 if (cpu != NULL) {
361 CPUAlphaState *env = &cpu->env;
362 /* IPI can be either cleared or set by the write. */
363 if (newval & (1 << (i + 8))) {
364 cpu_interrupt(env, CPU_INTERRUPT_SMP);
365 } else {
366 cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);
369 /* ITI can only be cleared by the write. */
370 if ((newval & (1 << (i + 4))) == 0) {
371 cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);
376 break;
378 case 0x00c0:
379 /* MPD: Memory Presence Detect Register. */
380 break;
382 case 0x0100: /* AAR0 */
383 case 0x0140: /* AAR1 */
384 case 0x0180: /* AAR2 */
385 case 0x01c0: /* AAR3 */
386 /* AAR: Array Address Register. */
387 /* All sorts of information about DRAM. */
388 break;
390 case 0x0200: /* DIM0 */
391 /* DIM: Device Interrupt Mask Register, CPU0. */
392 s->cchip.dim[0] = val;
393 cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir);
394 break;
395 case 0x0240: /* DIM1 */
396 /* DIM: Device Interrupt Mask Register, CPU1. */
397 s->cchip.dim[0] = val;
398 cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
399 break;
401 case 0x0280: /* DIR0 (RO) */
402 case 0x02c0: /* DIR1 (RO) */
403 case 0x0300: /* DRIR (RO) */
404 break;
406 case 0x0340:
407 /* PRBEN: Probe Enable Register. */
408 break;
410 case 0x0380: /* IIC0 */
411 s->cchip.iic[0] = val & 0xffffff;
412 break;
413 case 0x03c0: /* IIC1 */
414 s->cchip.iic[1] = val & 0xffffff;
415 break;
417 case 0x0400: /* MPR0 */
418 case 0x0440: /* MPR1 */
419 case 0x0480: /* MPR2 */
420 case 0x04c0: /* MPR3 */
421 /* MPR: Memory Programming Register. */
422 break;
424 case 0x0580:
425 /* TTR: TIGbus Timing Register. */
426 /* All sorts of stuff related to interrupt delivery timings. */
427 break;
428 case 0x05c0:
429 /* TDR: TIGbug Device Timing Register. */
430 break;
432 case 0x0600:
433 /* DIM2: Device Interrupt Mask Register, CPU2. */
434 s->cchip.dim[2] = val;
435 cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir);
436 break;
437 case 0x0640:
438 /* DIM3: Device Interrupt Mask Register, CPU3. */
439 s->cchip.dim[3] = val;
440 cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir);
441 break;
443 case 0x0680: /* DIR2 (RO) */
444 case 0x06c0: /* DIR3 (RO) */
445 break;
447 case 0x0700: /* IIC2 */
448 s->cchip.iic[2] = val & 0xffffff;
449 break;
450 case 0x0740: /* IIC3 */
451 s->cchip.iic[3] = val & 0xffffff;
452 break;
454 case 0x0780:
455 /* PWR: Power Management Control. */
456 break;
458 case 0x0c00: /* CMONCTLA */
459 case 0x0c40: /* CMONCTLB */
460 case 0x0c80: /* CMONCNT01 */
461 case 0x0cc0: /* CMONCNT23 */
462 break;
464 default:
465 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
466 return;
470 static void dchip_write(void *opaque, hwaddr addr,
471 uint64_t val, unsigned size)
473 /* Skip this. It's all related to DRAM timing and setup. */
476 static void pchip_write(void *opaque, hwaddr addr,
477 uint64_t v32, unsigned size)
479 TyphoonState *s = opaque;
480 uint64_t val, oldval;
482 if (addr & 4) {
483 val = v32 << 32 | s->latch_tmp;
484 addr ^= 4;
485 } else {
486 s->latch_tmp = v32;
487 return;
490 switch (addr) {
491 case 0x0000:
492 /* WSBA0: Window Space Base Address Register. */
493 s->pchip.win[0].base_addr = val;
494 break;
495 case 0x0040:
496 /* WSBA1 */
497 s->pchip.win[1].base_addr = val;
498 break;
499 case 0x0080:
500 /* WSBA2 */
501 s->pchip.win[2].base_addr = val;
502 break;
503 case 0x00c0:
504 /* WSBA3 */
505 s->pchip.win[3].base_addr = val;
506 break;
508 case 0x0100:
509 /* WSM0: Window Space Mask Register. */
510 s->pchip.win[0].mask = val;
511 break;
512 case 0x0140:
513 /* WSM1 */
514 s->pchip.win[1].mask = val;
515 break;
516 case 0x0180:
517 /* WSM2 */
518 s->pchip.win[2].mask = val;
519 break;
520 case 0x01c0:
521 /* WSM3 */
522 s->pchip.win[3].mask = val;
523 break;
525 case 0x0200:
526 /* TBA0: Translated Base Address Register. */
527 s->pchip.win[0].translated_base_pfn = val >> 10;
528 break;
529 case 0x0240:
530 /* TBA1 */
531 s->pchip.win[1].translated_base_pfn = val >> 10;
532 break;
533 case 0x0280:
534 /* TBA2 */
535 s->pchip.win[2].translated_base_pfn = val >> 10;
536 break;
537 case 0x02c0:
538 /* TBA3 */
539 s->pchip.win[3].translated_base_pfn = val >> 10;
540 break;
542 case 0x0300:
543 /* PCTL: Pchip Control Register. */
544 oldval = s->pchip.ctl;
545 oldval &= ~0x00001cff0fc7ffull; /* RW fields */
546 oldval |= val & 0x00001cff0fc7ffull;
548 s->pchip.ctl = oldval;
549 break;
551 case 0x0340:
552 /* PLAT: Pchip Master Latency Register. */
553 break;
554 case 0x03c0:
555 /* PERROR: Pchip Error Register. */
556 break;
557 case 0x0400:
558 /* PERRMASK: Pchip Error Mask Register. */
559 break;
560 case 0x0440:
561 /* PERRSET: Pchip Error Set Register. */
562 break;
564 case 0x0480:
565 /* TLBIV: Translation Buffer Invalidate Virtual Register. */
566 break;
568 case 0x04c0:
569 /* TLBIA: Translation Buffer Invalidate All Register (WO). */
570 break;
572 case 0x0500:
573 /* PMONCTL */
574 case 0x0540:
575 /* PMONCNT */
576 case 0x0800:
577 /* SPRST */
578 break;
580 default:
581 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
582 return;
586 static const MemoryRegionOps cchip_ops = {
587 .read = cchip_read,
588 .write = cchip_write,
589 .endianness = DEVICE_LITTLE_ENDIAN,
590 .valid = {
591 .min_access_size = 4, /* ??? Should be 8. */
592 .max_access_size = 8,
594 .impl = {
595 .min_access_size = 4,
596 .max_access_size = 4,
600 static const MemoryRegionOps dchip_ops = {
601 .read = dchip_read,
602 .write = dchip_write,
603 .endianness = DEVICE_LITTLE_ENDIAN,
604 .valid = {
605 .min_access_size = 4, /* ??? Should be 8. */
606 .max_access_size = 8,
608 .impl = {
609 .min_access_size = 4,
610 .max_access_size = 8,
614 static const MemoryRegionOps pchip_ops = {
615 .read = pchip_read,
616 .write = pchip_write,
617 .endianness = DEVICE_LITTLE_ENDIAN,
618 .valid = {
619 .min_access_size = 4, /* ??? Should be 8. */
620 .max_access_size = 8,
622 .impl = {
623 .min_access_size = 4,
624 .max_access_size = 4,
628 static void typhoon_set_irq(void *opaque, int irq, int level)
630 TyphoonState *s = opaque;
631 uint64_t drir;
632 int i;
634 /* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL. */
635 drir = s->cchip.drir;
636 if (level) {
637 drir |= 1ull << irq;
638 } else {
639 drir &= ~(1ull << irq);
641 s->cchip.drir = drir;
643 for (i = 0; i < 4; ++i) {
644 cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir);
648 static void typhoon_set_isa_irq(void *opaque, int irq, int level)
650 typhoon_set_irq(opaque, 55, level);
653 static void typhoon_set_timer_irq(void *opaque, int irq, int level)
655 TyphoonState *s = opaque;
656 int i;
658 /* Thankfully, the mc146818rtc code doesn't track the IRQ state,
659 and so we don't have to worry about missing interrupts just
660 because we never actually ACK the interrupt. Just ignore any
661 case of the interrupt level going low. */
662 if (level == 0) {
663 return;
666 /* Deliver the interrupt to each CPU, considering each CPU's IIC. */
667 for (i = 0; i < 4; ++i) {
668 AlphaCPU *cpu = s->cchip.cpu[i];
669 if (cpu != NULL) {
670 uint32_t iic = s->cchip.iic[i];
672 /* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
673 Bit 24 is the OverFlow bit, RO, and set when the count
674 decrements past 0. When is OF cleared? My guess is that
675 OF is actually cleared when the IIC is written, and that
676 the ICNT field always decrements. At least, that's an
677 interpretation that makes sense, and "allows the CPU to
678 determine exactly how mant interval timer ticks were
679 skipped". At least within the next 4M ticks... */
681 iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000);
682 s->cchip.iic[i] = iic;
684 if (iic & 0x1000000) {
685 /* Set the ITI bit for this cpu. */
686 s->cchip.misc |= 1 << (i + 4);
687 /* And signal the interrupt. */
688 cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);
694 static void typhoon_alarm_timer(void *opaque)
696 TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3);
697 int cpu = (uintptr_t)opaque & 3;
699 /* Set the ITI bit for this cpu. */
700 s->cchip.misc |= 1 << (cpu + 4);
701 cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);
704 PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
705 qemu_irq *p_rtc_irq,
706 AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
708 const uint64_t MB = 1024 * 1024;
709 const uint64_t GB = 1024 * MB;
710 MemoryRegion *addr_space = get_system_memory();
711 MemoryRegion *addr_space_io = get_system_io();
712 DeviceState *dev;
713 TyphoonState *s;
714 PCIHostState *phb;
715 PCIBus *b;
716 int i;
718 dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
719 qdev_init_nofail(dev);
721 s = TYPHOON_PCI_HOST_BRIDGE(dev);
722 phb = PCI_HOST_BRIDGE(dev);
724 /* Remember the CPUs so that we can deliver interrupts to them. */
725 for (i = 0; i < 4; i++) {
726 AlphaCPU *cpu = cpus[i];
727 s->cchip.cpu[i] = cpu;
728 if (cpu != NULL) {
729 cpu->alarm_timer = qemu_new_timer_ns(rtc_clock,
730 typhoon_alarm_timer,
731 (void *)((uintptr_t)s + i));
735 *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
737 /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
738 but the address space hole reserved at this point is 8TB. */
739 memory_region_init_ram(&s->ram_region, "ram", ram_size);
740 vmstate_register_ram_global(&s->ram_region);
741 memory_region_add_subregion(addr_space, 0, &s->ram_region);
743 /* TIGbus, 0x801.0000.0000, 1GB. */
744 /* ??? The TIGbus is used for delivering interrupts, and access to
745 the flash ROM. I'm not sure that we need to implement it at all. */
747 /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
748 memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);
749 memory_region_add_subregion(addr_space, 0x80180000000ULL,
750 &s->pchip.region);
752 /* Cchip CSRs, 0x801.A000.0000, 256MB. */
753 memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);
754 memory_region_add_subregion(addr_space, 0x801a0000000ULL,
755 &s->cchip.region);
757 /* Dchip CSRs, 0x801.B000.0000, 256MB. */
758 memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);
759 memory_region_add_subregion(addr_space, 0x801b0000000ULL,
760 &s->dchip_region);
762 /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
763 memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);
764 memory_region_add_subregion(addr_space, 0x80000000000ULL,
765 &s->pchip.reg_mem);
767 /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
768 /* ??? Ideally we drop the "system" i/o space on the floor and give the
769 PCI subsystem the full address space reserved by the chipset.
770 We can't do that until the MEM and IO paths in memory.c are unified. */
771 memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,
772 "pci0-io", 32*MB);
773 memory_region_add_subregion(addr_space, 0x801fc000000ULL,
774 &s->pchip.reg_io);
776 b = pci_register_bus(dev, "pci",
777 typhoon_set_irq, sys_map_irq, s,
778 &s->pchip.reg_mem, addr_space_io, 0, 64);
779 phb->bus = b;
781 /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
782 memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
783 "pci0-iack", 64*MB);
784 memory_region_add_subregion(addr_space, 0x801f8000000ULL,
785 &s->pchip.reg_iack);
787 /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
788 memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,
789 "pci0-conf", 16*MB);
790 memory_region_add_subregion(addr_space, 0x801fe000000ULL,
791 &s->pchip.reg_conf);
793 /* For the record, these are the mappings for the second PCI bus.
794 We can get away with not implementing them because we indicate
795 via the Cchip.CSC<PIP> bit that Pchip1 is not present. */
796 /* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */
797 /* Pchip1 CSRs, 0x802.8000.0000, 256MB. */
798 /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */
799 /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */
800 /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */
802 /* Init the ISA bus. */
803 /* ??? Technically there should be a cy82c693ub pci-isa bridge. */
805 qemu_irq isa_pci_irq, *isa_irqs;
807 *isa_bus = isa_bus_new(NULL, addr_space_io);
808 isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
809 isa_irqs = i8259_init(*isa_bus, isa_pci_irq);
810 isa_bus_irqs(*isa_bus, isa_irqs);
813 return b;
816 static int typhoon_pcihost_init(SysBusDevice *dev)
818 return 0;
821 static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
823 DeviceClass *dc = DEVICE_CLASS(klass);
824 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
826 k->init = typhoon_pcihost_init;
827 dc->no_user = 1;
830 static const TypeInfo typhoon_pcihost_info = {
831 .name = TYPE_TYPHOON_PCI_HOST_BRIDGE,
832 .parent = TYPE_PCI_HOST_BRIDGE,
833 .instance_size = sizeof(TyphoonState),
834 .class_init = typhoon_pcihost_class_init,
837 static void typhoon_register_types(void)
839 type_register_static(&typhoon_pcihost_info);
842 type_init(typhoon_register_types)