target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUArchState struct CPUX86State
  46
  47 #include "exec/cpu-defs.h"
  48
  49 #include "fpu/softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK
 127    bit positions to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_AC_SHIFT         18 /* must be same as eflags */
 151 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 152 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 153 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 154 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 155 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
 156
 157 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 158 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 159 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 160 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 161 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 162 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 163 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 164 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 165 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 166 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 167 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 168 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 169 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 170 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 171 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 172 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 173 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
 174 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 175 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 176 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 177 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 178 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
 179
 180 /* hflags2 */
 181
 182 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 183 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 184 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 185 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 186
 187 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 188 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 189 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 190 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 191
 192 #define CR0_PE_SHIFT 0
 193 #define CR0_MP_SHIFT 1
 194
 195 #define CR0_PE_MASK  (1 << 0)
 196 #define CR0_MP_MASK  (1 << 1)
 197 #define CR0_EM_MASK  (1 << 2)
 198 #define CR0_TS_MASK  (1 << 3)
 199 #define CR0_ET_MASK  (1 << 4)
 200 #define CR0_NE_MASK  (1 << 5)
 201 #define CR0_WP_MASK  (1 << 16)
 202 #define CR0_AM_MASK  (1 << 18)
 203 #define CR0_PG_MASK  (1 << 31)
 204
 205 #define CR4_VME_MASK  (1 << 0)
 206 #define CR4_PVI_MASK  (1 << 1)
 207 #define CR4_TSD_MASK  (1 << 2)
 208 #define CR4_DE_MASK   (1 << 3)
 209 #define CR4_PSE_MASK  (1 << 4)
 210 #define CR4_PAE_MASK  (1 << 5)
 211 #define CR4_MCE_MASK  (1 << 6)
 212 #define CR4_PGE_MASK  (1 << 7)
 213 #define CR4_PCE_MASK  (1 << 8)
 214 #define CR4_OSFXSR_SHIFT 9
 215 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 216 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 217 #define CR4_VMXE_MASK   (1 << 13)
 218 #define CR4_SMXE_MASK   (1 << 14)
 219 #define CR4_FSGSBASE_MASK (1 << 16)
 220 #define CR4_PCIDE_MASK  (1 << 17)
 221 #define CR4_OSXSAVE_MASK (1 << 18)
 222 #define CR4_SMEP_MASK   (1 << 20)
 223 #define CR4_SMAP_MASK   (1 << 21)
 224
 225 #define DR6_BD          (1 << 13)
 226 #define DR6_BS          (1 << 14)
 227 #define DR6_BT          (1 << 15)
 228 #define DR6_FIXED_1     0xffff0ff0
 229
 230 #define DR7_GD          (1 << 13)
 231 #define DR7_TYPE_SHIFT  16
 232 #define DR7_LEN_SHIFT   18
 233 #define DR7_FIXED_1     0x00000400
 234 #define DR7_LOCAL_BP_MASK    0x55
 235 #define DR7_MAX_BP           4
 236 #define DR7_TYPE_BP_INST     0x0
 237 #define DR7_TYPE_DATA_WR     0x1
 238 #define DR7_TYPE_IO_RW       0x2
 239 #define DR7_TYPE_DATA_RW     0x3
 240
 241 #define PG_PRESENT_BIT  0
 242 #define PG_RW_BIT       1
 243 #define PG_USER_BIT     2
 244 #define PG_PWT_BIT      3
 245 #define PG_PCD_BIT      4
 246 #define PG_ACCESSED_BIT 5
 247 #define PG_DIRTY_BIT    6
 248 #define PG_PSE_BIT      7
 249 #define PG_GLOBAL_BIT   8
 250 #define PG_NX_BIT       63
 251
 252 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 253 #define PG_RW_MASK       (1 << PG_RW_BIT)
 254 #define PG_USER_MASK     (1 << PG_USER_BIT)
 255 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 256 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 257 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 258 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 259 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 260 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 261 #define PG_HI_USER_MASK  0x7ff0000000000000LL
 262 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 263
 264 #define PG_ERROR_W_BIT     1
 265
 266 #define PG_ERROR_P_MASK    0x01
 267 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 268 #define PG_ERROR_U_MASK    0x04
 269 #define PG_ERROR_RSVD_MASK 0x08
 270 #define PG_ERROR_I_D_MASK  0x10
 271
 272 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 273 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 274
 275 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 276 #define MCE_BANKS_DEF   10
 277
 278 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 279 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 280 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 281
 282 #define MCI_STATUS_VAL  (1ULL<<63)  /* valid error */
 283 #define MCI_STATUS_OVER (1ULL<<62)  /* previous errors lost */
 284 #define MCI_STATUS_UC   (1ULL<<61)  /* uncorrected error */
 285 #define MCI_STATUS_EN   (1ULL<<60)  /* error enabled */
 286 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
 287 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
 288 #define MCI_STATUS_PCC  (1ULL<<57)  /* processor context corrupt */
 289 #define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
 290 #define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
 291
 292 /* MISC register defines */
 293 #define MCM_ADDR_SEGOFF 0       /* segment offset */
 294 #define MCM_ADDR_LINEAR 1       /* linear address */
 295 #define MCM_ADDR_PHYS   2       /* physical address */
 296 #define MCM_ADDR_MEM    3       /* memory address */
 297 #define MCM_ADDR_GENERIC 7      /* generic */
 298
 299 #define MSR_IA32_TSC                    0x10
 300 #define MSR_IA32_APICBASE               0x1b
 301 #define MSR_IA32_APICBASE_BSP           (1<<8)
 302 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 303 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 304 #define MSR_TSC_ADJUST                  0x0000003b
 305 #define MSR_IA32_TSCDEADLINE            0x6e0
 306
 307 #define MSR_MTRRcap                     0xfe
 308 #define MSR_MTRRcap_VCNT                8
 309 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 310 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 311
 312 #define MSR_IA32_SYSENTER_CS            0x174
 313 #define MSR_IA32_SYSENTER_ESP           0x175
 314 #define MSR_IA32_SYSENTER_EIP           0x176
 315
 316 #define MSR_MCG_CAP                     0x179
 317 #define MSR_MCG_STATUS                  0x17a
 318 #define MSR_MCG_CTL                     0x17b
 319
 320 #define MSR_IA32_PERF_STATUS            0x198
 321
 322 #define MSR_IA32_MISC_ENABLE            0x1a0
 323 /* Indicates good rep/movs microcode on some processors: */
 324 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
 325
 326 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 327 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 328
 329 #define MSR_MTRRfix64K_00000            0x250
 330 #define MSR_MTRRfix16K_80000            0x258
 331 #define MSR_MTRRfix16K_A0000            0x259
 332 #define MSR_MTRRfix4K_C0000             0x268
 333 #define MSR_MTRRfix4K_C8000             0x269
 334 #define MSR_MTRRfix4K_D0000             0x26a
 335 #define MSR_MTRRfix4K_D8000             0x26b
 336 #define MSR_MTRRfix4K_E0000             0x26c
 337 #define MSR_MTRRfix4K_E8000             0x26d
 338 #define MSR_MTRRfix4K_F0000             0x26e
 339 #define MSR_MTRRfix4K_F8000             0x26f
 340
 341 #define MSR_PAT                         0x277
 342
 343 #define MSR_MTRRdefType                 0x2ff
 344
 345 #define MSR_MC0_CTL                     0x400
 346 #define MSR_MC0_STATUS                  0x401
 347 #define MSR_MC0_ADDR                    0x402
 348 #define MSR_MC0_MISC                    0x403
 349
 350 #define MSR_EFER                        0xc0000080
 351
 352 #define MSR_EFER_SCE   (1 << 0)
 353 #define MSR_EFER_LME   (1 << 8)
 354 #define MSR_EFER_LMA   (1 << 10)
 355 #define MSR_EFER_NXE   (1 << 11)
 356 #define MSR_EFER_SVME  (1 << 12)
 357 #define MSR_EFER_FFXSR (1 << 14)
 358
 359 #define MSR_STAR                        0xc0000081
 360 #define MSR_LSTAR                       0xc0000082
 361 #define MSR_CSTAR                       0xc0000083
 362 #define MSR_FMASK                       0xc0000084
 363 #define MSR_FSBASE                      0xc0000100
 364 #define MSR_GSBASE                      0xc0000101
 365 #define MSR_KERNELGSBASE                0xc0000102
 366 #define MSR_TSC_AUX                     0xc0000103
 367
 368 #define MSR_VM_HSAVE_PA                 0xc0010117
 369
 370 /* CPUID feature words */
 371 typedef enum FeatureWord {
 372     FEAT_1_EDX,         /* CPUID[1].EDX */
 373     FEAT_1_ECX,         /* CPUID[1].ECX */
 374     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
 375     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
 376     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
 377     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
 378     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
 379     FEAT_SVM,           /* CPUID[8000_000A].EDX */
 380     FEATURE_WORDS,
 381 } FeatureWord;
 382
 383 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 384
 385 /* cpuid_features bits */
 386 #define CPUID_FP87 (1 << 0)
 387 #define CPUID_VME  (1 << 1)
 388 #define CPUID_DE   (1 << 2)
 389 #define CPUID_PSE  (1 << 3)
 390 #define CPUID_TSC  (1 << 4)
 391 #define CPUID_MSR  (1 << 5)
 392 #define CPUID_PAE  (1 << 6)
 393 #define CPUID_MCE  (1 << 7)
 394 #define CPUID_CX8  (1 << 8)
 395 #define CPUID_APIC (1 << 9)
 396 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 397 #define CPUID_MTRR (1 << 12)
 398 #define CPUID_PGE  (1 << 13)
 399 #define CPUID_MCA  (1 << 14)
 400 #define CPUID_CMOV (1 << 15)
 401 #define CPUID_PAT  (1 << 16)
 402 #define CPUID_PSE36   (1 << 17)
 403 #define CPUID_PN   (1 << 18)
 404 #define CPUID_CLFLUSH (1 << 19)
 405 #define CPUID_DTS (1 << 21)
 406 #define CPUID_ACPI (1 << 22)
 407 #define CPUID_MMX  (1 << 23)
 408 #define CPUID_FXSR (1 << 24)
 409 #define CPUID_SSE  (1 << 25)
 410 #define CPUID_SSE2 (1 << 26)
 411 #define CPUID_SS (1 << 27)
 412 #define CPUID_HT (1 << 28)
 413 #define CPUID_TM (1 << 29)
 414 #define CPUID_IA64 (1 << 30)
 415 #define CPUID_PBE (1 << 31)
 416
 417 #define CPUID_EXT_SSE3     (1 << 0)
 418 #define CPUID_EXT_PCLMULQDQ (1 << 1)
 419 #define CPUID_EXT_DTES64   (1 << 2)
 420 #define CPUID_EXT_MONITOR  (1 << 3)
 421 #define CPUID_EXT_DSCPL    (1 << 4)
 422 #define CPUID_EXT_VMX      (1 << 5)
 423 #define CPUID_EXT_SMX      (1 << 6)
 424 #define CPUID_EXT_EST      (1 << 7)
 425 #define CPUID_EXT_TM2      (1 << 8)
 426 #define CPUID_EXT_SSSE3    (1 << 9)
 427 #define CPUID_EXT_CID      (1 << 10)
 428 #define CPUID_EXT_FMA      (1 << 12)
 429 #define CPUID_EXT_CX16     (1 << 13)
 430 #define CPUID_EXT_XTPR     (1 << 14)
 431 #define CPUID_EXT_PDCM     (1 << 15)
 432 #define CPUID_EXT_PCID     (1 << 17)
 433 #define CPUID_EXT_DCA      (1 << 18)
 434 #define CPUID_EXT_SSE41    (1 << 19)
 435 #define CPUID_EXT_SSE42    (1 << 20)
 436 #define CPUID_EXT_X2APIC   (1 << 21)
 437 #define CPUID_EXT_MOVBE    (1 << 22)
 438 #define CPUID_EXT_POPCNT   (1 << 23)
 439 #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
 440 #define CPUID_EXT_AES      (1 << 25)
 441 #define CPUID_EXT_XSAVE    (1 << 26)
 442 #define CPUID_EXT_OSXSAVE  (1 << 27)
 443 #define CPUID_EXT_AVX      (1 << 28)
 444 #define CPUID_EXT_F16C     (1 << 29)
 445 #define CPUID_EXT_RDRAND   (1 << 30)
 446 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 447
 448 #define CPUID_EXT2_FPU     (1 << 0)
 449 #define CPUID_EXT2_VME     (1 << 1)
 450 #define CPUID_EXT2_DE      (1 << 2)
 451 #define CPUID_EXT2_PSE     (1 << 3)
 452 #define CPUID_EXT2_TSC     (1 << 4)
 453 #define CPUID_EXT2_MSR     (1 << 5)
 454 #define CPUID_EXT2_PAE     (1 << 6)
 455 #define CPUID_EXT2_MCE     (1 << 7)
 456 #define CPUID_EXT2_CX8     (1 << 8)
 457 #define CPUID_EXT2_APIC    (1 << 9)
 458 #define CPUID_EXT2_SYSCALL (1 << 11)
 459 #define CPUID_EXT2_MTRR    (1 << 12)
 460 #define CPUID_EXT2_PGE     (1 << 13)
 461 #define CPUID_EXT2_MCA     (1 << 14)
 462 #define CPUID_EXT2_CMOV    (1 << 15)
 463 #define CPUID_EXT2_PAT     (1 << 16)
 464 #define CPUID_EXT2_PSE36   (1 << 17)
 465 #define CPUID_EXT2_MP      (1 << 19)
 466 #define CPUID_EXT2_NX      (1 << 20)
 467 #define CPUID_EXT2_MMXEXT  (1 << 22)
 468 #define CPUID_EXT2_MMX     (1 << 23)
 469 #define CPUID_EXT2_FXSR    (1 << 24)
 470 #define CPUID_EXT2_FFXSR   (1 << 25)
 471 #define CPUID_EXT2_PDPE1GB (1 << 26)
 472 #define CPUID_EXT2_RDTSCP  (1 << 27)
 473 #define CPUID_EXT2_LM      (1 << 29)
 474 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 475 #define CPUID_EXT2_3DNOW   (1 << 31)
 476
 477 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
 478 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
 479                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
 480                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
 481                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
 482                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
 483                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
 484                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
 485                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
 486                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
 487
 488 #define CPUID_EXT3_LAHF_LM (1 << 0)
 489 #define CPUID_EXT3_CMP_LEG (1 << 1)
 490 #define CPUID_EXT3_SVM     (1 << 2)
 491 #define CPUID_EXT3_EXTAPIC (1 << 3)
 492 #define CPUID_EXT3_CR8LEG  (1 << 4)
 493 #define CPUID_EXT3_ABM     (1 << 5)
 494 #define CPUID_EXT3_SSE4A   (1 << 6)
 495 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 496 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 497 #define CPUID_EXT3_OSVW    (1 << 9)
 498 #define CPUID_EXT3_IBS     (1 << 10)
 499 #define CPUID_EXT3_XOP     (1 << 11)
 500 #define CPUID_EXT3_SKINIT  (1 << 12)
 501 #define CPUID_EXT3_WDT     (1 << 13)
 502 #define CPUID_EXT3_LWP     (1 << 15)
 503 #define CPUID_EXT3_FMA4    (1 << 16)
 504 #define CPUID_EXT3_TCE     (1 << 17)
 505 #define CPUID_EXT3_NODEID  (1 << 19)
 506 #define CPUID_EXT3_TBM     (1 << 21)
 507 #define CPUID_EXT3_TOPOEXT (1 << 22)
 508 #define CPUID_EXT3_PERFCORE (1 << 23)
 509 #define CPUID_EXT3_PERFNB  (1 << 24)
 510
 511 #define CPUID_SVM_NPT          (1 << 0)
 512 #define CPUID_SVM_LBRV         (1 << 1)
 513 #define CPUID_SVM_SVMLOCK      (1 << 2)
 514 #define CPUID_SVM_NRIPSAVE     (1 << 3)
 515 #define CPUID_SVM_TSCSCALE     (1 << 4)
 516 #define CPUID_SVM_VMCBCLEAN    (1 << 5)
 517 #define CPUID_SVM_FLUSHASID    (1 << 6)
 518 #define CPUID_SVM_DECODEASSIST (1 << 7)
 519 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 520 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 521
 522 #define CPUID_7_0_EBX_FSGSBASE (1 << 0)
 523 #define CPUID_7_0_EBX_BMI1     (1 << 3)
 524 #define CPUID_7_0_EBX_HLE      (1 << 4)
 525 #define CPUID_7_0_EBX_AVX2     (1 << 5)
 526 #define CPUID_7_0_EBX_SMEP     (1 << 7)
 527 #define CPUID_7_0_EBX_BMI2     (1 << 8)
 528 #define CPUID_7_0_EBX_ERMS     (1 << 9)
 529 #define CPUID_7_0_EBX_INVPCID  (1 << 10)
 530 #define CPUID_7_0_EBX_RTM      (1 << 11)
 531 #define CPUID_7_0_EBX_RDSEED   (1 << 18)
 532 #define CPUID_7_0_EBX_ADX      (1 << 19)
 533 #define CPUID_7_0_EBX_SMAP     (1 << 20)
 534
 535 #define CPUID_VENDOR_SZ      12
 536
 537 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 538 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 539 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 540 #define CPUID_VENDOR_INTEL "GenuineIntel"
 541
 542 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 543 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 544 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 545 #define CPUID_VENDOR_AMD   "AuthenticAMD"
 546
 547 #define CPUID_VENDOR_VIA   "CentaurHauls"
 548
 549 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 550 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 551
 552 #define EXCP00_DIVZ     0
 553 #define EXCP01_DB       1
 554 #define EXCP02_NMI      2
 555 #define EXCP03_INT3     3
 556 #define EXCP04_INTO     4
 557 #define EXCP05_BOUND    5
 558 #define EXCP06_ILLOP    6
 559 #define EXCP07_PREX     7
 560 #define EXCP08_DBLE     8
 561 #define EXCP09_XERR     9
 562 #define EXCP0A_TSS      10
 563 #define EXCP0B_NOSEG    11
 564 #define EXCP0C_STACK    12
 565 #define EXCP0D_GPF      13
 566 #define EXCP0E_PAGE     14
 567 #define EXCP10_COPR     16
 568 #define EXCP11_ALGN     17
 569 #define EXCP12_MCHK     18
 570
 571 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 572                                  for syscall instruction */
 573
 574 /* i386-specific interrupt pending bits.  */
 575 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
 576 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
 577 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 578 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 579 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 580 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
 581 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2
 582 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_3
 583
 584
 585 typedef enum {
 586     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 587     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 588
 589     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 590     CC_OP_MULW,
 591     CC_OP_MULL,
 592     CC_OP_MULQ,
 593
 594     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 595     CC_OP_ADDW,
 596     CC_OP_ADDL,
 597     CC_OP_ADDQ,
 598
 599     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 600     CC_OP_ADCW,
 601     CC_OP_ADCL,
 602     CC_OP_ADCQ,
 603
 604     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 605     CC_OP_SUBW,
 606     CC_OP_SUBL,
 607     CC_OP_SUBQ,
 608
 609     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 610     CC_OP_SBBW,
 611     CC_OP_SBBL,
 612     CC_OP_SBBQ,
 613
 614     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 615     CC_OP_LOGICW,
 616     CC_OP_LOGICL,
 617     CC_OP_LOGICQ,
 618
 619     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 620     CC_OP_INCW,
 621     CC_OP_INCL,
 622     CC_OP_INCQ,
 623
 624     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 625     CC_OP_DECW,
 626     CC_OP_DECL,
 627     CC_OP_DECQ,
 628
 629     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 630     CC_OP_SHLW,
 631     CC_OP_SHLL,
 632     CC_OP_SHLQ,
 633
 634     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 635     CC_OP_SARW,
 636     CC_OP_SARL,
 637     CC_OP_SARQ,
 638
 639     CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
 640     CC_OP_BMILGW,
 641     CC_OP_BMILGL,
 642     CC_OP_BMILGQ,
 643
 644     CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
 645     CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest.  */
 646     CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
 647
 648     CC_OP_CLR, /* Z set, all other flags clear.  */
 649
 650     CC_OP_NB,
 651 } CCOp;
 652
 653 typedef struct SegmentCache {
 654     uint32_t selector;
 655     target_ulong base;
 656     uint32_t limit;
 657     uint32_t flags;
 658 } SegmentCache;
 659
 660 typedef union {
 661     uint8_t _b[16];
 662     uint16_t _w[8];
 663     uint32_t _l[4];
 664     uint64_t _q[2];
 665     float32 _s[4];
 666     float64 _d[2];
 667 } XMMReg;
 668
 669 typedef union {
 670     uint8_t _b[8];
 671     uint16_t _w[4];
 672     uint32_t _l[2];
 673     float32 _s[2];
 674     uint64_t q;
 675 } MMXReg;
 676
 677 #ifdef HOST_WORDS_BIGENDIAN
 678 #define XMM_B(n) _b[15 - (n)]
 679 #define XMM_W(n) _w[7 - (n)]
 680 #define XMM_L(n) _l[3 - (n)]
 681 #define XMM_S(n) _s[3 - (n)]
 682 #define XMM_Q(n) _q[1 - (n)]
 683 #define XMM_D(n) _d[1 - (n)]
 684
 685 #define MMX_B(n) _b[7 - (n)]
 686 #define MMX_W(n) _w[3 - (n)]
 687 #define MMX_L(n) _l[1 - (n)]
 688 #define MMX_S(n) _s[1 - (n)]
 689 #else
 690 #define XMM_B(n) _b[n]
 691 #define XMM_W(n) _w[n]
 692 #define XMM_L(n) _l[n]
 693 #define XMM_S(n) _s[n]
 694 #define XMM_Q(n) _q[n]
 695 #define XMM_D(n) _d[n]
 696
 697 #define MMX_B(n) _b[n]
 698 #define MMX_W(n) _w[n]
 699 #define MMX_L(n) _l[n]
 700 #define MMX_S(n) _s[n]
 701 #endif
 702 #define MMX_Q(n) q
 703
 704 typedef union {
 705     floatx80 d __attribute__((aligned(16)));
 706     MMXReg mmx;
 707 } FPReg;
 708
 709 typedef struct {
 710     uint64_t base;
 711     uint64_t mask;
 712 } MTRRVar;
 713
 714 #define CPU_NB_REGS64 16
 715 #define CPU_NB_REGS32 8
 716
 717 #ifdef TARGET_X86_64
 718 #define CPU_NB_REGS CPU_NB_REGS64
 719 #else
 720 #define CPU_NB_REGS CPU_NB_REGS32
 721 #endif
 722
 723 #define NB_MMU_MODES 3
 724
 725 typedef enum TPRAccess {
 726     TPR_ACCESS_READ,
 727     TPR_ACCESS_WRITE,
 728 } TPRAccess;
 729
 730 typedef struct CPUX86State {
 731     /* standard registers */
 732     target_ulong regs[CPU_NB_REGS];
 733     target_ulong eip;
 734     target_ulong eflags; /* eflags register. During CPU emulation, CC
 735                         flags and DF are set to zero because they are
 736                         stored elsewhere */
 737
 738     /* emulator internal eflags handling */
 739     target_ulong cc_dst;
 740     target_ulong cc_src;
 741     target_ulong cc_src2;
 742     uint32_t cc_op;
 743     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 744     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 745                         are known at translation time. */
 746     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 747
 748     /* segments */
 749     SegmentCache segs[6]; /* selector values */
 750     SegmentCache ldt;
 751     SegmentCache tr;
 752     SegmentCache gdt; /* only base and limit are used */
 753     SegmentCache idt; /* only base and limit are used */
 754
 755     target_ulong cr[5]; /* NOTE: cr1 is unused */
 756     int32_t a20_mask;
 757
 758     /* FPU state */
 759     unsigned int fpstt; /* top of stack index */
 760     uint16_t fpus;
 761     uint16_t fpuc;
 762     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 763     FPReg fpregs[8];
 764     /* KVM-only so far */
 765     uint16_t fpop;
 766     uint64_t fpip;
 767     uint64_t fpdp;
 768
 769     /* emulator internal variables */
 770     float_status fp_status;
 771     floatx80 ft0;
 772
 773     float_status mmx_status; /* for 3DNow! float ops */
 774     float_status sse_status;
 775     uint32_t mxcsr;
 776     XMMReg xmm_regs[CPU_NB_REGS];
 777     XMMReg xmm_t0;
 778     MMXReg mmx_t0;
 779
 780     /* sysenter registers */
 781     uint32_t sysenter_cs;
 782     target_ulong sysenter_esp;
 783     target_ulong sysenter_eip;
 784     uint64_t efer;
 785     uint64_t star;
 786
 787     uint64_t vm_hsave;
 788     uint64_t vm_vmcb;
 789     uint64_t tsc_offset;
 790     uint64_t intercept;
 791     uint16_t intercept_cr_read;
 792     uint16_t intercept_cr_write;
 793     uint16_t intercept_dr_read;
 794     uint16_t intercept_dr_write;
 795     uint32_t intercept_exceptions;
 796     uint8_t v_tpr;
 797
 798 #ifdef TARGET_X86_64
 799     target_ulong lstar;
 800     target_ulong cstar;
 801     target_ulong fmask;
 802     target_ulong kernelgsbase;
 803 #endif
 804     uint64_t system_time_msr;
 805     uint64_t wall_clock_msr;
 806     uint64_t async_pf_en_msr;
 807     uint64_t pv_eoi_en_msr;
 808
 809     uint64_t tsc;
 810     uint64_t tsc_adjust;
 811     uint64_t tsc_deadline;
 812
 813     uint64_t mcg_status;
 814     uint64_t msr_ia32_misc_enable;
 815
 816     /* exception/interrupt handling */
 817     int error_code;
 818     int exception_is_int;
 819     target_ulong exception_next_eip;
 820     target_ulong dr[8]; /* debug registers */
 821     union {
 822         CPUBreakpoint *cpu_breakpoint[4];
 823         CPUWatchpoint *cpu_watchpoint[4];
 824     }; /* break/watchpoints for dr[0..3] */
 825     uint32_t smbase;
 826     int old_exception;  /* exception in flight */
 827
 828     /* KVM states, automatically cleared on reset */
 829     uint8_t nmi_injected;
 830     uint8_t nmi_pending;
 831
 832     CPU_COMMON
 833
 834     uint64_t pat;
 835
 836     /* processor features (e.g. for CPUID insn) */
 837     uint32_t cpuid_level;
 838     uint32_t cpuid_vendor1;
 839     uint32_t cpuid_vendor2;
 840     uint32_t cpuid_vendor3;
 841     uint32_t cpuid_version;
 842     uint32_t cpuid_features;
 843     uint32_t cpuid_ext_features;
 844     uint32_t cpuid_xlevel;
 845     uint32_t cpuid_model[12];
 846     uint32_t cpuid_ext2_features;
 847     uint32_t cpuid_ext3_features;
 848     uint32_t cpuid_apic_id;
 849     /* Store the results of Centaur's CPUID instructions */
 850     uint32_t cpuid_xlevel2;
 851     uint32_t cpuid_ext4_features;
 852     /* Flags from CPUID[EAX=7,ECX=0].EBX */
 853     uint32_t cpuid_7_0_ebx_features;
 854
 855     /* MTRRs */
 856     uint64_t mtrr_fixed[11];
 857     uint64_t mtrr_deftype;
 858     MTRRVar mtrr_var[8];
 859
 860     /* For KVM */
 861     uint32_t mp_state;
 862     int32_t exception_injected;
 863     int32_t interrupt_injected;
 864     uint8_t soft_interrupt;
 865     uint8_t has_error_code;
 866     uint32_t sipi_vector;
 867     uint32_t cpuid_kvm_features;
 868     uint32_t cpuid_svm_features;
 869     bool tsc_valid;
 870     int tsc_khz;
 871     void *kvm_xsave_buf;
 872
 873     /* in order to simplify APIC support, we leave this pointer to the
 874        user */
 875     struct DeviceState *apic_state;
 876
 877     uint64_t mcg_cap;
 878     uint64_t mcg_ctl;
 879     uint64_t mce_banks[MCE_BANKS_DEF*4];
 880
 881     uint64_t tsc_aux;
 882
 883     /* vmstate */
 884     uint16_t fpus_vmstate;
 885     uint16_t fptag_vmstate;
 886     uint16_t fpregs_format_vmstate;
 887
 888     uint64_t xstate_bv;
 889     XMMReg ymmh_regs[CPU_NB_REGS];
 890
 891     uint64_t xcr0;
 892
 893     TPRAccess tpr_access_type;
 894 } CPUX86State;
 895
 896 #include "cpu-qom.h"
 897
 898 X86CPU *cpu_x86_init(const char *cpu_model);
 899 int cpu_x86_exec(CPUX86State *s);
 900 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 901 void x86_cpudef_setup(void);
 902 int cpu_x86_support_mca_broadcast(CPUX86State *env);
 903
 904 int cpu_get_pic_interrupt(CPUX86State *s);
 905 /* MSDOS compatibility mode FPU exception support */
 906 void cpu_set_ferr(CPUX86State *s);
 907
 908 /* this function must always be used to load data in the segment
 909    cache: it synchronizes the hflags with the segment cache values */
 910 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 911                                           int seg_reg, unsigned int selector,
 912                                           target_ulong base,
 913                                           unsigned int limit,
 914                                           unsigned int flags)
 915 {
 916     SegmentCache *sc;
 917     unsigned int new_hflags;
 918
 919     sc = &env->segs[seg_reg];
 920     sc->selector = selector;
 921     sc->base = base;
 922     sc->limit = limit;
 923     sc->flags = flags;
 924
 925     /* update the hidden flags */
 926     {
 927         if (seg_reg == R_CS) {
 928 #ifdef TARGET_X86_64
 929             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 930                 /* long mode */
 931                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 932                 env->hflags &= ~(HF_ADDSEG_MASK);
 933             } else
 934 #endif
 935             {
 936                 /* legacy / compatibility case */
 937                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 938                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 939                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 940                     new_hflags;
 941             }
 942         }
 943         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 944             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 945         if (env->hflags & HF_CS64_MASK) {
 946             /* zero base assumed for DS, ES and SS in long mode */
 947         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 948                    (env->eflags & VM_MASK) ||
 949                    !(env->hflags & HF_CS32_MASK)) {
 950             /* XXX: try to avoid this test. The problem comes from the
 951                fact that is real mode or vm86 mode we only modify the
 952                'base' and 'selector' fields of the segment cache to go
 953                faster. A solution may be to force addseg to one in
 954                translate-i386.c. */
 955             new_hflags |= HF_ADDSEG_MASK;
 956         } else {
 957             new_hflags |= ((env->segs[R_DS].base |
 958                             env->segs[R_ES].base |
 959                             env->segs[R_SS].base) != 0) <<
 960                 HF_ADDSEG_SHIFT;
 961         }
 962         env->hflags = (env->hflags &
 963                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 964     }
 965 }
 966
 967 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
 968                                                int sipi_vector)
 969 {
 970     CPUState *cs = CPU(cpu);
 971     CPUX86State *env = &cpu->env;
 972
 973     env->eip = 0;
 974     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
 975                            sipi_vector << 12,
 976                            env->segs[R_CS].limit,
 977                            env->segs[R_CS].flags);
 978     cs->halted = 0;
 979 }
 980
 981 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 982                             target_ulong *base, unsigned int *limit,
 983                             unsigned int *flags);
 984
 985 /* wrapper, just in case memory mappings must be changed */
 986 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 987 {
 988 #if HF_CPL_MASK == 3
 989     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 990 #else
 991 #error HF_CPL_MASK is hardcoded
 992 #endif
 993 }
 994
 995 /* op_helper.c */
 996 /* used for debug or cpu save/restore */
 997 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
 998 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
 999
1000 /* cpu-exec.c */
1001 /* the following helpers are only usable in user mode simulation as
1002    they can trigger unexpected exceptions */
1003 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1004 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1005 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1006
1007 /* you can call this signal handler from your SIGBUS and SIGSEGV
1008    signal handlers to inform the virtual CPU of exceptions. non zero
1009    is returned if the signal was handled by the virtual CPU.  */
1010 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1011                            void *puc);
1012
1013 /* cpuid.c */
1014 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1015                    uint32_t *eax, uint32_t *ebx,
1016                    uint32_t *ecx, uint32_t *edx);
1017 void cpu_clear_apic_feature(CPUX86State *env);
1018 void host_cpuid(uint32_t function, uint32_t count,
1019                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1020
1021 /* helper.c */
1022 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
1023                              int is_write, int mmu_idx);
1024 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
1025 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1026
1027 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
1028 {
1029     return (dr7 >> (index * 2)) & 1;
1030 }
1031
1032 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1033 {
1034     return (dr7 >> (index * 2)) & 2;
1035
1036 }
1037 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1038 {
1039     return hw_global_breakpoint_enabled(dr7, index) ||
1040            hw_local_breakpoint_enabled(dr7, index);
1041 }
1042
1043 static inline int hw_breakpoint_type(unsigned long dr7, int index)
1044 {
1045     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1046 }
1047
1048 static inline int hw_breakpoint_len(unsigned long dr7, int index)
1049 {
1050     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1051     return (len == 2) ? 8 : len + 1;
1052 }
1053
1054 void hw_breakpoint_insert(CPUX86State *env, int index);
1055 void hw_breakpoint_remove(CPUX86State *env, int index);
1056 bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
1057 void breakpoint_handler(CPUX86State *env);
1058
1059 /* will be suppressed */
1060 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1061 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1062 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1063
1064 /* hw/pc.c */
1065 void cpu_smm_update(CPUX86State *env);
1066 uint64_t cpu_get_tsc(CPUX86State *env);
1067
1068 #define TARGET_PAGE_BITS 12
1069
1070 #ifdef TARGET_X86_64
1071 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1072 /* ??? This is really 48 bits, sign-extended, but the only thing
1073    accessible to userland with bit 48 set is the VSYSCALL, and that
1074    is handled via other mechanisms.  */
1075 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1076 #else
1077 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1078 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1079 #endif
1080
1081 static inline CPUX86State *cpu_init(const char *cpu_model)
1082 {
1083     X86CPU *cpu = cpu_x86_init(cpu_model);
1084     if (cpu == NULL) {
1085         return NULL;
1086     }
1087     return &cpu->env;
1088 }
1089
1090 #define cpu_exec cpu_x86_exec
1091 #define cpu_gen_code cpu_x86_gen_code
1092 #define cpu_signal_handler cpu_x86_signal_handler
1093 #define cpu_list x86_cpu_list
1094 #define cpudef_setup    x86_cpudef_setup
1095
1096 /* MMU modes definitions */
1097 #define MMU_MODE0_SUFFIX _kernel
1098 #define MMU_MODE1_SUFFIX _user
1099 #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */
1100 #define MMU_KERNEL_IDX  0
1101 #define MMU_USER_IDX    1
1102 #define MMU_KSMAP_IDX   2
1103 static inline int cpu_mmu_index (CPUX86State *env)
1104 {
1105     return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1106         ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
1107         ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
1108 }
1109
1110 #undef EAX
1111 #define EAX (env->regs[R_EAX])
1112 #undef ECX
1113 #define ECX (env->regs[R_ECX])
1114 #undef EDX
1115 #define EDX (env->regs[R_EDX])
1116 #undef EBX
1117 #define EBX (env->regs[R_EBX])
1118 #undef ESP
1119 #define ESP (env->regs[R_ESP])
1120 #undef EBP
1121 #define EBP (env->regs[R_EBP])
1122 #undef ESI
1123 #define ESI (env->regs[R_ESI])
1124 #undef EDI
1125 #define EDI (env->regs[R_EDI])
1126 #undef EIP
1127 #define EIP (env->eip)
1128 #define DF  (env->df)
1129
1130 #define CC_DST  (env->cc_dst)
1131 #define CC_SRC  (env->cc_src)
1132 #define CC_SRC2 (env->cc_src2)
1133 #define CC_OP   (env->cc_op)
1134
1135 /* n must be a constant to be efficient */
1136 static inline target_long lshift(target_long x, int n)
1137 {
1138     if (n >= 0) {
1139         return x << n;
1140     } else {
1141         return x >> (-n);
1142     }
1143 }
1144
1145 /* float macros */
1146 #define FT0    (env->ft0)
1147 #define ST0    (env->fpregs[env->fpstt].d)
1148 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
1149 #define ST1    ST(1)
1150
1151 /* translate.c */
1152 void optimize_flags_init(void);
1153
1154 #if defined(CONFIG_USER_ONLY)
1155 static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp)
1156 {
1157     if (newsp)
1158         env->regs[R_ESP] = newsp;
1159     env->regs[R_EAX] = 0;
1160 }
1161 #endif
1162
1163 #include "exec/cpu-all.h"
1164 #include "svm.h"
1165
1166 #if !defined(CONFIG_USER_ONLY)
1167 #include "hw/apic.h"
1168 #endif
1169
1170 static inline bool cpu_has_work(CPUState *cs)
1171 {
1172     X86CPU *cpu = X86_CPU(cs);
1173     CPUX86State *env = &cpu->env;
1174
1175     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
1176                                       CPU_INTERRUPT_POLL)) &&
1177             (env->eflags & IF_MASK)) ||
1178            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
1179                                      CPU_INTERRUPT_INIT |
1180                                      CPU_INTERRUPT_SIPI |
1181                                      CPU_INTERRUPT_MCE));
1182 }
1183
1184 #include "exec/exec-all.h"
1185
1186 static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb)
1187 {
1188     env->eip = tb->pc - tb->cs_base;
1189 }
1190
1191 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1192                                         target_ulong *cs_base, int *flags)
1193 {
1194     *cs_base = env->segs[R_CS].base;
1195     *pc = *cs_base + env->eip;
1196     *flags = env->hflags |
1197         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1198 }
1199
1200 void do_cpu_init(X86CPU *cpu);
1201 void do_cpu_sipi(X86CPU *cpu);
1202
1203 #define MCE_INJECT_BROADCAST    1
1204 #define MCE_INJECT_UNCOND_AO    2
1205
1206 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1207                         uint64_t status, uint64_t mcg_status, uint64_t addr,
1208                         uint64_t misc, int flags);
1209
1210 /* excp_helper.c */
1211 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1212 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1213                                        int error_code);
1214 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1215                                    int error_code, int next_eip_addend);
1216
1217 /* cc_helper.c */
1218 extern const uint8_t parity_table[256];
1219 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1220
1221 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1222 {
1223     return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
1224 }
1225
1226 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
1227 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1228                                    int update_mask)
1229 {
1230     CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1231     DF = 1 - (2 * ((eflags >> 10) & 1));
1232     env->eflags = (env->eflags & ~update_mask) |
1233         (eflags & update_mask) | 0x2;
1234 }
1235
1236 /* load efer and update the corresponding hflags. XXX: do consistency
1237    checks with cpuid bits? */
1238 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1239 {
1240     env->efer = val;
1241     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1242     if (env->efer & MSR_EFER_LMA) {
1243         env->hflags |= HF_LMA_MASK;
1244     }
1245     if (env->efer & MSR_EFER_SVME) {
1246         env->hflags |= HF_SVME_MASK;
1247     }
1248 }
1249
1250 /* svm_helper.c */
1251 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1252                                    uint64_t param);
1253 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1254
1255 /* seg_helper.c */
1256 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1257
1258 void do_smm_enter(CPUX86State *env1);
1259
1260 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1261
1262 void disable_kvm_pv_eoi(void);
1263
1264 /* Return name of 32-bit register, from a R_* constant */
1265 const char *get_register_name_32(unsigned int reg);
1266
1267 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
1268 void enable_compat_apic_id_mode(void);
1269
1270 #define APIC_DEFAULT_ADDRESS 0xfee00000
1271
1272 #endif /* CPU_I386_H */