hw/i8259_common.c

   1 /*
   2  * QEMU 8259 - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/pc.h"
  26 #include "hw/i8259_internal.h"
  27
  28 void pic_reset_common(PICCommonState *s)
  29 {
  30     s->last_irr = 0;
  31     s->irr &= s->elcr;
  32     s->imr = 0;
  33     s->isr = 0;
  34     s->priority_add = 0;
  35     s->irq_base = 0;
  36     s->read_reg_select = 0;
  37     s->poll = 0;
  38     s->special_mask = 0;
  39     s->init_state = 0;
  40     s->auto_eoi = 0;
  41     s->rotate_on_auto_eoi = 0;
  42     s->special_fully_nested_mode = 0;
  43     s->init4 = 0;
  44     s->single_mode = 0;
  45     /* Note: ELCR is not reset */
  46 }
  47
  48 static void pic_dispatch_pre_save(void *opaque)
  49 {
  50     PICCommonState *s = opaque;
  51     PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  52
  53     if (info->pre_save) {
  54         info->pre_save(s);
  55     }
  56 }
  57
  58 static int pic_dispatch_post_load(void *opaque, int version_id)
  59 {
  60     PICCommonState *s = opaque;
  61     PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  62
  63     if (info->post_load) {
  64         info->post_load(s);
  65     }
  66     return 0;
  67 }
  68
  69 static int pic_init_common(ISADevice *dev)
  70 {
  71     PICCommonState *s = DO_UPCAST(PICCommonState, dev, dev);
  72     PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  73
  74     info->init(s);
  75
  76     isa_register_ioport(NULL, &s->base_io, s->iobase);
  77     if (s->elcr_addr != -1) {
  78         isa_register_ioport(NULL, &s->elcr_io, s->elcr_addr);
  79     }
  80
  81     qdev_set_legacy_instance_id(&s->dev.qdev, s->iobase, 1);
  82
  83     return 0;
  84 }
  85
  86 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
  87 {
  88     ISADevice *dev;
  89
  90     dev = isa_create(bus, name);
  91     qdev_prop_set_uint32(&dev->qdev, "iobase", master ? 0x20 : 0xa0);
  92     qdev_prop_set_uint32(&dev->qdev, "elcr_addr", master ? 0x4d0 : 0x4d1);
  93     qdev_prop_set_uint8(&dev->qdev, "elcr_mask", master ? 0xf8 : 0xde);
  94     qdev_prop_set_bit(&dev->qdev, "master", master);
  95     qdev_init_nofail(&dev->qdev);
  96
  97     return dev;
  98 }
  99
 100 static const VMStateDescription vmstate_pic_common = {
 101     .name = "i8259",
 102     .version_id = 1,
 103     .minimum_version_id = 1,
 104     .minimum_version_id_old = 1,
 105     .pre_save = pic_dispatch_pre_save,
 106     .post_load = pic_dispatch_post_load,
 107     .fields = (VMStateField[]) {
 108         VMSTATE_UINT8(last_irr, PICCommonState),
 109         VMSTATE_UINT8(irr, PICCommonState),
 110         VMSTATE_UINT8(imr, PICCommonState),
 111         VMSTATE_UINT8(isr, PICCommonState),
 112         VMSTATE_UINT8(priority_add, PICCommonState),
 113         VMSTATE_UINT8(irq_base, PICCommonState),
 114         VMSTATE_UINT8(read_reg_select, PICCommonState),
 115         VMSTATE_UINT8(poll, PICCommonState),
 116         VMSTATE_UINT8(special_mask, PICCommonState),
 117         VMSTATE_UINT8(init_state, PICCommonState),
 118         VMSTATE_UINT8(auto_eoi, PICCommonState),
 119         VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
 120         VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
 121         VMSTATE_UINT8(init4, PICCommonState),
 122         VMSTATE_UINT8(single_mode, PICCommonState),
 123         VMSTATE_UINT8(elcr, PICCommonState),
 124         VMSTATE_END_OF_LIST()
 125     }
 126 };
 127
 128 static Property pic_properties_common[] = {
 129     DEFINE_PROP_HEX32("iobase", PICCommonState, iobase,  -1),
 130     DEFINE_PROP_HEX32("elcr_addr", PICCommonState, elcr_addr,  -1),
 131     DEFINE_PROP_HEX8("elcr_mask", PICCommonState, elcr_mask,  -1),
 132     DEFINE_PROP_BIT("master", PICCommonState, master,  0, false),
 133     DEFINE_PROP_END_OF_LIST(),
 134 };
 135
 136 static void pic_common_class_init(ObjectClass *klass, void *data)
 137 {
 138     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 139     DeviceClass *dc = DEVICE_CLASS(klass);
 140
 141     dc->vmsd = &vmstate_pic_common;
 142     dc->no_user = 1;
 143     dc->props = pic_properties_common;
 144     ic->init = pic_init_common;
 145 }
 146
 147 static const TypeInfo pic_common_type = {
 148     .name = TYPE_PIC_COMMON,
 149     .parent = TYPE_ISA_DEVICE,
 150     .instance_size = sizeof(PICCommonState),
 151     .class_size = sizeof(PICCommonClass),
 152     .class_init = pic_common_class_init,
 153     .abstract = true,
 154 };
 155
 156 static void register_types(void)
 157 {
 158     type_register_static(&pic_common_type);
 159 }
 160
 161 type_init(register_types);