hw/xilinx_axienet.c

   1 /*
   2  * QEMU model of Xilinx AXI-Ethernet.
   3  *
   4  * Copyright (c) 2011 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu/log.h"
  27 #include "net/net.h"
  28 #include "net/checksum.h"
  29
  30 #include "stream.h"
  31
  32 #define DPHY(x)
  33
  34 /* Advertisement control register. */
  35 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  36 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  37 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  38 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  39
  40 struct PHY {
  41     uint32_t regs[32];
  42
  43     int link;
  44
  45     unsigned int (*read)(struct PHY *phy, unsigned int req);
  46     void (*write)(struct PHY *phy, unsigned int req,
  47                   unsigned int data);
  48 };
  49
  50 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
  51 {
  52     int regnum;
  53     unsigned r = 0;
  54
  55     regnum = req & 0x1f;
  56
  57     switch (regnum) {
  58         case 1:
  59             if (!phy->link) {
  60                 break;
  61             }
  62             /* MR1.  */
  63             /* Speeds and modes.  */
  64             r |= (1 << 13) | (1 << 14);
  65             r |= (1 << 11) | (1 << 12);
  66             r |= (1 << 5); /* Autoneg complete.  */
  67             r |= (1 << 3); /* Autoneg able.  */
  68             r |= (1 << 2); /* link.  */
  69             r |= (1 << 1); /* link.  */
  70             break;
  71         case 5:
  72             /* Link partner ability.
  73                We are kind; always agree with whatever best mode
  74                the guest advertises.  */
  75             r = 1 << 14; /* Success.  */
  76             /* Copy advertised modes.  */
  77             r |= phy->regs[4] & (15 << 5);
  78             /* Autoneg support.  */
  79             r |= 1;
  80             break;
  81         case 17:
  82             /* Marvel PHY on many xilinx boards.  */
  83             r = 0x8000; /* 1000Mb  */
  84             break;
  85         case 18:
  86             {
  87                 /* Diagnostics reg.  */
  88                 int duplex = 0;
  89                 int speed_100 = 0;
  90
  91                 if (!phy->link) {
  92                     break;
  93                 }
  94
  95                 /* Are we advertising 100 half or 100 duplex ? */
  96                 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
  97                 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
  98
  99                 /* Are we advertising 10 duplex or 100 duplex ? */
 100                 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
 101                 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
 102                 r = (speed_100 << 10) | (duplex << 11);
 103             }
 104             break;
 105
 106         default:
 107             r = phy->regs[regnum];
 108             break;
 109     }
 110     DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
 111     return r;
 112 }
 113
 114 static void
 115 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
 116 {
 117     int regnum;
 118
 119     regnum = req & 0x1f;
 120     DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
 121     switch (regnum) {
 122         default:
 123             phy->regs[regnum] = data;
 124             break;
 125     }
 126 }
 127
 128 static void
 129 tdk_init(struct PHY *phy)
 130 {
 131     phy->regs[0] = 0x3100;
 132     /* PHY Id.  */
 133     phy->regs[2] = 0x0300;
 134     phy->regs[3] = 0xe400;
 135     /* Autonegotiation advertisement reg.  */
 136     phy->regs[4] = 0x01E1;
 137     phy->link = 1;
 138
 139     phy->read = tdk_read;
 140     phy->write = tdk_write;
 141 }
 142
 143 struct MDIOBus {
 144     /* bus.  */
 145     int mdc;
 146     int mdio;
 147
 148     /* decoder.  */
 149     enum {
 150         PREAMBLE,
 151         SOF,
 152         OPC,
 153         ADDR,
 154         REQ,
 155         TURNAROUND,
 156         DATA
 157     } state;
 158     unsigned int drive;
 159
 160     unsigned int cnt;
 161     unsigned int addr;
 162     unsigned int opc;
 163     unsigned int req;
 164     unsigned int data;
 165
 166     struct PHY *devs[32];
 167 };
 168
 169 static void
 170 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 171 {
 172     bus->devs[addr & 0x1f] = phy;
 173 }
 174
 175 #ifdef USE_THIS_DEAD_CODE
 176 static void
 177 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 178 {
 179     bus->devs[addr & 0x1f] = NULL;
 180 }
 181 #endif
 182
 183 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
 184                   unsigned int reg)
 185 {
 186     struct PHY *phy;
 187     uint16_t data;
 188
 189     phy = bus->devs[addr];
 190     if (phy && phy->read) {
 191         data = phy->read(phy, reg);
 192     } else {
 193         data = 0xffff;
 194     }
 195     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 196     return data;
 197 }
 198
 199 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
 200                unsigned int reg, uint16_t data)
 201 {
 202     struct PHY *phy;
 203
 204     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 205     phy = bus->devs[addr];
 206     if (phy && phy->write) {
 207         phy->write(phy, reg, data);
 208     }
 209 }
 210
 211 #define DENET(x)
 212
 213 #define R_RAF      (0x000 / 4)
 214 enum {
 215     RAF_MCAST_REJ = (1 << 1),
 216     RAF_BCAST_REJ = (1 << 2),
 217     RAF_EMCF_EN = (1 << 12),
 218     RAF_NEWFUNC_EN = (1 << 11)
 219 };
 220
 221 #define R_IS       (0x00C / 4)
 222 enum {
 223     IS_HARD_ACCESS_COMPLETE = 1,
 224     IS_AUTONEG = (1 << 1),
 225     IS_RX_COMPLETE = (1 << 2),
 226     IS_RX_REJECT = (1 << 3),
 227     IS_TX_COMPLETE = (1 << 5),
 228     IS_RX_DCM_LOCK = (1 << 6),
 229     IS_MGM_RDY = (1 << 7),
 230     IS_PHY_RST_DONE = (1 << 8),
 231 };
 232
 233 #define R_IP       (0x010 / 4)
 234 #define R_IE       (0x014 / 4)
 235 #define R_UAWL     (0x020 / 4)
 236 #define R_UAWU     (0x024 / 4)
 237 #define R_PPST     (0x030 / 4)
 238 enum {
 239     PPST_LINKSTATUS = (1 << 0),
 240     PPST_PHY_LINKSTATUS = (1 << 7),
 241 };
 242
 243 #define R_STATS_RX_BYTESL (0x200 / 4)
 244 #define R_STATS_RX_BYTESH (0x204 / 4)
 245 #define R_STATS_TX_BYTESL (0x208 / 4)
 246 #define R_STATS_TX_BYTESH (0x20C / 4)
 247 #define R_STATS_RXL       (0x290 / 4)
 248 #define R_STATS_RXH       (0x294 / 4)
 249 #define R_STATS_RX_BCASTL (0x2a0 / 4)
 250 #define R_STATS_RX_BCASTH (0x2a4 / 4)
 251 #define R_STATS_RX_MCASTL (0x2a8 / 4)
 252 #define R_STATS_RX_MCASTH (0x2ac / 4)
 253
 254 #define R_RCW0     (0x400 / 4)
 255 #define R_RCW1     (0x404 / 4)
 256 enum {
 257     RCW1_VLAN = (1 << 27),
 258     RCW1_RX   = (1 << 28),
 259     RCW1_FCS  = (1 << 29),
 260     RCW1_JUM  = (1 << 30),
 261     RCW1_RST  = (1 << 31),
 262 };
 263
 264 #define R_TC       (0x408 / 4)
 265 enum {
 266     TC_VLAN = (1 << 27),
 267     TC_TX   = (1 << 28),
 268     TC_FCS  = (1 << 29),
 269     TC_JUM  = (1 << 30),
 270     TC_RST  = (1 << 31),
 271 };
 272
 273 #define R_EMMC     (0x410 / 4)
 274 enum {
 275     EMMC_LINKSPEED_10MB = (0 << 30),
 276     EMMC_LINKSPEED_100MB = (1 << 30),
 277     EMMC_LINKSPEED_1000MB = (2 << 30),
 278 };
 279
 280 #define R_PHYC     (0x414 / 4)
 281
 282 #define R_MC       (0x500 / 4)
 283 #define MC_EN      (1 << 6)
 284
 285 #define R_MCR      (0x504 / 4)
 286 #define R_MWD      (0x508 / 4)
 287 #define R_MRD      (0x50c / 4)
 288 #define R_MIS      (0x600 / 4)
 289 #define R_MIP      (0x620 / 4)
 290 #define R_MIE      (0x640 / 4)
 291 #define R_MIC      (0x640 / 4)
 292
 293 #define R_UAW0     (0x700 / 4)
 294 #define R_UAW1     (0x704 / 4)
 295 #define R_FMI      (0x708 / 4)
 296 #define R_AF0      (0x710 / 4)
 297 #define R_AF1      (0x714 / 4)
 298 #define R_MAX      (0x34 / 4)
 299
 300 /* Indirect registers.  */
 301 struct TEMAC  {
 302     struct MDIOBus mdio_bus;
 303     struct PHY phy;
 304
 305     void *parent;
 306 };
 307
 308 struct XilinxAXIEnet {
 309     SysBusDevice busdev;
 310     MemoryRegion iomem;
 311     qemu_irq irq;
 312     StreamSlave *tx_dev;
 313     NICState *nic;
 314     NICConf conf;
 315
 316
 317     uint32_t c_rxmem;
 318     uint32_t c_txmem;
 319     uint32_t c_phyaddr;
 320
 321     struct TEMAC TEMAC;
 322
 323     /* MII regs.  */
 324     union {
 325         uint32_t regs[4];
 326         struct {
 327             uint32_t mc;
 328             uint32_t mcr;
 329             uint32_t mwd;
 330             uint32_t mrd;
 331         };
 332     } mii;
 333
 334     struct {
 335         uint64_t rx_bytes;
 336         uint64_t tx_bytes;
 337
 338         uint64_t rx;
 339         uint64_t rx_bcast;
 340         uint64_t rx_mcast;
 341     } stats;
 342
 343     /* Receive configuration words.  */
 344     uint32_t rcw[2];
 345     /* Transmit config.  */
 346     uint32_t tc;
 347     uint32_t emmc;
 348     uint32_t phyc;
 349
 350     /* Unicast Address Word.  */
 351     uint32_t uaw[2];
 352     /* Unicast address filter used with extended mcast.  */
 353     uint32_t ext_uaw[2];
 354     uint32_t fmi;
 355
 356     uint32_t regs[R_MAX];
 357
 358     /* Multicast filter addrs.  */
 359     uint32_t maddr[4][2];
 360     /* 32K x 1 lookup filter.  */
 361     uint32_t ext_mtable[1024];
 362
 363
 364     uint8_t *rxmem;
 365 };
 366
 367 static void axienet_rx_reset(struct XilinxAXIEnet *s)
 368 {
 369     s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
 370 }
 371
 372 static void axienet_tx_reset(struct XilinxAXIEnet *s)
 373 {
 374     s->tc = TC_JUM | TC_TX | TC_VLAN;
 375 }
 376
 377 static inline int axienet_rx_resetting(struct XilinxAXIEnet *s)
 378 {
 379     return s->rcw[1] & RCW1_RST;
 380 }
 381
 382 static inline int axienet_rx_enabled(struct XilinxAXIEnet *s)
 383 {
 384     return s->rcw[1] & RCW1_RX;
 385 }
 386
 387 static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s)
 388 {
 389     return !!(s->regs[R_RAF] & RAF_EMCF_EN);
 390 }
 391
 392 static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s)
 393 {
 394     return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
 395 }
 396
 397 static void axienet_reset(struct XilinxAXIEnet *s)
 398 {
 399     axienet_rx_reset(s);
 400     axienet_tx_reset(s);
 401
 402     s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
 403     s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
 404
 405     s->emmc = EMMC_LINKSPEED_100MB;
 406 }
 407
 408 static void enet_update_irq(struct XilinxAXIEnet *s)
 409 {
 410     s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
 411     qemu_set_irq(s->irq, !!s->regs[R_IP]);
 412 }
 413
 414 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 415 {
 416     struct XilinxAXIEnet *s = opaque;
 417     uint32_t r = 0;
 418     addr >>= 2;
 419
 420     switch (addr) {
 421         case R_RCW0:
 422         case R_RCW1:
 423             r = s->rcw[addr & 1];
 424             break;
 425
 426         case R_TC:
 427             r = s->tc;
 428             break;
 429
 430         case R_EMMC:
 431             r = s->emmc;
 432             break;
 433
 434         case R_PHYC:
 435             r = s->phyc;
 436             break;
 437
 438         case R_MCR:
 439             r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready.  */
 440             break;
 441
 442         case R_STATS_RX_BYTESL:
 443         case R_STATS_RX_BYTESH:
 444             r = s->stats.rx_bytes >> (32 * (addr & 1));
 445             break;
 446
 447         case R_STATS_TX_BYTESL:
 448         case R_STATS_TX_BYTESH:
 449             r = s->stats.tx_bytes >> (32 * (addr & 1));
 450             break;
 451
 452         case R_STATS_RXL:
 453         case R_STATS_RXH:
 454             r = s->stats.rx >> (32 * (addr & 1));
 455             break;
 456         case R_STATS_RX_BCASTL:
 457         case R_STATS_RX_BCASTH:
 458             r = s->stats.rx_bcast >> (32 * (addr & 1));
 459             break;
 460         case R_STATS_RX_MCASTL:
 461         case R_STATS_RX_MCASTH:
 462             r = s->stats.rx_mcast >> (32 * (addr & 1));
 463             break;
 464
 465         case R_MC:
 466         case R_MWD:
 467         case R_MRD:
 468             r = s->mii.regs[addr & 3];
 469             break;
 470
 471         case R_UAW0:
 472         case R_UAW1:
 473             r = s->uaw[addr & 1];
 474             break;
 475
 476         case R_UAWU:
 477         case R_UAWL:
 478             r = s->ext_uaw[addr & 1];
 479             break;
 480
 481         case R_FMI:
 482             r = s->fmi;
 483             break;
 484
 485         case R_AF0:
 486         case R_AF1:
 487             r = s->maddr[s->fmi & 3][addr & 1];
 488             break;
 489
 490         case 0x8000 ... 0x83ff:
 491             r = s->ext_mtable[addr - 0x8000];
 492             break;
 493
 494         default:
 495             if (addr < ARRAY_SIZE(s->regs)) {
 496                 r = s->regs[addr];
 497             }
 498             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 499                             __func__, addr * 4, r));
 500             break;
 501     }
 502     return r;
 503 }
 504
 505 static void enet_write(void *opaque, hwaddr addr,
 506                        uint64_t value, unsigned size)
 507 {
 508     struct XilinxAXIEnet *s = opaque;
 509     struct TEMAC *t = &s->TEMAC;
 510
 511     addr >>= 2;
 512     switch (addr) {
 513         case R_RCW0:
 514         case R_RCW1:
 515             s->rcw[addr & 1] = value;
 516             if ((addr & 1) && value & RCW1_RST) {
 517                 axienet_rx_reset(s);
 518             }
 519             break;
 520
 521         case R_TC:
 522             s->tc = value;
 523             if (value & TC_RST) {
 524                 axienet_tx_reset(s);
 525             }
 526             break;
 527
 528         case R_EMMC:
 529             s->emmc = value;
 530             break;
 531
 532         case R_PHYC:
 533             s->phyc = value;
 534             break;
 535
 536         case R_MC:
 537              value &= ((1 < 7) - 1);
 538
 539              /* Enable the MII.  */
 540              if (value & MC_EN) {
 541                  unsigned int miiclkdiv = value & ((1 << 6) - 1);
 542                  if (!miiclkdiv) {
 543                      qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
 544                  }
 545              }
 546              s->mii.mc = value;
 547              break;
 548
 549         case R_MCR: {
 550              unsigned int phyaddr = (value >> 24) & 0x1f;
 551              unsigned int regaddr = (value >> 16) & 0x1f;
 552              unsigned int op = (value >> 14) & 3;
 553              unsigned int initiate = (value >> 11) & 1;
 554
 555              if (initiate) {
 556                  if (op == 1) {
 557                      mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
 558                  } else if (op == 2) {
 559                      s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
 560                  } else {
 561                      qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
 562                  }
 563              }
 564              s->mii.mcr = value;
 565              break;
 566         }
 567
 568         case R_MWD:
 569         case R_MRD:
 570              s->mii.regs[addr & 3] = value;
 571              break;
 572
 573
 574         case R_UAW0:
 575         case R_UAW1:
 576             s->uaw[addr & 1] = value;
 577             break;
 578
 579         case R_UAWL:
 580         case R_UAWU:
 581             s->ext_uaw[addr & 1] = value;
 582             break;
 583
 584         case R_FMI:
 585             s->fmi = value;
 586             break;
 587
 588         case R_AF0:
 589         case R_AF1:
 590             s->maddr[s->fmi & 3][addr & 1] = value;
 591             break;
 592
 593         case R_IS:
 594             s->regs[addr] &= ~value;
 595             break;
 596
 597         case 0x8000 ... 0x83ff:
 598             s->ext_mtable[addr - 0x8000] = value;
 599             break;
 600
 601         default:
 602             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 603                            __func__, addr * 4, (unsigned)value));
 604             if (addr < ARRAY_SIZE(s->regs)) {
 605                 s->regs[addr] = value;
 606             }
 607             break;
 608     }
 609     enet_update_irq(s);
 610 }
 611
 612 static const MemoryRegionOps enet_ops = {
 613     .read = enet_read,
 614     .write = enet_write,
 615     .endianness = DEVICE_LITTLE_ENDIAN,
 616 };
 617
 618 static int eth_can_rx(NetClientState *nc)
 619 {
 620     struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
 621
 622     /* RX enabled?  */
 623     return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
 624 }
 625
 626 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
 627 {
 628     int match = 1;
 629
 630     if (memcmp(buf, &f0, 4)) {
 631         match = 0;
 632     }
 633
 634     if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
 635         match = 0;
 636     }
 637
 638     return match;
 639 }
 640
 641 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 642 {
 643     struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
 644     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 645                                               0xff, 0xff, 0xff};
 646     static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
 647     uint32_t app[6] = {0};
 648     int promisc = s->fmi & (1 << 31);
 649     int unicast, broadcast, multicast, ip_multicast = 0;
 650     uint32_t csum32;
 651     uint16_t csum16;
 652     int i;
 653
 654     DENET(qemu_log("%s: %zd bytes\n", __func__, size));
 655
 656     unicast = ~buf[0] & 0x1;
 657     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 658     multicast = !unicast && !broadcast;
 659     if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
 660         ip_multicast = 1;
 661     }
 662
 663     /* Jumbo or vlan sizes ?  */
 664     if (!(s->rcw[1] & RCW1_JUM)) {
 665         if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
 666             return size;
 667         }
 668     }
 669
 670     /* Basic Address filters.  If you want to use the extended filters
 671        you'll generally have to place the ethernet mac into promiscuous mode
 672        to avoid the basic filtering from dropping most frames.  */
 673     if (!promisc) {
 674         if (unicast) {
 675             if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
 676                 return size;
 677             }
 678         } else {
 679             if (broadcast) {
 680                 /* Broadcast.  */
 681                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 682                     return size;
 683                 }
 684             } else {
 685                 int drop = 1;
 686
 687                 /* Multicast.  */
 688                 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
 689                     return size;
 690                 }
 691
 692                 for (i = 0; i < 4; i++) {
 693                     if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
 694                         drop = 0;
 695                         break;
 696                     }
 697                 }
 698
 699                 if (drop) {
 700                     return size;
 701                 }
 702             }
 703         }
 704     }
 705
 706     /* Extended mcast filtering enabled?  */
 707     if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
 708         if (unicast) {
 709             if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
 710                 return size;
 711             }
 712         } else {
 713             if (broadcast) {
 714                 /* Broadcast. ???  */
 715                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 716                     return size;
 717                 }
 718             } else {
 719                 int idx, bit;
 720
 721                 /* Multicast.  */
 722                 if (!memcmp(buf, sa_ipmcast, 3)) {
 723                     return size;
 724                 }
 725
 726                 idx  = (buf[4] & 0x7f) << 8;
 727                 idx |= buf[5];
 728
 729                 bit = 1 << (idx & 0x1f);
 730                 idx >>= 5;
 731
 732                 if (!(s->ext_mtable[idx] & bit)) {
 733                     return size;
 734                 }
 735             }
 736         }
 737     }
 738
 739     if (size < 12) {
 740         s->regs[R_IS] |= IS_RX_REJECT;
 741         enet_update_irq(s);
 742         return -1;
 743     }
 744
 745     if (size > (s->c_rxmem - 4)) {
 746         size = s->c_rxmem - 4;
 747     }
 748
 749     memcpy(s->rxmem, buf, size);
 750     memset(s->rxmem + size, 0, 4); /* Clear the FCS.  */
 751
 752     if (s->rcw[1] & RCW1_FCS) {
 753         size += 4; /* fcs is inband.  */
 754     }
 755
 756     app[0] = 5 << 28;
 757     csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
 758     /* Fold it once.  */
 759     csum32 = (csum32 & 0xffff) + (csum32 >> 16);
 760     /* And twice to get rid of possible carries.  */
 761     csum16 = (csum32 & 0xffff) + (csum32 >> 16);
 762     app[3] = csum16;
 763     app[4] = size & 0xffff;
 764
 765     s->stats.rx_bytes += size;
 766     s->stats.rx++;
 767     if (multicast) {
 768         s->stats.rx_mcast++;
 769         app[2] |= 1 | (ip_multicast << 1);
 770     } else if (broadcast) {
 771         s->stats.rx_bcast++;
 772         app[2] |= 1 << 3;
 773     }
 774
 775     /* Good frame.  */
 776     app[2] |= 1 << 6;
 777
 778     stream_push(s->tx_dev, (void *)s->rxmem, size, app);
 779
 780     s->regs[R_IS] |= IS_RX_COMPLETE;
 781     enet_update_irq(s);
 782     return size;
 783 }
 784
 785 static void eth_cleanup(NetClientState *nc)
 786 {
 787     /* FIXME.  */
 788     struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
 789     g_free(s->rxmem);
 790     g_free(s);
 791 }
 792
 793 static void
 794 axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr)
 795 {
 796     struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
 797
 798     /* TX enable ?  */
 799     if (!(s->tc & TC_TX)) {
 800         return;
 801     }
 802
 803     /* Jumbo or vlan sizes ?  */
 804     if (!(s->tc & TC_JUM)) {
 805         if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
 806             return;
 807         }
 808     }
 809
 810     if (hdr[0] & 1) {
 811         unsigned int start_off = hdr[1] >> 16;
 812         unsigned int write_off = hdr[1] & 0xffff;
 813         uint32_t tmp_csum;
 814         uint16_t csum;
 815
 816         tmp_csum = net_checksum_add(size - start_off,
 817                                     (uint8_t *)buf + start_off);
 818         /* Accumulate the seed.  */
 819         tmp_csum += hdr[2] & 0xffff;
 820
 821         /* Fold the 32bit partial checksum.  */
 822         csum = net_checksum_finish(tmp_csum);
 823
 824         /* Writeback.  */
 825         buf[write_off] = csum >> 8;
 826         buf[write_off + 1] = csum & 0xff;
 827     }
 828
 829     qemu_send_packet(&s->nic->nc, buf, size);
 830
 831     s->stats.tx_bytes += size;
 832     s->regs[R_IS] |= IS_TX_COMPLETE;
 833     enet_update_irq(s);
 834 }
 835
 836 static NetClientInfo net_xilinx_enet_info = {
 837     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 838     .size = sizeof(NICState),
 839     .can_receive = eth_can_rx,
 840     .receive = eth_rx,
 841     .cleanup = eth_cleanup,
 842 };
 843
 844 static int xilinx_enet_init(SysBusDevice *dev)
 845 {
 846     struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
 847
 848     sysbus_init_irq(dev, &s->irq);
 849
 850     memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
 851     sysbus_init_mmio(dev, &s->iomem);
 852
 853     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 854     s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
 855                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 856     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 857
 858     tdk_init(&s->TEMAC.phy);
 859     mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
 860
 861     s->TEMAC.parent = s;
 862
 863     s->rxmem = g_malloc(s->c_rxmem);
 864     axienet_reset(s);
 865
 866     return 0;
 867 }
 868
 869 static void xilinx_enet_initfn(Object *obj)
 870 {
 871     struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
 872
 873     object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
 874                              (Object **) &s->tx_dev, NULL);
 875 }
 876
 877 static Property xilinx_enet_properties[] = {
 878     DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7),
 879     DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000),
 880     DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000),
 881     DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
 882     DEFINE_PROP_END_OF_LIST(),
 883 };
 884
 885 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
 886 {
 887     DeviceClass *dc = DEVICE_CLASS(klass);
 888     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 889     StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
 890
 891     k->init = xilinx_enet_init;
 892     dc->props = xilinx_enet_properties;
 893     ssc->push = axienet_stream_push;
 894 }
 895
 896 static const TypeInfo xilinx_enet_info = {
 897     .name          = "xlnx.axi-ethernet",
 898     .parent        = TYPE_SYS_BUS_DEVICE,
 899     .instance_size = sizeof(struct XilinxAXIEnet),
 900     .class_init    = xilinx_enet_class_init,
 901     .instance_init = xilinx_enet_initfn,
 902     .interfaces = (InterfaceInfo[]) {
 903             { TYPE_STREAM_SLAVE },
 904             { }
 905     }
 906 };
 907
 908 static void xilinx_enet_register_types(void)
 909 {
 910     type_register_static(&xilinx_enet_info);
 911 }
 912
 913 type_init(xilinx_enet_register_types)