virtio-net: introduce a new macaddr control
[qemu/ar7.git] / hw / qxl.c
bloba125e294aa47f17e476d7c758c2ace3400c73b52
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include <zlib.h>
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
25 #include "qemu/queue.h"
26 #include "monitor/monitor.h"
27 #include "sysemu/sysemu.h"
28 #include "trace.h"
30 #include "qxl.h"
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
36 * it may happen as a result of emulator bug as well.
38 #undef SPICE_RING_PROD_ITEM
39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
41 if (prod >= ARRAY_SIZE((r)->items)) { \
42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
44 ret = NULL; \
45 } else { \
46 ret = &(r)->items[prod].el; \
47 } \
50 #undef SPICE_RING_CONS_ITEM
51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
53 if (cons >= ARRAY_SIZE((r)->items)) { \
54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
56 ret = NULL; \
57 } else { \
58 ret = &(r)->items[cons].el; \
59 } \
62 #undef ALIGN
63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67 #define QXL_MODE(_x, _y, _b, _o) \
68 { .x_res = _x, \
69 .y_res = _y, \
70 .bits = _b, \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
74 .orientation = _o, \
77 #define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
81 #define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
83 QXL_MODE_16_32(x_res, y_res, 1)
85 static QXLMode qxl_modes[] = {
86 QXL_MODE_EX(640, 480),
87 QXL_MODE_EX(800, 480),
88 QXL_MODE_EX(800, 600),
89 QXL_MODE_EX(832, 624),
90 QXL_MODE_EX(960, 640),
91 QXL_MODE_EX(1024, 600),
92 QXL_MODE_EX(1024, 768),
93 QXL_MODE_EX(1152, 864),
94 QXL_MODE_EX(1152, 870),
95 QXL_MODE_EX(1280, 720),
96 QXL_MODE_EX(1280, 760),
97 QXL_MODE_EX(1280, 768),
98 QXL_MODE_EX(1280, 800),
99 QXL_MODE_EX(1280, 960),
100 QXL_MODE_EX(1280, 1024),
101 QXL_MODE_EX(1360, 768),
102 QXL_MODE_EX(1366, 768),
103 QXL_MODE_EX(1400, 1050),
104 QXL_MODE_EX(1440, 900),
105 QXL_MODE_EX(1600, 900),
106 QXL_MODE_EX(1600, 1200),
107 QXL_MODE_EX(1680, 1050),
108 QXL_MODE_EX(1920, 1080),
109 /* these modes need more than 8 MB video memory */
110 QXL_MODE_EX(1920, 1200),
111 QXL_MODE_EX(1920, 1440),
112 QXL_MODE_EX(2048, 1536),
113 QXL_MODE_EX(2560, 1440),
114 QXL_MODE_EX(2560, 1600),
115 /* these modes need more than 16 MB video memory */
116 QXL_MODE_EX(2560, 2048),
117 QXL_MODE_EX(2800, 2100),
118 QXL_MODE_EX(3200, 2400),
121 static PCIQXLDevice *qxl0;
123 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
124 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
125 static void qxl_reset_memslots(PCIQXLDevice *d);
126 static void qxl_reset_surfaces(PCIQXLDevice *d);
127 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
129 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
131 trace_qxl_set_guest_bug(qxl->id);
132 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
133 qxl->guest_bug = 1;
134 if (qxl->guestdebug) {
135 va_list ap;
136 va_start(ap, msg);
137 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
138 vfprintf(stderr, msg, ap);
139 fprintf(stderr, "\n");
140 va_end(ap);
144 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
146 qxl->guest_bug = 0;
149 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
150 struct QXLRect *area, struct QXLRect *dirty_rects,
151 uint32_t num_dirty_rects,
152 uint32_t clear_dirty_region,
153 qxl_async_io async, struct QXLCookie *cookie)
155 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
156 area->top, area->bottom);
157 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
158 clear_dirty_region);
159 if (async == QXL_SYNC) {
160 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
161 dirty_rects, num_dirty_rects, clear_dirty_region);
162 } else {
163 assert(cookie != NULL);
164 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
165 clear_dirty_region, (uintptr_t)cookie);
169 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
170 uint32_t id)
172 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
173 qemu_mutex_lock(&qxl->track_lock);
174 qxl->guest_surfaces.cmds[id] = 0;
175 qxl->guest_surfaces.count--;
176 qemu_mutex_unlock(&qxl->track_lock);
179 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
180 qxl_async_io async)
182 QXLCookie *cookie;
184 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
185 if (async) {
186 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
187 QXL_IO_DESTROY_SURFACE_ASYNC);
188 cookie->u.surface_id = id;
189 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
190 } else {
191 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
192 qxl_spice_destroy_surface_wait_complete(qxl, id);
196 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
198 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
199 qxl->num_free_res);
200 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
201 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
202 QXL_IO_FLUSH_SURFACES_ASYNC));
205 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
206 uint32_t count)
208 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
209 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
212 void qxl_spice_oom(PCIQXLDevice *qxl)
214 trace_qxl_spice_oom(qxl->id);
215 qxl->ssd.worker->oom(qxl->ssd.worker);
218 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
220 trace_qxl_spice_reset_memslots(qxl->id);
221 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
224 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
226 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
227 qemu_mutex_lock(&qxl->track_lock);
228 memset(qxl->guest_surfaces.cmds, 0,
229 sizeof(qxl->guest_surfaces.cmds) * qxl->ssd.num_surfaces);
230 qxl->guest_surfaces.count = 0;
231 qemu_mutex_unlock(&qxl->track_lock);
234 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
236 trace_qxl_spice_destroy_surfaces(qxl->id, async);
237 if (async) {
238 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
239 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
240 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
241 } else {
242 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
243 qxl_spice_destroy_surfaces_complete(qxl);
247 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
249 trace_qxl_spice_monitors_config(qxl->id);
250 if (replay) {
252 * don't use QXL_COOKIE_TYPE_IO:
253 * - we are not running yet (post_load), we will assert
254 * in send_events
255 * - this is not a guest io, but a reply, so async_io isn't set.
257 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
258 qxl->guest_monitors_config,
259 MEMSLOT_GROUP_GUEST,
260 (uintptr_t)qxl_cookie_new(
261 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
262 0));
263 } else {
264 qxl->guest_monitors_config = qxl->ram->monitors_config;
265 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
266 qxl->ram->monitors_config,
267 MEMSLOT_GROUP_GUEST,
268 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
269 QXL_IO_MONITORS_CONFIG_ASYNC));
273 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
275 trace_qxl_spice_reset_image_cache(qxl->id);
276 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
279 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
281 trace_qxl_spice_reset_cursor(qxl->id);
282 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
283 qemu_mutex_lock(&qxl->track_lock);
284 qxl->guest_cursor = 0;
285 qemu_mutex_unlock(&qxl->track_lock);
286 if (qxl->ssd.cursor) {
287 cursor_put(qxl->ssd.cursor);
289 qxl->ssd.cursor = cursor_builtin_hidden();
293 static inline uint32_t msb_mask(uint32_t val)
295 uint32_t mask;
297 do {
298 mask = ~(val - 1) & val;
299 val &= ~mask;
300 } while (mask < val);
302 return mask;
305 static ram_addr_t qxl_rom_size(void)
307 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
308 sizeof(qxl_modes);
309 uint32_t rom_size = 8192; /* two pages */
311 required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE);
312 required_rom_size = msb_mask(required_rom_size * 2 - 1);
313 assert(required_rom_size <= rom_size);
314 return rom_size;
317 static void init_qxl_rom(PCIQXLDevice *d)
319 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
320 QXLModes *modes = (QXLModes *)(rom + 1);
321 uint32_t ram_header_size;
322 uint32_t surface0_area_size;
323 uint32_t num_pages;
324 uint32_t fb;
325 int i, n;
327 memset(rom, 0, d->rom_size);
329 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
330 rom->id = cpu_to_le32(d->id);
331 rom->log_level = cpu_to_le32(d->guestdebug);
332 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
334 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
335 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
336 rom->slots_start = 1;
337 rom->slots_end = NUM_MEMSLOTS - 1;
338 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
340 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
341 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
342 if (fb > d->vgamem_size) {
343 continue;
345 modes->modes[n].id = cpu_to_le32(i);
346 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
347 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
348 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
349 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
350 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
351 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
352 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
353 n++;
355 modes->n_modes = cpu_to_le32(n);
357 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
358 surface0_area_size = ALIGN(d->vgamem_size, 4096);
359 num_pages = d->vga.vram_size;
360 num_pages -= ram_header_size;
361 num_pages -= surface0_area_size;
362 num_pages = num_pages / TARGET_PAGE_SIZE;
364 rom->draw_area_offset = cpu_to_le32(0);
365 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
366 rom->pages_offset = cpu_to_le32(surface0_area_size);
367 rom->num_pages = cpu_to_le32(num_pages);
368 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
370 d->shadow_rom = *rom;
371 d->rom = rom;
372 d->modes = modes;
375 static void init_qxl_ram(PCIQXLDevice *d)
377 uint8_t *buf;
378 uint64_t *item;
380 buf = d->vga.vram_ptr;
381 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
382 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
383 d->ram->int_pending = cpu_to_le32(0);
384 d->ram->int_mask = cpu_to_le32(0);
385 d->ram->update_surface = 0;
386 SPICE_RING_INIT(&d->ram->cmd_ring);
387 SPICE_RING_INIT(&d->ram->cursor_ring);
388 SPICE_RING_INIT(&d->ram->release_ring);
389 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
390 assert(item);
391 *item = 0;
392 qxl_ring_set_dirty(d);
395 /* can be called from spice server thread context */
396 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
398 memory_region_set_dirty(mr, addr, end - addr);
401 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
403 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
406 /* called from spice server thread context only */
407 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
409 void *base = qxl->vga.vram_ptr;
410 intptr_t offset;
412 offset = ptr - base;
413 offset &= ~(TARGET_PAGE_SIZE-1);
414 assert(offset < qxl->vga.vram_size);
415 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
418 /* can be called from spice server thread context */
419 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
421 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
422 ram_addr_t end = qxl->vga.vram_size;
423 qxl_set_dirty(&qxl->vga.vram, addr, end);
427 * keep track of some command state, for savevm/loadvm.
428 * called from spice server thread context only
430 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
432 switch (le32_to_cpu(ext->cmd.type)) {
433 case QXL_CMD_SURFACE:
435 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
437 if (!cmd) {
438 return 1;
440 uint32_t id = le32_to_cpu(cmd->surface_id);
442 if (id >= qxl->ssd.num_surfaces) {
443 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
444 qxl->ssd.num_surfaces);
445 return 1;
447 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
448 (cmd->u.surface_create.stride & 0x03) != 0) {
449 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
450 cmd->u.surface_create.stride);
451 return 1;
453 qemu_mutex_lock(&qxl->track_lock);
454 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
455 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
456 qxl->guest_surfaces.count++;
457 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
458 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
460 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
461 qxl->guest_surfaces.cmds[id] = 0;
462 qxl->guest_surfaces.count--;
464 qemu_mutex_unlock(&qxl->track_lock);
465 break;
467 case QXL_CMD_CURSOR:
469 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
471 if (!cmd) {
472 return 1;
474 if (cmd->type == QXL_CURSOR_SET) {
475 qemu_mutex_lock(&qxl->track_lock);
476 qxl->guest_cursor = ext->cmd.data;
477 qemu_mutex_unlock(&qxl->track_lock);
479 break;
482 return 0;
485 /* spice display interface callbacks */
487 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
489 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
491 trace_qxl_interface_attach_worker(qxl->id);
492 qxl->ssd.worker = qxl_worker;
495 static void interface_set_compression_level(QXLInstance *sin, int level)
497 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
499 trace_qxl_interface_set_compression_level(qxl->id, level);
500 qxl->shadow_rom.compression_level = cpu_to_le32(level);
501 qxl->rom->compression_level = cpu_to_le32(level);
502 qxl_rom_set_dirty(qxl);
505 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
507 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
509 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
510 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
511 qxl->rom->mm_clock = cpu_to_le32(mm_time);
512 qxl_rom_set_dirty(qxl);
515 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
517 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
519 trace_qxl_interface_get_init_info(qxl->id);
520 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
521 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
522 info->num_memslots = NUM_MEMSLOTS;
523 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
524 info->internal_groupslot_id = 0;
525 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
526 info->n_surfaces = qxl->ssd.num_surfaces;
529 static const char *qxl_mode_to_string(int mode)
531 switch (mode) {
532 case QXL_MODE_COMPAT:
533 return "compat";
534 case QXL_MODE_NATIVE:
535 return "native";
536 case QXL_MODE_UNDEFINED:
537 return "undefined";
538 case QXL_MODE_VGA:
539 return "vga";
541 return "INVALID";
544 static const char *io_port_to_string(uint32_t io_port)
546 if (io_port >= QXL_IO_RANGE_SIZE) {
547 return "out of range";
549 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
550 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
551 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
552 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
553 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
554 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
555 [QXL_IO_RESET] = "QXL_IO_RESET",
556 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
557 [QXL_IO_LOG] = "QXL_IO_LOG",
558 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
559 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
560 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
561 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
562 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
563 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
564 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
565 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
566 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
567 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
568 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
569 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
570 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
571 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
572 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
573 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
574 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
575 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
577 return io_port_to_string[io_port];
580 /* called from spice server thread context only */
581 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
583 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
584 SimpleSpiceUpdate *update;
585 QXLCommandRing *ring;
586 QXLCommand *cmd;
587 int notify, ret;
589 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
591 switch (qxl->mode) {
592 case QXL_MODE_VGA:
593 ret = false;
594 qemu_mutex_lock(&qxl->ssd.lock);
595 update = QTAILQ_FIRST(&qxl->ssd.updates);
596 if (update != NULL) {
597 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
598 *ext = update->ext;
599 ret = true;
601 qemu_mutex_unlock(&qxl->ssd.lock);
602 if (ret) {
603 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
604 qxl_log_command(qxl, "vga", ext);
606 return ret;
607 case QXL_MODE_COMPAT:
608 case QXL_MODE_NATIVE:
609 case QXL_MODE_UNDEFINED:
610 ring = &qxl->ram->cmd_ring;
611 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
612 return false;
614 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
615 if (!cmd) {
616 return false;
618 ext->cmd = *cmd;
619 ext->group_id = MEMSLOT_GROUP_GUEST;
620 ext->flags = qxl->cmdflags;
621 SPICE_RING_POP(ring, notify);
622 qxl_ring_set_dirty(qxl);
623 if (notify) {
624 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
626 qxl->guest_primary.commands++;
627 qxl_track_command(qxl, ext);
628 qxl_log_command(qxl, "cmd", ext);
629 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
630 return true;
631 default:
632 return false;
636 /* called from spice server thread context only */
637 static int interface_req_cmd_notification(QXLInstance *sin)
639 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
640 int wait = 1;
642 trace_qxl_ring_command_req_notification(qxl->id);
643 switch (qxl->mode) {
644 case QXL_MODE_COMPAT:
645 case QXL_MODE_NATIVE:
646 case QXL_MODE_UNDEFINED:
647 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
648 qxl_ring_set_dirty(qxl);
649 break;
650 default:
651 /* nothing */
652 break;
654 return wait;
657 /* called from spice server thread context only */
658 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
660 QXLReleaseRing *ring = &d->ram->release_ring;
661 uint64_t *item;
662 int notify;
664 #define QXL_FREE_BUNCH_SIZE 32
666 if (ring->prod - ring->cons + 1 == ring->num_items) {
667 /* ring full -- can't push */
668 return;
670 if (!flush && d->oom_running) {
671 /* collect everything from oom handler before pushing */
672 return;
674 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
675 /* collect a bit more before pushing */
676 return;
679 SPICE_RING_PUSH(ring, notify);
680 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
681 d->guest_surfaces.count, d->num_free_res,
682 d->last_release, notify ? "yes" : "no");
683 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
684 ring->num_items, ring->prod, ring->cons);
685 if (notify) {
686 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
688 SPICE_RING_PROD_ITEM(d, ring, item);
689 if (!item) {
690 return;
692 *item = 0;
693 d->num_free_res = 0;
694 d->last_release = NULL;
695 qxl_ring_set_dirty(d);
698 /* called from spice server thread context only */
699 static void interface_release_resource(QXLInstance *sin,
700 struct QXLReleaseInfoExt ext)
702 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
703 QXLReleaseRing *ring;
704 uint64_t *item, id;
706 if (ext.group_id == MEMSLOT_GROUP_HOST) {
707 /* host group -> vga mode update request */
708 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
709 return;
713 * ext->info points into guest-visible memory
714 * pci bar 0, $command.release_info
716 ring = &qxl->ram->release_ring;
717 SPICE_RING_PROD_ITEM(qxl, ring, item);
718 if (!item) {
719 return;
721 if (*item == 0) {
722 /* stick head into the ring */
723 id = ext.info->id;
724 ext.info->next = 0;
725 qxl_ram_set_dirty(qxl, &ext.info->next);
726 *item = id;
727 qxl_ring_set_dirty(qxl);
728 } else {
729 /* append item to the list */
730 qxl->last_release->next = ext.info->id;
731 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
732 ext.info->next = 0;
733 qxl_ram_set_dirty(qxl, &ext.info->next);
735 qxl->last_release = ext.info;
736 qxl->num_free_res++;
737 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
738 qxl_push_free_res(qxl, 0);
741 /* called from spice server thread context only */
742 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
744 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
745 QXLCursorRing *ring;
746 QXLCommand *cmd;
747 int notify;
749 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
751 switch (qxl->mode) {
752 case QXL_MODE_COMPAT:
753 case QXL_MODE_NATIVE:
754 case QXL_MODE_UNDEFINED:
755 ring = &qxl->ram->cursor_ring;
756 if (SPICE_RING_IS_EMPTY(ring)) {
757 return false;
759 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
760 if (!cmd) {
761 return false;
763 ext->cmd = *cmd;
764 ext->group_id = MEMSLOT_GROUP_GUEST;
765 ext->flags = qxl->cmdflags;
766 SPICE_RING_POP(ring, notify);
767 qxl_ring_set_dirty(qxl);
768 if (notify) {
769 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
771 qxl->guest_primary.commands++;
772 qxl_track_command(qxl, ext);
773 qxl_log_command(qxl, "csr", ext);
774 if (qxl->id == 0) {
775 qxl_render_cursor(qxl, ext);
777 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
778 return true;
779 default:
780 return false;
784 /* called from spice server thread context only */
785 static int interface_req_cursor_notification(QXLInstance *sin)
787 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
788 int wait = 1;
790 trace_qxl_ring_cursor_req_notification(qxl->id);
791 switch (qxl->mode) {
792 case QXL_MODE_COMPAT:
793 case QXL_MODE_NATIVE:
794 case QXL_MODE_UNDEFINED:
795 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
796 qxl_ring_set_dirty(qxl);
797 break;
798 default:
799 /* nothing */
800 break;
802 return wait;
805 /* called from spice server thread context */
806 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
809 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
810 * use by xf86-video-qxl and is defined out in the qxl windows driver.
811 * Probably was at some earlier version that is prior to git start (2009),
812 * and is still guest trigerrable.
814 fprintf(stderr, "%s: deprecated\n", __func__);
817 /* called from spice server thread context only */
818 static int interface_flush_resources(QXLInstance *sin)
820 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
821 int ret;
823 ret = qxl->num_free_res;
824 if (ret) {
825 qxl_push_free_res(qxl, 1);
827 return ret;
830 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
832 /* called from spice server thread context only */
833 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
835 uint32_t current_async;
837 qemu_mutex_lock(&qxl->async_lock);
838 current_async = qxl->current_async;
839 qxl->current_async = QXL_UNDEFINED_IO;
840 qemu_mutex_unlock(&qxl->async_lock);
842 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
843 if (!cookie) {
844 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
845 return;
847 if (cookie && current_async != cookie->io) {
848 fprintf(stderr,
849 "qxl: %s: error: current_async = %d != %"
850 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
852 switch (current_async) {
853 case QXL_IO_MEMSLOT_ADD_ASYNC:
854 case QXL_IO_DESTROY_PRIMARY_ASYNC:
855 case QXL_IO_UPDATE_AREA_ASYNC:
856 case QXL_IO_FLUSH_SURFACES_ASYNC:
857 case QXL_IO_MONITORS_CONFIG_ASYNC:
858 break;
859 case QXL_IO_CREATE_PRIMARY_ASYNC:
860 qxl_create_guest_primary_complete(qxl);
861 break;
862 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
863 qxl_spice_destroy_surfaces_complete(qxl);
864 break;
865 case QXL_IO_DESTROY_SURFACE_ASYNC:
866 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
867 break;
868 default:
869 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
870 current_async);
872 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
875 /* called from spice server thread context only */
876 static void interface_update_area_complete(QXLInstance *sin,
877 uint32_t surface_id,
878 QXLRect *dirty, uint32_t num_updated_rects)
880 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
881 int i;
882 int qxl_i;
884 qemu_mutex_lock(&qxl->ssd.lock);
885 if (surface_id != 0 || !qxl->render_update_cookie_num) {
886 qemu_mutex_unlock(&qxl->ssd.lock);
887 return;
889 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
890 dirty->right, dirty->top, dirty->bottom);
891 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
892 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
894 * overflow - treat this as a full update. Not expected to be common.
896 trace_qxl_interface_update_area_complete_overflow(qxl->id,
897 QXL_NUM_DIRTY_RECTS);
898 qxl->guest_primary.resized = 1;
900 if (qxl->guest_primary.resized) {
902 * Don't bother copying or scheduling the bh since we will flip
903 * the whole area anyway on completion of the update_area async call
905 qemu_mutex_unlock(&qxl->ssd.lock);
906 return;
908 qxl_i = qxl->num_dirty_rects;
909 for (i = 0; i < num_updated_rects; i++) {
910 qxl->dirty[qxl_i++] = dirty[i];
912 qxl->num_dirty_rects += num_updated_rects;
913 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
914 qxl->num_dirty_rects);
915 qemu_bh_schedule(qxl->update_area_bh);
916 qemu_mutex_unlock(&qxl->ssd.lock);
919 /* called from spice server thread context only */
920 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
922 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
923 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
925 switch (cookie->type) {
926 case QXL_COOKIE_TYPE_IO:
927 interface_async_complete_io(qxl, cookie);
928 g_free(cookie);
929 break;
930 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
931 qxl_render_update_area_done(qxl, cookie);
932 break;
933 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
934 break;
935 default:
936 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
937 __func__, cookie->type);
938 g_free(cookie);
942 /* called from spice server thread context only */
943 static void interface_set_client_capabilities(QXLInstance *sin,
944 uint8_t client_present,
945 uint8_t caps[58])
947 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
949 if (qxl->revision < 4) {
950 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
951 qxl->revision);
952 return;
955 if (runstate_check(RUN_STATE_INMIGRATE) ||
956 runstate_check(RUN_STATE_POSTMIGRATE)) {
957 return;
960 qxl->shadow_rom.client_present = client_present;
961 memcpy(qxl->shadow_rom.client_capabilities, caps,
962 sizeof(qxl->shadow_rom.client_capabilities));
963 qxl->rom->client_present = client_present;
964 memcpy(qxl->rom->client_capabilities, caps,
965 sizeof(qxl->rom->client_capabilities));
966 qxl_rom_set_dirty(qxl);
968 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
971 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
974 * zlib xors the seed with 0xffffffff, and xors the result
975 * again with 0xffffffff; Both are not done with linux's crc32,
976 * which we want to be compatible with, so undo that.
978 return crc32(0xffffffff, p, len) ^ 0xffffffff;
981 /* called from main context only */
982 static int interface_client_monitors_config(QXLInstance *sin,
983 VDAgentMonitorsConfig *monitors_config)
985 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
986 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
987 int i;
989 if (qxl->revision < 4) {
990 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
991 qxl->revision);
992 return 0;
995 * Older windows drivers set int_mask to 0 when their ISR is called,
996 * then later set it to ~0. So it doesn't relate to the actual interrupts
997 * handled. However, they are old, so clearly they don't support this
998 * interrupt
1000 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1001 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1002 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1003 qxl->ram->int_mask,
1004 monitors_config);
1005 return 0;
1007 if (!monitors_config) {
1008 return 1;
1010 memset(&rom->client_monitors_config, 0,
1011 sizeof(rom->client_monitors_config));
1012 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1013 /* monitors_config->flags ignored */
1014 if (rom->client_monitors_config.count >=
1015 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1016 trace_qxl_client_monitors_config_capped(qxl->id,
1017 monitors_config->num_of_monitors,
1018 ARRAY_SIZE(rom->client_monitors_config.heads));
1019 rom->client_monitors_config.count =
1020 ARRAY_SIZE(rom->client_monitors_config.heads);
1022 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1023 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1024 QXLURect *rect = &rom->client_monitors_config.heads[i];
1025 /* monitor->depth ignored */
1026 rect->left = monitor->x;
1027 rect->top = monitor->y;
1028 rect->right = monitor->x + monitor->width;
1029 rect->bottom = monitor->y + monitor->height;
1031 rom->client_monitors_config_crc = qxl_crc32(
1032 (const uint8_t *)&rom->client_monitors_config,
1033 sizeof(rom->client_monitors_config));
1034 trace_qxl_client_monitors_config_crc(qxl->id,
1035 sizeof(rom->client_monitors_config),
1036 rom->client_monitors_config_crc);
1038 trace_qxl_interrupt_client_monitors_config(qxl->id,
1039 rom->client_monitors_config.count,
1040 rom->client_monitors_config.heads);
1041 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1042 return 1;
1045 static const QXLInterface qxl_interface = {
1046 .base.type = SPICE_INTERFACE_QXL,
1047 .base.description = "qxl gpu",
1048 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1049 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1051 .attache_worker = interface_attach_worker,
1052 .set_compression_level = interface_set_compression_level,
1053 .set_mm_time = interface_set_mm_time,
1054 .get_init_info = interface_get_init_info,
1056 /* the callbacks below are called from spice server thread context */
1057 .get_command = interface_get_command,
1058 .req_cmd_notification = interface_req_cmd_notification,
1059 .release_resource = interface_release_resource,
1060 .get_cursor_command = interface_get_cursor_command,
1061 .req_cursor_notification = interface_req_cursor_notification,
1062 .notify_update = interface_notify_update,
1063 .flush_resources = interface_flush_resources,
1064 .async_complete = interface_async_complete,
1065 .update_area_complete = interface_update_area_complete,
1066 .set_client_capabilities = interface_set_client_capabilities,
1067 .client_monitors_config = interface_client_monitors_config,
1070 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1072 if (d->mode == QXL_MODE_VGA) {
1073 return;
1075 trace_qxl_enter_vga_mode(d->id);
1076 qemu_spice_create_host_primary(&d->ssd);
1077 d->mode = QXL_MODE_VGA;
1078 dpy_gfx_resize(d->ssd.ds);
1079 vga_dirty_log_start(&d->vga);
1082 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1084 if (d->mode != QXL_MODE_VGA) {
1085 return;
1087 trace_qxl_exit_vga_mode(d->id);
1088 vga_dirty_log_stop(&d->vga);
1089 qxl_destroy_primary(d, QXL_SYNC);
1092 static void qxl_update_irq(PCIQXLDevice *d)
1094 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1095 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1096 int level = !!(pending & mask);
1097 qemu_set_irq(d->pci.irq[0], level);
1098 qxl_ring_set_dirty(d);
1101 static void qxl_check_state(PCIQXLDevice *d)
1103 QXLRam *ram = d->ram;
1104 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1106 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1107 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1110 static void qxl_reset_state(PCIQXLDevice *d)
1112 QXLRom *rom = d->rom;
1114 qxl_check_state(d);
1115 d->shadow_rom.update_id = cpu_to_le32(0);
1116 *rom = d->shadow_rom;
1117 qxl_rom_set_dirty(d);
1118 init_qxl_ram(d);
1119 d->num_free_res = 0;
1120 d->last_release = NULL;
1121 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1124 static void qxl_soft_reset(PCIQXLDevice *d)
1126 trace_qxl_soft_reset(d->id);
1127 qxl_check_state(d);
1128 qxl_clear_guest_bug(d);
1129 d->current_async = QXL_UNDEFINED_IO;
1131 if (d->id == 0) {
1132 qxl_enter_vga_mode(d);
1133 } else {
1134 d->mode = QXL_MODE_UNDEFINED;
1138 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1140 trace_qxl_hard_reset(d->id, loadvm);
1142 qxl_spice_reset_cursor(d);
1143 qxl_spice_reset_image_cache(d);
1144 qxl_reset_surfaces(d);
1145 qxl_reset_memslots(d);
1147 /* pre loadvm reset must not touch QXLRam. This lives in
1148 * device memory, is migrated together with RAM and thus
1149 * already loaded at this point */
1150 if (!loadvm) {
1151 qxl_reset_state(d);
1153 qemu_spice_create_host_memslot(&d->ssd);
1154 qxl_soft_reset(d);
1157 static void qxl_reset_handler(DeviceState *dev)
1159 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
1161 qxl_hard_reset(d, 0);
1164 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1166 VGACommonState *vga = opaque;
1167 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1169 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1170 if (qxl->mode != QXL_MODE_VGA) {
1171 qxl_destroy_primary(qxl, QXL_SYNC);
1172 qxl_soft_reset(qxl);
1174 vga_ioport_write(opaque, addr, val);
1177 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1178 { 0x04, 2, 1, .read = vga_ioport_read,
1179 .write = qxl_vga_ioport_write }, /* 3b4 */
1180 { 0x0a, 1, 1, .read = vga_ioport_read,
1181 .write = qxl_vga_ioport_write }, /* 3ba */
1182 { 0x10, 16, 1, .read = vga_ioport_read,
1183 .write = qxl_vga_ioport_write }, /* 3c0 */
1184 { 0x24, 2, 1, .read = vga_ioport_read,
1185 .write = qxl_vga_ioport_write }, /* 3d4 */
1186 { 0x2a, 1, 1, .read = vga_ioport_read,
1187 .write = qxl_vga_ioport_write }, /* 3da */
1188 PORTIO_END_OF_LIST(),
1191 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1192 qxl_async_io async)
1194 static const int regions[] = {
1195 QXL_RAM_RANGE_INDEX,
1196 QXL_VRAM_RANGE_INDEX,
1197 QXL_VRAM64_RANGE_INDEX,
1199 uint64_t guest_start;
1200 uint64_t guest_end;
1201 int pci_region;
1202 pcibus_t pci_start;
1203 pcibus_t pci_end;
1204 intptr_t virt_start;
1205 QXLDevMemSlot memslot;
1206 int i;
1208 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1209 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1211 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1213 if (slot_id >= NUM_MEMSLOTS) {
1214 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1215 slot_id, NUM_MEMSLOTS);
1216 return 1;
1218 if (guest_start > guest_end) {
1219 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1220 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1221 return 1;
1224 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1225 pci_region = regions[i];
1226 pci_start = d->pci.io_regions[pci_region].addr;
1227 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1228 /* mapped? */
1229 if (pci_start == -1) {
1230 continue;
1232 /* start address in range ? */
1233 if (guest_start < pci_start || guest_start > pci_end) {
1234 continue;
1236 /* end address in range ? */
1237 if (guest_end > pci_end) {
1238 continue;
1240 /* passed */
1241 break;
1243 if (i == ARRAY_SIZE(regions)) {
1244 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1245 return 1;
1248 switch (pci_region) {
1249 case QXL_RAM_RANGE_INDEX:
1250 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1251 break;
1252 case QXL_VRAM_RANGE_INDEX:
1253 case 4 /* vram 64bit */:
1254 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1255 break;
1256 default:
1257 /* should not happen */
1258 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1259 return 1;
1262 memslot.slot_id = slot_id;
1263 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1264 memslot.virt_start = virt_start + (guest_start - pci_start);
1265 memslot.virt_end = virt_start + (guest_end - pci_start);
1266 memslot.addr_delta = memslot.virt_start - delta;
1267 memslot.generation = d->rom->slot_generation = 0;
1268 qxl_rom_set_dirty(d);
1270 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1271 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1272 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1273 d->guest_slots[slot_id].delta = delta;
1274 d->guest_slots[slot_id].active = 1;
1275 return 0;
1278 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1280 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1281 d->guest_slots[slot_id].active = 0;
1284 static void qxl_reset_memslots(PCIQXLDevice *d)
1286 qxl_spice_reset_memslots(d);
1287 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1290 static void qxl_reset_surfaces(PCIQXLDevice *d)
1292 trace_qxl_reset_surfaces(d->id);
1293 d->mode = QXL_MODE_UNDEFINED;
1294 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1297 /* can be also called from spice server thread context */
1298 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1300 uint64_t phys = le64_to_cpu(pqxl);
1301 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1302 uint64_t offset = phys & 0xffffffffffff;
1304 switch (group_id) {
1305 case MEMSLOT_GROUP_HOST:
1306 return (void *)(intptr_t)offset;
1307 case MEMSLOT_GROUP_GUEST:
1308 if (slot >= NUM_MEMSLOTS) {
1309 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1310 NUM_MEMSLOTS);
1311 return NULL;
1313 if (!qxl->guest_slots[slot].active) {
1314 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1315 return NULL;
1317 if (offset < qxl->guest_slots[slot].delta) {
1318 qxl_set_guest_bug(qxl,
1319 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1320 slot, offset, qxl->guest_slots[slot].delta);
1321 return NULL;
1323 offset -= qxl->guest_slots[slot].delta;
1324 if (offset > qxl->guest_slots[slot].size) {
1325 qxl_set_guest_bug(qxl,
1326 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1327 slot, offset, qxl->guest_slots[slot].size);
1328 return NULL;
1330 return qxl->guest_slots[slot].ptr + offset;
1332 return NULL;
1335 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1337 /* for local rendering */
1338 qxl_render_resize(qxl);
1341 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1342 qxl_async_io async)
1344 QXLDevSurfaceCreate surface;
1345 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1346 int size;
1347 int requested_height = le32_to_cpu(sc->height);
1348 int requested_stride = le32_to_cpu(sc->stride);
1350 size = abs(requested_stride) * requested_height;
1351 if (size > qxl->vgamem_size) {
1352 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1353 " size", __func__);
1354 return;
1357 if (qxl->mode == QXL_MODE_NATIVE) {
1358 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1359 __func__);
1361 qxl_exit_vga_mode(qxl);
1363 surface.format = le32_to_cpu(sc->format);
1364 surface.height = le32_to_cpu(sc->height);
1365 surface.mem = le64_to_cpu(sc->mem);
1366 surface.position = le32_to_cpu(sc->position);
1367 surface.stride = le32_to_cpu(sc->stride);
1368 surface.width = le32_to_cpu(sc->width);
1369 surface.type = le32_to_cpu(sc->type);
1370 surface.flags = le32_to_cpu(sc->flags);
1371 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1372 sc->format, sc->position);
1373 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1374 sc->flags);
1376 if ((surface.stride & 0x3) != 0) {
1377 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1378 surface.stride);
1379 return;
1382 surface.mouse_mode = true;
1383 surface.group_id = MEMSLOT_GROUP_GUEST;
1384 if (loadvm) {
1385 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1388 qxl->mode = QXL_MODE_NATIVE;
1389 qxl->cmdflags = 0;
1390 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1392 if (async == QXL_SYNC) {
1393 qxl_create_guest_primary_complete(qxl);
1397 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1398 * done (in QXL_SYNC case), 0 otherwise. */
1399 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1401 if (d->mode == QXL_MODE_UNDEFINED) {
1402 return 0;
1404 trace_qxl_destroy_primary(d->id);
1405 d->mode = QXL_MODE_UNDEFINED;
1406 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1407 qxl_spice_reset_cursor(d);
1408 return 1;
1411 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1413 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1414 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1415 QXLMode *mode = d->modes->modes + modenr;
1416 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1417 QXLMemSlot slot = {
1418 .mem_start = start,
1419 .mem_end = end
1421 QXLSurfaceCreate surface = {
1422 .width = mode->x_res,
1423 .height = mode->y_res,
1424 .stride = -mode->x_res * 4,
1425 .format = SPICE_SURFACE_FMT_32_xRGB,
1426 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1427 .mouse_mode = true,
1428 .mem = devmem + d->shadow_rom.draw_area_offset,
1431 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1432 devmem);
1433 if (!loadvm) {
1434 qxl_hard_reset(d, 0);
1437 d->guest_slots[0].slot = slot;
1438 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1440 d->guest_primary.surface = surface;
1441 qxl_create_guest_primary(d, 0, QXL_SYNC);
1443 d->mode = QXL_MODE_COMPAT;
1444 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1445 if (mode->bits == 16) {
1446 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1448 d->shadow_rom.mode = cpu_to_le32(modenr);
1449 d->rom->mode = cpu_to_le32(modenr);
1450 qxl_rom_set_dirty(d);
1453 static void ioport_write(void *opaque, hwaddr addr,
1454 uint64_t val, unsigned size)
1456 PCIQXLDevice *d = opaque;
1457 uint32_t io_port = addr;
1458 qxl_async_io async = QXL_SYNC;
1459 uint32_t orig_io_port = io_port;
1461 if (d->guest_bug && io_port != QXL_IO_RESET) {
1462 return;
1465 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1466 io_port > QXL_IO_FLUSH_RELEASE) {
1467 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1468 io_port, d->revision);
1469 return;
1472 switch (io_port) {
1473 case QXL_IO_RESET:
1474 case QXL_IO_SET_MODE:
1475 case QXL_IO_MEMSLOT_ADD:
1476 case QXL_IO_MEMSLOT_DEL:
1477 case QXL_IO_CREATE_PRIMARY:
1478 case QXL_IO_UPDATE_IRQ:
1479 case QXL_IO_LOG:
1480 case QXL_IO_MEMSLOT_ADD_ASYNC:
1481 case QXL_IO_CREATE_PRIMARY_ASYNC:
1482 break;
1483 default:
1484 if (d->mode != QXL_MODE_VGA) {
1485 break;
1487 trace_qxl_io_unexpected_vga_mode(d->id,
1488 addr, val, io_port_to_string(io_port));
1489 /* be nice to buggy guest drivers */
1490 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1491 io_port < QXL_IO_RANGE_SIZE) {
1492 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1494 return;
1497 /* we change the io_port to avoid ifdeffery in the main switch */
1498 orig_io_port = io_port;
1499 switch (io_port) {
1500 case QXL_IO_UPDATE_AREA_ASYNC:
1501 io_port = QXL_IO_UPDATE_AREA;
1502 goto async_common;
1503 case QXL_IO_MEMSLOT_ADD_ASYNC:
1504 io_port = QXL_IO_MEMSLOT_ADD;
1505 goto async_common;
1506 case QXL_IO_CREATE_PRIMARY_ASYNC:
1507 io_port = QXL_IO_CREATE_PRIMARY;
1508 goto async_common;
1509 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1510 io_port = QXL_IO_DESTROY_PRIMARY;
1511 goto async_common;
1512 case QXL_IO_DESTROY_SURFACE_ASYNC:
1513 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1514 goto async_common;
1515 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1516 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1517 goto async_common;
1518 case QXL_IO_FLUSH_SURFACES_ASYNC:
1519 case QXL_IO_MONITORS_CONFIG_ASYNC:
1520 async_common:
1521 async = QXL_ASYNC;
1522 qemu_mutex_lock(&d->async_lock);
1523 if (d->current_async != QXL_UNDEFINED_IO) {
1524 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1525 io_port, d->current_async);
1526 qemu_mutex_unlock(&d->async_lock);
1527 return;
1529 d->current_async = orig_io_port;
1530 qemu_mutex_unlock(&d->async_lock);
1531 break;
1532 default:
1533 break;
1535 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1536 async);
1538 switch (io_port) {
1539 case QXL_IO_UPDATE_AREA:
1541 QXLCookie *cookie = NULL;
1542 QXLRect update = d->ram->update_area;
1544 if (d->ram->update_surface > d->ssd.num_surfaces) {
1545 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1546 d->ram->update_surface);
1547 break;
1549 if (update.left >= update.right || update.top >= update.bottom ||
1550 update.left < 0 || update.top < 0) {
1551 qxl_set_guest_bug(d,
1552 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1553 update.left, update.top, update.right, update.bottom);
1554 break;
1556 if (async == QXL_ASYNC) {
1557 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1558 QXL_IO_UPDATE_AREA_ASYNC);
1559 cookie->u.area = update;
1561 qxl_spice_update_area(d, d->ram->update_surface,
1562 cookie ? &cookie->u.area : &update,
1563 NULL, 0, 0, async, cookie);
1564 break;
1566 case QXL_IO_NOTIFY_CMD:
1567 qemu_spice_wakeup(&d->ssd);
1568 break;
1569 case QXL_IO_NOTIFY_CURSOR:
1570 qemu_spice_wakeup(&d->ssd);
1571 break;
1572 case QXL_IO_UPDATE_IRQ:
1573 qxl_update_irq(d);
1574 break;
1575 case QXL_IO_NOTIFY_OOM:
1576 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1577 break;
1579 d->oom_running = 1;
1580 qxl_spice_oom(d);
1581 d->oom_running = 0;
1582 break;
1583 case QXL_IO_SET_MODE:
1584 qxl_set_mode(d, val, 0);
1585 break;
1586 case QXL_IO_LOG:
1587 trace_qxl_io_log(d->id, d->ram->log_buf);
1588 if (d->guestdebug) {
1589 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1590 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1592 break;
1593 case QXL_IO_RESET:
1594 qxl_hard_reset(d, 0);
1595 break;
1596 case QXL_IO_MEMSLOT_ADD:
1597 if (val >= NUM_MEMSLOTS) {
1598 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1599 break;
1601 if (d->guest_slots[val].active) {
1602 qxl_set_guest_bug(d,
1603 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1604 break;
1606 d->guest_slots[val].slot = d->ram->mem_slot;
1607 qxl_add_memslot(d, val, 0, async);
1608 break;
1609 case QXL_IO_MEMSLOT_DEL:
1610 if (val >= NUM_MEMSLOTS) {
1611 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1612 break;
1614 qxl_del_memslot(d, val);
1615 break;
1616 case QXL_IO_CREATE_PRIMARY:
1617 if (val != 0) {
1618 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1619 async);
1620 goto cancel_async;
1622 d->guest_primary.surface = d->ram->create_surface;
1623 qxl_create_guest_primary(d, 0, async);
1624 break;
1625 case QXL_IO_DESTROY_PRIMARY:
1626 if (val != 0) {
1627 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1628 async);
1629 goto cancel_async;
1631 if (!qxl_destroy_primary(d, async)) {
1632 trace_qxl_io_destroy_primary_ignored(d->id,
1633 qxl_mode_to_string(d->mode));
1634 goto cancel_async;
1636 break;
1637 case QXL_IO_DESTROY_SURFACE_WAIT:
1638 if (val >= d->ssd.num_surfaces) {
1639 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1640 "%" PRIu64 " >= NUM_SURFACES", async, val);
1641 goto cancel_async;
1643 qxl_spice_destroy_surface_wait(d, val, async);
1644 break;
1645 case QXL_IO_FLUSH_RELEASE: {
1646 QXLReleaseRing *ring = &d->ram->release_ring;
1647 if (ring->prod - ring->cons + 1 == ring->num_items) {
1648 fprintf(stderr,
1649 "ERROR: no flush, full release ring [p%d,%dc]\n",
1650 ring->prod, ring->cons);
1652 qxl_push_free_res(d, 1 /* flush */);
1653 break;
1655 case QXL_IO_FLUSH_SURFACES_ASYNC:
1656 qxl_spice_flush_surfaces_async(d);
1657 break;
1658 case QXL_IO_DESTROY_ALL_SURFACES:
1659 d->mode = QXL_MODE_UNDEFINED;
1660 qxl_spice_destroy_surfaces(d, async);
1661 break;
1662 case QXL_IO_MONITORS_CONFIG_ASYNC:
1663 qxl_spice_monitors_config_async(d, 0);
1664 break;
1665 default:
1666 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1668 return;
1669 cancel_async:
1670 if (async) {
1671 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1672 qemu_mutex_lock(&d->async_lock);
1673 d->current_async = QXL_UNDEFINED_IO;
1674 qemu_mutex_unlock(&d->async_lock);
1678 static uint64_t ioport_read(void *opaque, hwaddr addr,
1679 unsigned size)
1681 PCIQXLDevice *qxl = opaque;
1683 trace_qxl_io_read_unexpected(qxl->id);
1684 return 0xff;
1687 static const MemoryRegionOps qxl_io_ops = {
1688 .read = ioport_read,
1689 .write = ioport_write,
1690 .valid = {
1691 .min_access_size = 1,
1692 .max_access_size = 1,
1696 static void pipe_read(void *opaque)
1698 PCIQXLDevice *d = opaque;
1699 char dummy;
1700 int len;
1702 do {
1703 len = read(d->pipe[0], &dummy, sizeof(dummy));
1704 } while (len == sizeof(dummy));
1705 qxl_update_irq(d);
1708 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1710 uint32_t old_pending;
1711 uint32_t le_events = cpu_to_le32(events);
1713 trace_qxl_send_events(d->id, events);
1714 if (!qemu_spice_display_is_running(&d->ssd)) {
1715 /* spice-server tracks guest running state and should not do this */
1716 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1717 __func__);
1718 trace_qxl_send_events_vm_stopped(d->id, events);
1719 return;
1721 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1722 if ((old_pending & le_events) == le_events) {
1723 return;
1725 if (qemu_thread_is_self(&d->main)) {
1726 qxl_update_irq(d);
1727 } else {
1728 if (write(d->pipe[1], d, 1) != 1) {
1729 dprint(d, 1, "%s: write to pipe failed\n", __func__);
1734 static void init_pipe_signaling(PCIQXLDevice *d)
1736 if (pipe(d->pipe) < 0) {
1737 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1738 __FILE__, __func__);
1739 exit(1);
1741 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1742 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1743 fcntl(d->pipe[0], F_SETOWN, getpid());
1745 qemu_thread_get_self(&d->main);
1746 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1749 /* graphics console */
1751 static void qxl_hw_update(void *opaque)
1753 PCIQXLDevice *qxl = opaque;
1754 VGACommonState *vga = &qxl->vga;
1756 switch (qxl->mode) {
1757 case QXL_MODE_VGA:
1758 vga->update(vga);
1759 break;
1760 case QXL_MODE_COMPAT:
1761 case QXL_MODE_NATIVE:
1762 qxl_render_update(qxl);
1763 break;
1764 default:
1765 break;
1769 static void qxl_hw_invalidate(void *opaque)
1771 PCIQXLDevice *qxl = opaque;
1772 VGACommonState *vga = &qxl->vga;
1774 vga->invalidate(vga);
1777 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch,
1778 Error **errp)
1780 PCIQXLDevice *qxl = opaque;
1781 VGACommonState *vga = &qxl->vga;
1783 switch (qxl->mode) {
1784 case QXL_MODE_COMPAT:
1785 case QXL_MODE_NATIVE:
1786 qxl_render_update(qxl);
1787 ppm_save(filename, qxl->ssd.ds->surface, errp);
1788 break;
1789 case QXL_MODE_VGA:
1790 vga->screen_dump(vga, filename, cswitch, errp);
1791 break;
1792 default:
1793 break;
1797 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1799 PCIQXLDevice *qxl = opaque;
1800 VGACommonState *vga = &qxl->vga;
1802 if (qxl->mode == QXL_MODE_VGA) {
1803 vga->text_update(vga, chardata);
1804 return;
1808 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1810 uintptr_t vram_start;
1811 int i;
1813 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1814 return;
1817 /* dirty the primary surface */
1818 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1819 qxl->shadow_rom.surface0_area_size);
1821 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1823 /* dirty the off-screen surfaces */
1824 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1825 QXLSurfaceCmd *cmd;
1826 intptr_t surface_offset;
1827 int surface_size;
1829 if (qxl->guest_surfaces.cmds[i] == 0) {
1830 continue;
1833 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1834 MEMSLOT_GROUP_GUEST);
1835 assert(cmd);
1836 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1837 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1838 cmd->u.surface_create.data,
1839 MEMSLOT_GROUP_GUEST);
1840 assert(surface_offset);
1841 surface_offset -= vram_start;
1842 surface_size = cmd->u.surface_create.height *
1843 abs(cmd->u.surface_create.stride);
1844 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1845 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1849 static void qxl_vm_change_state_handler(void *opaque, int running,
1850 RunState state)
1852 PCIQXLDevice *qxl = opaque;
1854 if (running) {
1856 * if qxl_send_events was called from spice server context before
1857 * migration ended, qxl_update_irq for these events might not have been
1858 * called
1860 qxl_update_irq(qxl);
1861 } else {
1862 /* make sure surfaces are saved before migration */
1863 qxl_dirty_surfaces(qxl);
1867 /* display change listener */
1869 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1871 if (qxl0->mode == QXL_MODE_VGA) {
1872 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1876 static void display_resize(struct DisplayState *ds)
1878 if (qxl0->mode == QXL_MODE_VGA) {
1879 qemu_spice_display_resize(&qxl0->ssd);
1883 static void display_refresh(struct DisplayState *ds)
1885 if (qxl0->mode == QXL_MODE_VGA) {
1886 qemu_spice_display_refresh(&qxl0->ssd);
1887 } else {
1888 qemu_mutex_lock(&qxl0->ssd.lock);
1889 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1890 qemu_mutex_unlock(&qxl0->ssd.lock);
1894 static DisplayChangeListener display_listener = {
1895 .dpy_gfx_update = display_update,
1896 .dpy_gfx_resize = display_resize,
1897 .dpy_refresh = display_refresh,
1900 static void qxl_init_ramsize(PCIQXLDevice *qxl)
1902 /* vga mode framebuffer / primary surface (bar 0, first part) */
1903 if (qxl->vgamem_size_mb < 8) {
1904 qxl->vgamem_size_mb = 8;
1906 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1908 /* vga ram (bar 0, total) */
1909 if (qxl->ram_size_mb != -1) {
1910 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1912 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1913 qxl->vga.vram_size = qxl->vgamem_size * 2;
1916 /* vram32 (surfaces, 32bit, bar 1) */
1917 if (qxl->vram32_size_mb != -1) {
1918 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1920 if (qxl->vram32_size < 4096) {
1921 qxl->vram32_size = 4096;
1924 /* vram (surfaces, 64bit, bar 4+5) */
1925 if (qxl->vram_size_mb != -1) {
1926 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1928 if (qxl->vram_size < qxl->vram32_size) {
1929 qxl->vram_size = qxl->vram32_size;
1932 if (qxl->revision == 1) {
1933 qxl->vram32_size = 4096;
1934 qxl->vram_size = 4096;
1936 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1937 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1938 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1939 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1942 static int qxl_init_common(PCIQXLDevice *qxl)
1944 uint8_t* config = qxl->pci.config;
1945 uint32_t pci_device_rev;
1946 uint32_t io_size;
1948 qxl->mode = QXL_MODE_UNDEFINED;
1949 qxl->generation = 1;
1950 qxl->num_memslots = NUM_MEMSLOTS;
1951 qemu_mutex_init(&qxl->track_lock);
1952 qemu_mutex_init(&qxl->async_lock);
1953 qxl->current_async = QXL_UNDEFINED_IO;
1954 qxl->guest_bug = 0;
1956 switch (qxl->revision) {
1957 case 1: /* spice 0.4 -- qxl-1 */
1958 pci_device_rev = QXL_REVISION_STABLE_V04;
1959 io_size = 8;
1960 break;
1961 case 2: /* spice 0.6 -- qxl-2 */
1962 pci_device_rev = QXL_REVISION_STABLE_V06;
1963 io_size = 16;
1964 break;
1965 case 3: /* qxl-3 */
1966 pci_device_rev = QXL_REVISION_STABLE_V10;
1967 io_size = 32; /* PCI region size must be pow2 */
1968 break;
1969 case 4: /* qxl-4 */
1970 pci_device_rev = QXL_REVISION_STABLE_V12;
1971 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1972 break;
1973 default:
1974 error_report("Invalid revision %d for qxl device (max %d)",
1975 qxl->revision, QXL_DEFAULT_REVISION);
1976 return -1;
1979 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1980 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1982 qxl->rom_size = qxl_rom_size();
1983 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1984 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1985 init_qxl_rom(qxl);
1986 init_qxl_ram(qxl);
1988 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
1989 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1990 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1991 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1992 0, qxl->vram32_size);
1994 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1995 "qxl-ioports", io_size);
1996 if (qxl->id == 0) {
1997 vga_dirty_log_start(&qxl->vga);
1999 memory_region_set_flush_coalesced(&qxl->io_bar);
2002 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2003 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2005 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2006 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2008 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2009 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2011 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2012 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2014 if (qxl->vram32_size < qxl->vram_size) {
2016 * Make the 64bit vram bar show up only in case it is
2017 * configured to be larger than the 32bit vram bar.
2019 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2020 PCI_BASE_ADDRESS_SPACE_MEMORY |
2021 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2022 PCI_BASE_ADDRESS_MEM_PREFETCH,
2023 &qxl->vram_bar);
2026 /* print pci bar details */
2027 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2028 qxl->id == 0 ? "pri" : "sec",
2029 qxl->vga.vram_size / (1024*1024));
2030 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2031 qxl->vram32_size / (1024*1024));
2032 dprint(qxl, 1, "vram/64: %d MB %s\n",
2033 qxl->vram_size / (1024*1024),
2034 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2036 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2037 qxl->ssd.qxl.id = qxl->id;
2038 if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) {
2039 error_report("qxl interface %d.%d not supported by spice-server\n",
2040 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2041 return -1;
2043 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2045 init_pipe_signaling(qxl);
2046 qxl_reset_state(qxl);
2048 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2050 return 0;
2053 static int qxl_init_primary(PCIDevice *dev)
2055 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2056 VGACommonState *vga = &qxl->vga;
2057 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
2058 int rc;
2060 qxl->id = 0;
2061 qxl_init_ramsize(qxl);
2062 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2063 vga_common_init(vga);
2064 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
2065 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
2066 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
2068 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
2069 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
2070 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
2072 qxl0 = qxl;
2074 rc = qxl_init_common(qxl);
2075 if (rc != 0) {
2076 return rc;
2079 register_displaychangelistener(vga->ds, &display_listener);
2080 return rc;
2083 static int qxl_init_secondary(PCIDevice *dev)
2085 static int device_id = 1;
2086 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2088 qxl->id = device_id++;
2089 qxl_init_ramsize(qxl);
2090 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
2091 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2092 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2094 return qxl_init_common(qxl);
2097 static void qxl_pre_save(void *opaque)
2099 PCIQXLDevice* d = opaque;
2100 uint8_t *ram_start = d->vga.vram_ptr;
2102 trace_qxl_pre_save(d->id);
2103 if (d->last_release == NULL) {
2104 d->last_release_offset = 0;
2105 } else {
2106 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2108 assert(d->last_release_offset < d->vga.vram_size);
2111 static int qxl_pre_load(void *opaque)
2113 PCIQXLDevice* d = opaque;
2115 trace_qxl_pre_load(d->id);
2116 qxl_hard_reset(d, 1);
2117 qxl_exit_vga_mode(d);
2118 return 0;
2121 static void qxl_create_memslots(PCIQXLDevice *d)
2123 int i;
2125 for (i = 0; i < NUM_MEMSLOTS; i++) {
2126 if (!d->guest_slots[i].active) {
2127 continue;
2129 qxl_add_memslot(d, i, 0, QXL_SYNC);
2133 static int qxl_post_load(void *opaque, int version)
2135 PCIQXLDevice* d = opaque;
2136 uint8_t *ram_start = d->vga.vram_ptr;
2137 QXLCommandExt *cmds;
2138 int in, out, newmode;
2140 assert(d->last_release_offset < d->vga.vram_size);
2141 if (d->last_release_offset == 0) {
2142 d->last_release = NULL;
2143 } else {
2144 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2147 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2149 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2150 newmode = d->mode;
2151 d->mode = QXL_MODE_UNDEFINED;
2153 switch (newmode) {
2154 case QXL_MODE_UNDEFINED:
2155 qxl_create_memslots(d);
2156 break;
2157 case QXL_MODE_VGA:
2158 qxl_create_memslots(d);
2159 qxl_enter_vga_mode(d);
2160 break;
2161 case QXL_MODE_NATIVE:
2162 qxl_create_memslots(d);
2163 qxl_create_guest_primary(d, 1, QXL_SYNC);
2165 /* replay surface-create and cursor-set commands */
2166 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2167 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2168 if (d->guest_surfaces.cmds[in] == 0) {
2169 continue;
2171 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2172 cmds[out].cmd.type = QXL_CMD_SURFACE;
2173 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2174 out++;
2176 if (d->guest_cursor) {
2177 cmds[out].cmd.data = d->guest_cursor;
2178 cmds[out].cmd.type = QXL_CMD_CURSOR;
2179 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2180 out++;
2182 qxl_spice_loadvm_commands(d, cmds, out);
2183 g_free(cmds);
2184 if (d->guest_monitors_config) {
2185 qxl_spice_monitors_config_async(d, 1);
2187 break;
2188 case QXL_MODE_COMPAT:
2189 /* note: no need to call qxl_create_memslots, qxl_set_mode
2190 * creates the mem slot. */
2191 qxl_set_mode(d, d->shadow_rom.mode, 1);
2192 break;
2194 return 0;
2197 #define QXL_SAVE_VERSION 21
2199 static bool qxl_monitors_config_needed(void *opaque)
2201 PCIQXLDevice *qxl = opaque;
2203 return qxl->guest_monitors_config != 0;
2207 static VMStateDescription qxl_memslot = {
2208 .name = "qxl-memslot",
2209 .version_id = QXL_SAVE_VERSION,
2210 .minimum_version_id = QXL_SAVE_VERSION,
2211 .fields = (VMStateField[]) {
2212 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2213 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2214 VMSTATE_UINT32(active, struct guest_slots),
2215 VMSTATE_END_OF_LIST()
2219 static VMStateDescription qxl_surface = {
2220 .name = "qxl-surface",
2221 .version_id = QXL_SAVE_VERSION,
2222 .minimum_version_id = QXL_SAVE_VERSION,
2223 .fields = (VMStateField[]) {
2224 VMSTATE_UINT32(width, QXLSurfaceCreate),
2225 VMSTATE_UINT32(height, QXLSurfaceCreate),
2226 VMSTATE_INT32(stride, QXLSurfaceCreate),
2227 VMSTATE_UINT32(format, QXLSurfaceCreate),
2228 VMSTATE_UINT32(position, QXLSurfaceCreate),
2229 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2230 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2231 VMSTATE_UINT32(type, QXLSurfaceCreate),
2232 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2233 VMSTATE_END_OF_LIST()
2237 static VMStateDescription qxl_vmstate_monitors_config = {
2238 .name = "qxl/monitors-config",
2239 .version_id = 1,
2240 .minimum_version_id = 1,
2241 .fields = (VMStateField[]) {
2242 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2243 VMSTATE_END_OF_LIST()
2247 static VMStateDescription qxl_vmstate = {
2248 .name = "qxl",
2249 .version_id = QXL_SAVE_VERSION,
2250 .minimum_version_id = QXL_SAVE_VERSION,
2251 .pre_save = qxl_pre_save,
2252 .pre_load = qxl_pre_load,
2253 .post_load = qxl_post_load,
2254 .fields = (VMStateField[]) {
2255 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2256 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2257 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2258 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2259 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2260 VMSTATE_UINT32(mode, PCIQXLDevice),
2261 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2262 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2263 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2264 qxl_memslot, struct guest_slots),
2265 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2266 qxl_surface, QXLSurfaceCreate),
2267 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2268 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2269 ssd.num_surfaces, 0,
2270 vmstate_info_uint64, uint64_t),
2271 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2272 VMSTATE_END_OF_LIST()
2274 .subsections = (VMStateSubsection[]) {
2276 .vmsd = &qxl_vmstate_monitors_config,
2277 .needed = qxl_monitors_config_needed,
2278 }, {
2279 /* empty */
2284 static Property qxl_properties[] = {
2285 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2286 64 * 1024 * 1024),
2287 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2288 64 * 1024 * 1024),
2289 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2290 QXL_DEFAULT_REVISION),
2291 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2292 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2293 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2294 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2295 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2296 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2297 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2298 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2299 DEFINE_PROP_END_OF_LIST(),
2302 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2304 DeviceClass *dc = DEVICE_CLASS(klass);
2305 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2307 k->no_hotplug = 1;
2308 k->init = qxl_init_primary;
2309 k->romfile = "vgabios-qxl.bin";
2310 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2311 k->device_id = QXL_DEVICE_ID_STABLE;
2312 k->class_id = PCI_CLASS_DISPLAY_VGA;
2313 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2314 dc->reset = qxl_reset_handler;
2315 dc->vmsd = &qxl_vmstate;
2316 dc->props = qxl_properties;
2319 static const TypeInfo qxl_primary_info = {
2320 .name = "qxl-vga",
2321 .parent = TYPE_PCI_DEVICE,
2322 .instance_size = sizeof(PCIQXLDevice),
2323 .class_init = qxl_primary_class_init,
2326 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2328 DeviceClass *dc = DEVICE_CLASS(klass);
2329 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2331 k->init = qxl_init_secondary;
2332 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2333 k->device_id = QXL_DEVICE_ID_STABLE;
2334 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2335 dc->desc = "Spice QXL GPU (secondary)";
2336 dc->reset = qxl_reset_handler;
2337 dc->vmsd = &qxl_vmstate;
2338 dc->props = qxl_properties;
2341 static const TypeInfo qxl_secondary_info = {
2342 .name = "qxl",
2343 .parent = TYPE_PCI_DEVICE,
2344 .instance_size = sizeof(PCIQXLDevice),
2345 .class_init = qxl_secondary_class_init,
2348 static void qxl_register_types(void)
2350 type_register_static(&qxl_primary_info);
2351 type_register_static(&qxl_secondary_info);
2354 type_init(qxl_register_types)