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virtio-net: introduce a new macaddr control
[qemu/ar7.git] / hw / e1000.c
blobee85c53d38b0683adebc67890785f0d0521e1795
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci/pci.h"
30 #include "net/net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/dma.h"
35
36 #include "e1000_hw.h"
37
38 #define E1000_DEBUG
39
40 #ifdef E1000_DEBUG
41 enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
46 };
47 #define DBGBIT(x) (1<<DEBUG_##x)
48 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
50 #define DBGOUT(what, fmt, ...) do { \
51 if (debugflags & DBGBIT(what)) \
52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
53 } while (0)
54 #else
55 #define DBGOUT(what, fmt, ...) do {} while (0)
56 #endif
57
58 #define IOPORT_SIZE 0x40
59 #define PNPMMIO_SIZE 0x20000
60 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
61
62 /* this is the size past which hardware will drop packets when setting LPE=0 */
63 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
64 /* this is the size past which hardware will drop packets when setting LPE=1 */
65 #define MAXIMUM_ETHERNET_LPE_SIZE 16384
66
67 /*
68 * HW models:
69 * E1000_DEV_ID_82540EM works with Windows and Linux
70 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
71 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
72 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
73 * Others never tested
74 */
75 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
76
77 /*
78 * May need to specify additional MAC-to-PHY entries --
79 * Intel's Windows driver refuses to initialize unless they match
80 */
81 enum {
82 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
83 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
84 /* default to E1000_DEV_ID_82540EM */ 0xc20
85 };
86
87 typedef struct E1000State_st {
88 PCIDevice dev;
89 NICState *nic;
90 NICConf conf;
91 MemoryRegion mmio;
92 MemoryRegion io;
93
94 uint32_t mac_reg[0x8000];
95 uint16_t phy_reg[0x20];
96 uint16_t eeprom_data[64];
97
98 uint32_t rxbuf_size;
99 uint32_t rxbuf_min_shift;
100 struct e1000_tx {
101 unsigned char header[256];
102 unsigned char vlan_header[4];
103 /* Fields vlan and data must not be reordered or separated. */
104 unsigned char vlan[4];
105 unsigned char data[0x10000];
106 uint16_t size;
107 unsigned char sum_needed;
108 unsigned char vlan_needed;
109 uint8_t ipcss;
110 uint8_t ipcso;
111 uint16_t ipcse;
112 uint8_t tucss;
113 uint8_t tucso;
114 uint16_t tucse;
115 uint8_t hdr_len;
116 uint16_t mss;
117 uint32_t paylen;
118 uint16_t tso_frames;
119 char tse;
120 int8_t ip;
121 int8_t tcp;
122 char cptse; // current packet tse bit
123 } tx;
124
125 struct {
126 uint32_t val_in; // shifted in from guest driver
127 uint16_t bitnum_in;
128 uint16_t bitnum_out;
129 uint16_t reading;
130 uint32_t old_eecd;
131 } eecd_state;
132
133 QEMUTimer *autoneg_timer;
134 } E1000State;
135
136 #define defreg(x) x = (E1000_##x>>2)
137 enum {
138 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
139 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
140 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
141 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
142 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
143 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
144 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
145 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
146 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
147 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
148 defreg(VET),
149 };
150
151 static void
152 e1000_link_down(E1000State *s)
153 {
154 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
155 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
156 }
157
158 static void
159 e1000_link_up(E1000State *s)
160 {
161 s->mac_reg[STATUS] |= E1000_STATUS_LU;
162 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
163 }
164
165 static void
166 set_phy_ctrl(E1000State *s, int index, uint16_t val)
167 {
168 if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) {
169 /* no need auto-negotiation if link was down */
170 if (s->nic->nc.link_down) {
171 s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
172 return;
173 }
174 s->nic->nc.link_down = true;
175 e1000_link_down(s);
176 s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE;
177 DBGOUT(PHY, "Start link auto negotiation\n");
178 qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
179 }
180 }
181
182 static void
183 e1000_autoneg_timer(void *opaque)
184 {
185 E1000State *s = opaque;
186 s->nic->nc.link_down = false;
187 e1000_link_up(s);
188 s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
189 DBGOUT(PHY, "Auto negotiation is completed\n");
190 }
191
192 static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
193 [PHY_CTRL] = set_phy_ctrl,
194 };
195
196 enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
197
198 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
199 static const char phy_regcap[0x20] = {
200 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
201 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
202 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
203 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
204 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
205 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
206 };
207
208 static const uint16_t phy_reg_init[] = {
209 [PHY_CTRL] = 0x1140,
210 [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */
211 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
212 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
213 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
214 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
215 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
216 };
217
218 static const uint32_t mac_reg_init[] = {
219 [PBA] = 0x00100030,
220 [LEDCTL] = 0x602,
221 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
222 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
223 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
224 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
225 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
226 E1000_STATUS_LU,
227 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
228 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
229 E1000_MANC_RMCP_EN,
230 };
231
232 static void
233 set_interrupt_cause(E1000State *s, int index, uint32_t val)
234 {
235 if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
236 /* Only for 8257x */
237 val |= E1000_ICR_INT_ASSERTED;
238 }
239 s->mac_reg[ICR] = val;
240
241 /*
242 * Make sure ICR and ICS registers have the same value.
243 * The spec says that the ICS register is write-only. However in practice,
244 * on real hardware ICS is readable, and for reads it has the same value as
245 * ICR (except that ICS does not have the clear on read behaviour of ICR).
246 *
247 * The VxWorks PRO/1000 driver uses this behaviour.
248 */
249 s->mac_reg[ICS] = val;
250
251 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
252 }
253
254 static void
255 set_ics(E1000State *s, int index, uint32_t val)
256 {
257 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
258 s->mac_reg[IMS]);
259 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
260 }
261
262 static int
263 rxbufsize(uint32_t v)
264 {
265 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
266 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
267 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
268 switch (v) {
269 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
270 return 16384;
271 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
272 return 8192;
273 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
274 return 4096;
275 case E1000_RCTL_SZ_1024:
276 return 1024;
277 case E1000_RCTL_SZ_512:
278 return 512;
279 case E1000_RCTL_SZ_256:
280 return 256;
281 }
282 return 2048;
283 }
284
285 static void e1000_reset(void *opaque)
286 {
287 E1000State *d = opaque;
288 uint8_t *macaddr = d->conf.macaddr.a;
289 int i;
290
291 qemu_del_timer(d->autoneg_timer);
292 memset(d->phy_reg, 0, sizeof d->phy_reg);
293 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
294 memset(d->mac_reg, 0, sizeof d->mac_reg);
295 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
296 d->rxbuf_min_shift = 1;
297 memset(&d->tx, 0, sizeof d->tx);
298
299 if (d->nic->nc.link_down) {
300 e1000_link_down(d);
301 }
302
303 /* Some guests expect pre-initialized RAH/RAL (AddrValid flag + MACaddr) */
304 d->mac_reg[RA] = 0;
305 d->mac_reg[RA + 1] = E1000_RAH_AV;
306 for (i = 0; i < 4; i++) {
307 d->mac_reg[RA] |= macaddr[i] << (8 * i);
308 d->mac_reg[RA + 1] |= (i < 2) ? macaddr[i + 4] << (8 * i) : 0;
309 }
310 }
311
312 static void
313 set_ctrl(E1000State *s, int index, uint32_t val)
314 {
315 /* RST is self clearing */
316 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
317 }
318
319 static void
320 set_rx_control(E1000State *s, int index, uint32_t val)
321 {
322 s->mac_reg[RCTL] = val;
323 s->rxbuf_size = rxbufsize(val);
324 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
325 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
326 s->mac_reg[RCTL]);
327 qemu_flush_queued_packets(&s->nic->nc);
328 }
329
330 static void
331 set_mdic(E1000State *s, int index, uint32_t val)
332 {
333 uint32_t data = val & E1000_MDIC_DATA_MASK;
334 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
335
336 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
337 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
338 else if (val & E1000_MDIC_OP_READ) {
339 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
340 if (!(phy_regcap[addr] & PHY_R)) {
341 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
342 val |= E1000_MDIC_ERROR;
343 } else
344 val = (val ^ data) | s->phy_reg[addr];
345 } else if (val & E1000_MDIC_OP_WRITE) {
346 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
347 if (!(phy_regcap[addr] & PHY_W)) {
348 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
349 val |= E1000_MDIC_ERROR;
350 } else {
351 if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
352 phyreg_writeops[addr](s, index, data);
353 }
354 s->phy_reg[addr] = data;
355 }
356 }
357 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
358
359 if (val & E1000_MDIC_INT_EN) {
360 set_ics(s, 0, E1000_ICR_MDAC);
361 }
362 }
363
364 static uint32_t
365 get_eecd(E1000State *s, int index)
366 {
367 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
368
369 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
370 s->eecd_state.bitnum_out, s->eecd_state.reading);
371 if (!s->eecd_state.reading ||
372 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
373 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
374 ret |= E1000_EECD_DO;
375 return ret;
376 }
377
378 static void
379 set_eecd(E1000State *s, int index, uint32_t val)
380 {
381 uint32_t oldval = s->eecd_state.old_eecd;
382
383 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
384 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
385 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
386 return;
387 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
388 s->eecd_state.val_in = 0;
389 s->eecd_state.bitnum_in = 0;
390 s->eecd_state.bitnum_out = 0;
391 s->eecd_state.reading = 0;
392 }
393 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
394 return;
395 if (!(E1000_EECD_SK & val)) { // falling edge
396 s->eecd_state.bitnum_out++;
397 return;
398 }
399 s->eecd_state.val_in <<= 1;
400 if (val & E1000_EECD_DI)
401 s->eecd_state.val_in |= 1;
402 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
403 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
404 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
405 EEPROM_READ_OPCODE_MICROWIRE);
406 }
407 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
408 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
409 s->eecd_state.reading);
410 }
411
412 static uint32_t
413 flash_eerd_read(E1000State *s, int x)
414 {
415 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
416
417 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
418 return (s->mac_reg[EERD]);
419
420 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
421 return (E1000_EEPROM_RW_REG_DONE | r);
422
423 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
424 E1000_EEPROM_RW_REG_DONE | r);
425 }
426
427 static void
428 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
429 {
430 uint32_t sum;
431
432 if (cse && cse < n)
433 n = cse + 1;
434 if (sloc < n-1) {
435 sum = net_checksum_add(n-css, data+css);
436 cpu_to_be16wu((uint16_t *)(data + sloc),
437 net_checksum_finish(sum));
438 }
439 }
440
441 static inline int
442 vlan_enabled(E1000State *s)
443 {
444 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
445 }
446
447 static inline int
448 vlan_rx_filter_enabled(E1000State *s)
449 {
450 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
451 }
452
453 static inline int
454 is_vlan_packet(E1000State *s, const uint8_t *buf)
455 {
456 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
457 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
458 }
459
460 static inline int
461 is_vlan_txd(uint32_t txd_lower)
462 {
463 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
464 }
465
466 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
467 * fill it in, just pad descriptor length by 4 bytes unless guest
468 * told us to strip it off the packet. */
469 static inline int
470 fcs_len(E1000State *s)
471 {
472 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
473 }
474
475 static void
476 e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
477 {
478 if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
479 s->nic->nc.info->receive(&s->nic->nc, buf, size);
480 } else {
481 qemu_send_packet(&s->nic->nc, buf, size);
482 }
483 }
484
485 static void
486 xmit_seg(E1000State *s)
487 {
488 uint16_t len, *sp;
489 unsigned int frames = s->tx.tso_frames, css, sofar, n;
490 struct e1000_tx *tp = &s->tx;
491
492 if (tp->tse && tp->cptse) {
493 css = tp->ipcss;
494 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
495 frames, tp->size, css);
496 if (tp->ip) { // IPv4
497 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
498 tp->size - css);
499 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
500 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
501 } else // IPv6
502 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
503 tp->size - css);
504 css = tp->tucss;
505 len = tp->size - css;
506 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
507 if (tp->tcp) {
508 sofar = frames * tp->mss;
509 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
510 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
511 if (tp->paylen - sofar > tp->mss)
512 tp->data[css + 13] &= ~9; // PSH, FIN
513 } else // UDP
514 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
515 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
516 unsigned int phsum;
517 // add pseudo-header length before checksum calculation
518 sp = (uint16_t *)(tp->data + tp->tucso);
519 phsum = be16_to_cpup(sp) + len;
520 phsum = (phsum >> 16) + (phsum & 0xffff);
521 cpu_to_be16wu(sp, phsum);
522 }
523 tp->tso_frames++;
524 }
525
526 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
527 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
528 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
529 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
530 if (tp->vlan_needed) {
531 memmove(tp->vlan, tp->data, 4);
532 memmove(tp->data, tp->data + 4, 8);
533 memcpy(tp->data + 8, tp->vlan_header, 4);
534 e1000_send_packet(s, tp->vlan, tp->size + 4);
535 } else
536 e1000_send_packet(s, tp->data, tp->size);
537 s->mac_reg[TPT]++;
538 s->mac_reg[GPTC]++;
539 n = s->mac_reg[TOTL];
540 if ((s->mac_reg[TOTL] += s->tx.size) < n)
541 s->mac_reg[TOTH]++;
542 }
543
544 static void
545 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
546 {
547 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
548 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
549 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
550 unsigned int msh = 0xfffff, hdr = 0;
551 uint64_t addr;
552 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
553 struct e1000_tx *tp = &s->tx;
554
555 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
556 op = le32_to_cpu(xp->cmd_and_length);
557 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
558 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
559 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
560 tp->tucss = xp->upper_setup.tcp_fields.tucss;
561 tp->tucso = xp->upper_setup.tcp_fields.tucso;
562 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
563 tp->paylen = op & 0xfffff;
564 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
565 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
566 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
567 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
568 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
569 tp->tso_frames = 0;
570 if (tp->tucso == 0) { // this is probably wrong
571 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
572 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
573 }
574 return;
575 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
576 // data descriptor
577 if (tp->size == 0) {
578 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
579 }
580 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
581 } else {
582 // legacy descriptor
583 tp->cptse = 0;
584 }
585
586 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
587 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
588 tp->vlan_needed = 1;
589 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
590 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
591 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
592 le16_to_cpu(dp->upper.fields.special));
593 }
594
595 addr = le64_to_cpu(dp->buffer_addr);
596 if (tp->tse && tp->cptse) {
597 hdr = tp->hdr_len;
598 msh = hdr + tp->mss;
599 do {
600 bytes = split_size;
601 if (tp->size + bytes > msh)
602 bytes = msh - tp->size;
603
604 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
605 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
606 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
607 memmove(tp->header, tp->data, hdr);
608 tp->size = sz;
609 addr += bytes;
610 if (sz == msh) {
611 xmit_seg(s);
612 memmove(tp->data, tp->header, hdr);
613 tp->size = hdr;
614 }
615 } while (split_size -= bytes);
616 } else if (!tp->tse && tp->cptse) {
617 // context descriptor TSE is not set, while data descriptor TSE is set
618 DBGOUT(TXERR, "TCP segmentation error\n");
619 } else {
620 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
621 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
622 tp->size += split_size;
623 }
624
625 if (!(txd_lower & E1000_TXD_CMD_EOP))
626 return;
627 if (!(tp->tse && tp->cptse && tp->size < hdr))
628 xmit_seg(s);
629 tp->tso_frames = 0;
630 tp->sum_needed = 0;
631 tp->vlan_needed = 0;
632 tp->size = 0;
633 tp->cptse = 0;
634 }
635
636 static uint32_t
637 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
638 {
639 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
640
641 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
642 return 0;
643 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
644 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
645 dp->upper.data = cpu_to_le32(txd_upper);
646 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
647 &dp->upper, sizeof(dp->upper));
648 return E1000_ICR_TXDW;
649 }
650
651 static uint64_t tx_desc_base(E1000State *s)
652 {
653 uint64_t bah = s->mac_reg[TDBAH];
654 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
655
656 return (bah << 32) + bal;
657 }
658
659 static void
660 start_xmit(E1000State *s)
661 {
662 dma_addr_t base;
663 struct e1000_tx_desc desc;
664 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
665
666 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
667 DBGOUT(TX, "tx disabled\n");
668 return;
669 }
670
671 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
672 base = tx_desc_base(s) +
673 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
674 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
675
676 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
677 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
678 desc.upper.data);
679
680 process_tx_desc(s, &desc);
681 cause |= txdesc_writeback(s, base, &desc);
682
683 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
684 s->mac_reg[TDH] = 0;
685 /*
686 * the following could happen only if guest sw assigns
687 * bogus values to TDT/TDLEN.
688 * there's nothing too intelligent we could do about this.
689 */
690 if (s->mac_reg[TDH] == tdh_start) {
691 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
692 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
693 break;
694 }
695 }
696 set_ics(s, 0, cause);
697 }
698
699 static int
700 receive_filter(E1000State *s, const uint8_t *buf, int size)
701 {
702 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
703 static const int mta_shift[] = {4, 3, 2, 0};
704 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
705
706 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
707 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
708 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
709 ((vid >> 5) & 0x7f));
710 if ((vfta & (1 << (vid & 0x1f))) == 0)
711 return 0;
712 }
713
714 if (rctl & E1000_RCTL_UPE) // promiscuous
715 return 1;
716
717 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
718 return 1;
719
720 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
721 return 1;
722
723 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
724 if (!(rp[1] & E1000_RAH_AV))
725 continue;
726 ra[0] = cpu_to_le32(rp[0]);
727 ra[1] = cpu_to_le32(rp[1]);
728 if (!memcmp(buf, (uint8_t *)ra, 6)) {
729 DBGOUT(RXFILTER,
730 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
731 (int)(rp - s->mac_reg - RA)/2,
732 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
733 return 1;
734 }
735 }
736 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
737 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
738
739 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
740 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
741 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
742 return 1;
743 DBGOUT(RXFILTER,
744 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
745 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
746 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
747 s->mac_reg[MTA + (f >> 5)]);
748
749 return 0;
750 }
751
752 static void
753 e1000_set_link_status(NetClientState *nc)
754 {
755 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
756 uint32_t old_status = s->mac_reg[STATUS];
757
758 if (nc->link_down) {
759 e1000_link_down(s);
760 } else {
761 e1000_link_up(s);
762 }
763
764 if (s->mac_reg[STATUS] != old_status)
765 set_ics(s, 0, E1000_ICR_LSC);
766 }
767
768 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
769 {
770 int bufs;
771 /* Fast-path short packets */
772 if (total_size <= s->rxbuf_size) {
773 return s->mac_reg[RDH] != s->mac_reg[RDT];
774 }
775 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
776 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
777 } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) {
778 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
779 s->mac_reg[RDT] - s->mac_reg[RDH];
780 } else {
781 return false;
782 }
783 return total_size <= bufs * s->rxbuf_size;
784 }
785
786 static int
787 e1000_can_receive(NetClientState *nc)
788 {
789 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
790
791 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
792 }
793
794 static uint64_t rx_desc_base(E1000State *s)
795 {
796 uint64_t bah = s->mac_reg[RDBAH];
797 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
798
799 return (bah << 32) + bal;
800 }
801
802 static ssize_t
803 e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
804 {
805 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
806 struct e1000_rx_desc desc;
807 dma_addr_t base;
808 unsigned int n, rdt;
809 uint32_t rdh_start;
810 uint16_t vlan_special = 0;
811 uint8_t vlan_status = 0, vlan_offset = 0;
812 uint8_t min_buf[MIN_BUF_SIZE];
813 size_t desc_offset;
814 size_t desc_size;
815 size_t total_size;
816
817 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
818 return -1;
819
820 /* Pad to minimum Ethernet frame length */
821 if (size < sizeof(min_buf)) {
822 memcpy(min_buf, buf, size);
823 memset(&min_buf[size], 0, sizeof(min_buf) - size);
824 buf = min_buf;
825 size = sizeof(min_buf);
826 }
827
828 /* Discard oversized packets if !LPE and !SBP. */
829 if ((size > MAXIMUM_ETHERNET_LPE_SIZE ||
830 (size > MAXIMUM_ETHERNET_VLAN_SIZE
831 && !(s->mac_reg[RCTL] & E1000_RCTL_LPE)))
832 && !(s->mac_reg[RCTL] & E1000_RCTL_SBP)) {
833 return size;
834 }
835
836 if (!receive_filter(s, buf, size))
837 return size;
838
839 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
840 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
841 memmove((uint8_t *)buf + 4, buf, 12);
842 vlan_status = E1000_RXD_STAT_VP;
843 vlan_offset = 4;
844 size -= 4;
845 }
846
847 rdh_start = s->mac_reg[RDH];
848 desc_offset = 0;
849 total_size = size + fcs_len(s);
850 if (!e1000_has_rxbufs(s, total_size)) {
851 set_ics(s, 0, E1000_ICS_RXO);
852 return -1;
853 }
854 do {
855 desc_size = total_size - desc_offset;
856 if (desc_size > s->rxbuf_size) {
857 desc_size = s->rxbuf_size;
858 }
859 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
860 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
861 desc.special = vlan_special;
862 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
863 if (desc.buffer_addr) {
864 if (desc_offset < size) {
865 size_t copy_size = size - desc_offset;
866 if (copy_size > s->rxbuf_size) {
867 copy_size = s->rxbuf_size;
868 }
869 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
870 buf + desc_offset + vlan_offset, copy_size);
871 }
872 desc_offset += desc_size;
873 desc.length = cpu_to_le16(desc_size);
874 if (desc_offset >= total_size) {
875 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
876 } else {
877 /* Guest zeroing out status is not a hardware requirement.
878 Clear EOP in case guest didn't do it. */
879 desc.status &= ~E1000_RXD_STAT_EOP;
880 }
881 } else { // as per intel docs; skip descriptors with null buf addr
882 DBGOUT(RX, "Null RX descriptor!!\n");
883 }
884 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
885
886 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
887 s->mac_reg[RDH] = 0;
888 /* see comment in start_xmit; same here */
889 if (s->mac_reg[RDH] == rdh_start) {
890 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
891 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
892 set_ics(s, 0, E1000_ICS_RXO);
893 return -1;
894 }
895 } while (desc_offset < total_size);
896
897 s->mac_reg[GPRC]++;
898 s->mac_reg[TPR]++;
899 /* TOR - Total Octets Received:
900 * This register includes bytes received in a packet from the <Destination
901 * Address> field through the <CRC> field, inclusively.
902 */
903 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
904 if (n < s->mac_reg[TORL])
905 s->mac_reg[TORH]++;
906 s->mac_reg[TORL] = n;
907
908 n = E1000_ICS_RXT0;
909 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
910 rdt += s->mac_reg[RDLEN] / sizeof(desc);
911 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
912 s->rxbuf_min_shift)
913 n |= E1000_ICS_RXDMT0;
914
915 set_ics(s, 0, n);
916
917 return size;
918 }
919
920 static uint32_t
921 mac_readreg(E1000State *s, int index)
922 {
923 return s->mac_reg[index];
924 }
925
926 static uint32_t
927 mac_icr_read(E1000State *s, int index)
928 {
929 uint32_t ret = s->mac_reg[ICR];
930
931 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
932 set_interrupt_cause(s, 0, 0);
933 return ret;
934 }
935
936 static uint32_t
937 mac_read_clr4(E1000State *s, int index)
938 {
939 uint32_t ret = s->mac_reg[index];
940
941 s->mac_reg[index] = 0;
942 return ret;
943 }
944
945 static uint32_t
946 mac_read_clr8(E1000State *s, int index)
947 {
948 uint32_t ret = s->mac_reg[index];
949
950 s->mac_reg[index] = 0;
951 s->mac_reg[index-1] = 0;
952 return ret;
953 }
954
955 static void
956 mac_writereg(E1000State *s, int index, uint32_t val)
957 {
958 s->mac_reg[index] = val;
959 }
960
961 static void
962 set_rdt(E1000State *s, int index, uint32_t val)
963 {
964 s->mac_reg[index] = val & 0xffff;
965 if (e1000_has_rxbufs(s, 1)) {
966 qemu_flush_queued_packets(&s->nic->nc);
967 }
968 }
969
970 static void
971 set_16bit(E1000State *s, int index, uint32_t val)
972 {
973 s->mac_reg[index] = val & 0xffff;
974 }
975
976 static void
977 set_dlen(E1000State *s, int index, uint32_t val)
978 {
979 s->mac_reg[index] = val & 0xfff80;
980 }
981
982 static void
983 set_tctl(E1000State *s, int index, uint32_t val)
984 {
985 s->mac_reg[index] = val;
986 s->mac_reg[TDT] &= 0xffff;
987 start_xmit(s);
988 }
989
990 static void
991 set_icr(E1000State *s, int index, uint32_t val)
992 {
993 DBGOUT(INTERRUPT, "set_icr %x\n", val);
994 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
995 }
996
997 static void
998 set_imc(E1000State *s, int index, uint32_t val)
999 {
1000 s->mac_reg[IMS] &= ~val;
1001 set_ics(s, 0, 0);
1002 }
1003
1004 static void
1005 set_ims(E1000State *s, int index, uint32_t val)
1006 {
1007 s->mac_reg[IMS] |= val;
1008 set_ics(s, 0, 0);
1009 }
1010
1011 #define getreg(x) [x] = mac_readreg
1012 static uint32_t (*macreg_readops[])(E1000State *, int) = {
1013 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1014 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1015 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
1016 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1017 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1018 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1019 getreg(TDLEN), getreg(RDLEN),
1020
1021 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
1022 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
1023 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
1024 [CRCERRS ... MPC] = &mac_readreg,
1025 [RA ... RA+31] = &mac_readreg,
1026 [MTA ... MTA+127] = &mac_readreg,
1027 [VFTA ... VFTA+127] = &mac_readreg,
1028 };
1029 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
1030
1031 #define putreg(x) [x] = mac_writereg
1032 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
1033 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
1034 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
1035 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
1036 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
1037 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
1038 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
1039 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
1040 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
1041 [RA ... RA+31] = &mac_writereg,
1042 [MTA ... MTA+127] = &mac_writereg,
1043 [VFTA ... VFTA+127] = &mac_writereg,
1044 };
1045
1046 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
1047
1048 static void
1049 e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1050 unsigned size)
1051 {
1052 E1000State *s = opaque;
1053 unsigned int index = (addr & 0x1ffff) >> 2;
1054
1055 if (index < NWRITEOPS && macreg_writeops[index]) {
1056 macreg_writeops[index](s, index, val);
1057 } else if (index < NREADOPS && macreg_readops[index]) {
1058 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
1059 } else {
1060 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
1061 index<<2, val);
1062 }
1063 }
1064
1065 static uint64_t
1066 e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
1067 {
1068 E1000State *s = opaque;
1069 unsigned int index = (addr & 0x1ffff) >> 2;
1070
1071 if (index < NREADOPS && macreg_readops[index])
1072 {
1073 return macreg_readops[index](s, index);
1074 }
1075 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
1076 return 0;
1077 }
1078
1079 static const MemoryRegionOps e1000_mmio_ops = {
1080 .read = e1000_mmio_read,
1081 .write = e1000_mmio_write,
1082 .endianness = DEVICE_LITTLE_ENDIAN,
1083 .impl = {
1084 .min_access_size = 4,
1085 .max_access_size = 4,
1086 },
1087 };
1088
1089 static uint64_t e1000_io_read(void *opaque, hwaddr addr,
1090 unsigned size)
1091 {
1092 E1000State *s = opaque;
1093
1094 (void)s;
1095 return 0;
1096 }
1097
1098 static void e1000_io_write(void *opaque, hwaddr addr,
1099 uint64_t val, unsigned size)
1100 {
1101 E1000State *s = opaque;
1102
1103 (void)s;
1104 }
1105
1106 static const MemoryRegionOps e1000_io_ops = {
1107 .read = e1000_io_read,
1108 .write = e1000_io_write,
1109 .endianness = DEVICE_LITTLE_ENDIAN,
1110 };
1111
1112 static bool is_version_1(void *opaque, int version_id)
1113 {
1114 return version_id == 1;
1115 }
1116
1117 static int e1000_post_load(void *opaque, int version_id)
1118 {
1119 E1000State *s = opaque;
1120
1121 /* nc.link_down can't be migrated, so infer link_down according
1122 * to link status bit in mac_reg[STATUS] */
1123 s->nic->nc.link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;
1124
1125 return 0;
1126 }
1127
1128 static const VMStateDescription vmstate_e1000 = {
1129 .name = "e1000",
1130 .version_id = 2,
1131 .minimum_version_id = 1,
1132 .minimum_version_id_old = 1,
1133 .post_load = e1000_post_load,
1134 .fields = (VMStateField []) {
1135 VMSTATE_PCI_DEVICE(dev, E1000State),
1136 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1137 VMSTATE_UNUSED(4), /* Was mmio_base. */
1138 VMSTATE_UINT32(rxbuf_size, E1000State),
1139 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1140 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1141 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1142 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1143 VMSTATE_UINT16(eecd_state.reading, E1000State),
1144 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1145 VMSTATE_UINT8(tx.ipcss, E1000State),
1146 VMSTATE_UINT8(tx.ipcso, E1000State),
1147 VMSTATE_UINT16(tx.ipcse, E1000State),
1148 VMSTATE_UINT8(tx.tucss, E1000State),
1149 VMSTATE_UINT8(tx.tucso, E1000State),
1150 VMSTATE_UINT16(tx.tucse, E1000State),
1151 VMSTATE_UINT32(tx.paylen, E1000State),
1152 VMSTATE_UINT8(tx.hdr_len, E1000State),
1153 VMSTATE_UINT16(tx.mss, E1000State),
1154 VMSTATE_UINT16(tx.size, E1000State),
1155 VMSTATE_UINT16(tx.tso_frames, E1000State),
1156 VMSTATE_UINT8(tx.sum_needed, E1000State),
1157 VMSTATE_INT8(tx.ip, E1000State),
1158 VMSTATE_INT8(tx.tcp, E1000State),
1159 VMSTATE_BUFFER(tx.header, E1000State),
1160 VMSTATE_BUFFER(tx.data, E1000State),
1161 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1162 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1163 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1164 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1165 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1166 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1167 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1168 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1169 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1170 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1171 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1172 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1173 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1174 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1175 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1176 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1177 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1178 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1179 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1180 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1181 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1182 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1183 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1184 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1185 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1186 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1187 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1188 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1189 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1190 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1191 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1192 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1193 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1194 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1195 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1196 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1197 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1198 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1199 VMSTATE_UINT32(mac_reg[VET], E1000State),
1200 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1201 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1202 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1203 VMSTATE_END_OF_LIST()
1204 }
1205 };
1206
1207 static const uint16_t e1000_eeprom_template[64] = {
1208 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1209 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1210 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1211 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1212 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1213 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1214 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1215 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1216 };
1217
1218 /* PCI interface */
1219
1220 static void
1221 e1000_mmio_setup(E1000State *d)
1222 {
1223 int i;
1224 const uint32_t excluded_regs[] = {
1225 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1226 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1227 };
1228
1229 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1230 PNPMMIO_SIZE);
1231 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
1232 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1233 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1234 excluded_regs[i+1] - excluded_regs[i] - 4);
1235 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
1236 }
1237
1238 static void
1239 e1000_cleanup(NetClientState *nc)
1240 {
1241 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1242
1243 s->nic = NULL;
1244 }
1245
1246 static void
1247 pci_e1000_uninit(PCIDevice *dev)
1248 {
1249 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1250
1251 qemu_del_timer(d->autoneg_timer);
1252 qemu_free_timer(d->autoneg_timer);
1253 memory_region_destroy(&d->mmio);
1254 memory_region_destroy(&d->io);
1255 qemu_del_net_client(&d->nic->nc);
1256 }
1257
1258 static NetClientInfo net_e1000_info = {
1259 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1260 .size = sizeof(NICState),
1261 .can_receive = e1000_can_receive,
1262 .receive = e1000_receive,
1263 .cleanup = e1000_cleanup,
1264 .link_status_changed = e1000_set_link_status,
1265 };
1266
1267 static int pci_e1000_init(PCIDevice *pci_dev)
1268 {
1269 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1270 uint8_t *pci_conf;
1271 uint16_t checksum = 0;
1272 int i;
1273 uint8_t *macaddr;
1274
1275 pci_conf = d->dev.config;
1276
1277 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1278 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1279
1280 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1281
1282 e1000_mmio_setup(d);
1283
1284 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
1285
1286 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
1287
1288 memmove(d->eeprom_data, e1000_eeprom_template,
1289 sizeof e1000_eeprom_template);
1290 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1291 macaddr = d->conf.macaddr.a;
1292 for (i = 0; i < 3; i++)
1293 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1294 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1295 checksum += d->eeprom_data[i];
1296 checksum = (uint16_t) EEPROM_SUM - checksum;
1297 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1298
1299 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1300 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
1301
1302 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1303
1304 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1305
1306 d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
1307
1308 return 0;
1309 }
1310
1311 static void qdev_e1000_reset(DeviceState *dev)
1312 {
1313 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1314 e1000_reset(d);
1315 }
1316
1317 static Property e1000_properties[] = {
1318 DEFINE_NIC_PROPERTIES(E1000State, conf),
1319 DEFINE_PROP_END_OF_LIST(),
1320 };
1321
1322 static void e1000_class_init(ObjectClass *klass, void *data)
1323 {
1324 DeviceClass *dc = DEVICE_CLASS(klass);
1325 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1326
1327 k->init = pci_e1000_init;
1328 k->exit = pci_e1000_uninit;
1329 k->romfile = "pxe-e1000.rom";
1330 k->vendor_id = PCI_VENDOR_ID_INTEL;
1331 k->device_id = E1000_DEVID;
1332 k->revision = 0x03;
1333 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
1334 dc->desc = "Intel Gigabit Ethernet";
1335 dc->reset = qdev_e1000_reset;
1336 dc->vmsd = &vmstate_e1000;
1337 dc->props = e1000_properties;
1338 }
1339
1340 static const TypeInfo e1000_info = {
1341 .name = "e1000",
1342 .parent = TYPE_PCI_DEVICE,
1343 .instance_size = sizeof(E1000State),
1344 .class_init = e1000_class_init,
1345 };
1346
1347 static void e1000_register_types(void)
1348 {
1349 type_register_static(&e1000_info);
1350 }
1351
1352 type_init(e1000_register_types)
AR7 emulation for QEMU