hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "monitor/monitor.h"
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/i386/ioapic.h"
  29 #include "hw/i386/ioapic_internal.h"
  30 #include "include/hw/pci/msi.h"
  31 #include "sysemu/kvm.h"
  32 #include "target-i386/cpu.h"
  33 #include "hw/i386/apic-msidef.h"
  34
  35 //#define DEBUG_IOAPIC
  36
  37 #ifdef DEBUG_IOAPIC
  38 #define DPRINTF(fmt, ...)                                       \
  39     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...)
  42 #endif
  43
  44 #define APIC_DELIVERY_MODE_SHIFT 8
  45 #define APIC_POLARITY_SHIFT 14
  46 #define APIC_TRIG_MODE_SHIFT 15
  47
  48 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  49
  50 /* global variable from ioapic_common.c */
  51 extern int ioapic_no;
  52
  53 struct ioapic_entry_info {
  54     /* fields parsed from IOAPIC entries */
  55     uint8_t masked;
  56     uint8_t trig_mode;
  57     uint16_t dest_idx;
  58     uint8_t dest_mode;
  59     uint8_t delivery_mode;
  60     uint8_t vector;
  61
  62     /* MSI message generated from above parsed fields */
  63     uint32_t addr;
  64     uint32_t data;
  65 };
  66
  67 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
  68 {
  69     memset(info, 0, sizeof(*info));
  70     info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
  71     info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
  72     /*
  73      * By default, this would be dest_id[8] + reserved[8]. When IR
  74      * is enabled, this would be interrupt_index[15] +
  75      * interrupt_format[1]. This field never means anything, but
  76      * only used to generate corresponding MSI.
  77      */
  78     info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
  79     info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  80     info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
  81         & IOAPIC_DM_MASK;
  82     if (info->delivery_mode == IOAPIC_DM_EXTINT) {
  83         info->vector = pic_read_irq(isa_pic);
  84     } else {
  85         info->vector = entry & IOAPIC_VECTOR_MASK;
  86     }
  87
  88     info->addr = APIC_DEFAULT_ADDRESS | \
  89         (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
  90         (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
  91     info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
  92         (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
  93         (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
  94 }
  95
  96 static void ioapic_service(IOAPICCommonState *s)
  97 {
  98     AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
  99     struct ioapic_entry_info info;
 100     uint8_t i;
 101     uint32_t mask;
 102     uint64_t entry;
 103
 104     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 105         mask = 1 << i;
 106         if (s->irr & mask) {
 107             int coalesce = 0;
 108
 109             entry = s->ioredtbl[i];
 110             ioapic_entry_parse(entry, &info);
 111             if (!info.masked) {
 112                 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 113                     s->irr &= ~mask;
 114                 } else {
 115                     coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
 116                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 117                 }
 118
 119 #ifdef CONFIG_KVM
 120                 if (kvm_irqchip_is_split()) {
 121                     if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 122                         kvm_set_irq(kvm_state, i, 1);
 123                         kvm_set_irq(kvm_state, i, 0);
 124                     } else {
 125                         if (!coalesce) {
 126                             kvm_set_irq(kvm_state, i, 1);
 127                         }
 128                     }
 129                     continue;
 130                 }
 131 #else
 132                 (void)coalesce;
 133 #endif
 134                 /* No matter whether IR is enabled, we translate
 135                  * the IOAPIC message into a MSI one, and its
 136                  * address space will decide whether we need a
 137                  * translation. */
 138                 stl_le_phys(ioapic_as, info.addr, info.data);
 139             }
 140         }
 141     }
 142 }
 143
 144 static void ioapic_set_irq(void *opaque, int vector, int level)
 145 {
 146     IOAPICCommonState *s = opaque;
 147
 148     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 149      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 150      * the cleanest way of doing it but it should work. */
 151
 152     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 153     if (vector == 0) {
 154         vector = 2;
 155     }
 156     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 157         uint32_t mask = 1 << vector;
 158         uint64_t entry = s->ioredtbl[vector];
 159
 160         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 161             IOAPIC_TRIGGER_LEVEL) {
 162             /* level triggered */
 163             if (level) {
 164                 s->irr |= mask;
 165                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 166                     ioapic_service(s);
 167                 }
 168             } else {
 169                 s->irr &= ~mask;
 170             }
 171         } else {
 172             /* According to the 82093AA manual, we must ignore edge requests
 173              * if the input pin is masked. */
 174             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 175                 s->irr |= mask;
 176                 ioapic_service(s);
 177             }
 178         }
 179     }
 180 }
 181
 182 static void ioapic_update_kvm_routes(IOAPICCommonState *s)
 183 {
 184 #ifdef CONFIG_KVM
 185     int i;
 186
 187     if (kvm_irqchip_is_split()) {
 188         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 189             MSIMessage msg;
 190             struct ioapic_entry_info info;
 191             ioapic_entry_parse(s->ioredtbl[i], &info);
 192             msg.address = info.addr;
 193             msg.data = info.data;
 194             kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
 195         }
 196         kvm_irqchip_commit_routes(kvm_state);
 197     }
 198 #endif
 199 }
 200
 201 void ioapic_eoi_broadcast(int vector)
 202 {
 203     IOAPICCommonState *s;
 204     uint64_t entry;
 205     int i, n;
 206
 207     for (i = 0; i < MAX_IOAPICS; i++) {
 208         s = ioapics[i];
 209         if (!s) {
 210             continue;
 211         }
 212         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 213             entry = s->ioredtbl[n];
 214             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 215                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 216                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 217                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 218                     ioapic_service(s);
 219                 }
 220             }
 221         }
 222     }
 223 }
 224
 225 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 226 {
 227     int i;
 228
 229     for (i = 0; i < MAX_IOAPICS; i++) {
 230         if (ioapics[i] != 0) {
 231             ioapic_print_redtbl(mon, ioapics[i]);
 232         }
 233     }
 234 }
 235
 236 static uint64_t
 237 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 238 {
 239     IOAPICCommonState *s = opaque;
 240     int index;
 241     uint32_t val = 0;
 242
 243     switch (addr & 0xff) {
 244     case IOAPIC_IOREGSEL:
 245         val = s->ioregsel;
 246         break;
 247     case IOAPIC_IOWIN:
 248         if (size != 4) {
 249             break;
 250         }
 251         switch (s->ioregsel) {
 252         case IOAPIC_REG_ID:
 253         case IOAPIC_REG_ARB:
 254             val = s->id << IOAPIC_ID_SHIFT;
 255             break;
 256         case IOAPIC_REG_VER:
 257             val = IOAPIC_VERSION |
 258                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 259             break;
 260         default:
 261             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 262             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 263                 if (s->ioregsel & 1) {
 264                     val = s->ioredtbl[index] >> 32;
 265                 } else {
 266                     val = s->ioredtbl[index] & 0xffffffff;
 267                 }
 268             }
 269         }
 270         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 271         break;
 272     }
 273     return val;
 274 }
 275
 276 /*
 277  * This is to satisfy the hack in Linux kernel. One hack of it is to
 278  * simulate clearing the Remote IRR bit of IOAPIC entry using the
 279  * following:
 280  *
 281  * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
 282  * Otherwise, we simulate the EOI message manually by changing the trigger
 283  * mode to edge and then back to level, with RTE being masked during
 284  * this."
 285  *
 286  * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
 287  *
 288  * This is based on the assumption that, Remote IRR bit will be
 289  * cleared by IOAPIC hardware when configured as edge-triggered
 290  * interrupts.
 291  *
 292  * Without this, level-triggered interrupts in IR mode might fail to
 293  * work correctly.
 294  */
 295 static inline void
 296 ioapic_fix_edge_remote_irr(uint64_t *entry)
 297 {
 298     if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
 299         /* Edge-triggered interrupts, make sure remote IRR is zero */
 300         *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
 301     }
 302 }
 303
 304 static void
 305 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 306                  unsigned int size)
 307 {
 308     IOAPICCommonState *s = opaque;
 309     int index;
 310
 311     switch (addr & 0xff) {
 312     case IOAPIC_IOREGSEL:
 313         s->ioregsel = val;
 314         break;
 315     case IOAPIC_IOWIN:
 316         if (size != 4) {
 317             break;
 318         }
 319         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 320         switch (s->ioregsel) {
 321         case IOAPIC_REG_ID:
 322             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 323             break;
 324         case IOAPIC_REG_VER:
 325         case IOAPIC_REG_ARB:
 326             break;
 327         default:
 328             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 329             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 330                 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
 331                 if (s->ioregsel & 1) {
 332                     s->ioredtbl[index] &= 0xffffffff;
 333                     s->ioredtbl[index] |= (uint64_t)val << 32;
 334                 } else {
 335                     s->ioredtbl[index] &= ~0xffffffffULL;
 336                     s->ioredtbl[index] |= val;
 337                 }
 338                 /* restore RO bits */
 339                 s->ioredtbl[index] &= IOAPIC_RW_BITS;
 340                 s->ioredtbl[index] |= ro_bits;
 341                 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
 342                 ioapic_service(s);
 343             }
 344         }
 345         break;
 346     }
 347
 348     ioapic_update_kvm_routes(s);
 349 }
 350
 351 static const MemoryRegionOps ioapic_io_ops = {
 352     .read = ioapic_mem_read,
 353     .write = ioapic_mem_write,
 354     .endianness = DEVICE_NATIVE_ENDIAN,
 355 };
 356
 357 static void ioapic_realize(DeviceState *dev, Error **errp)
 358 {
 359     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 360
 361     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 362                           "ioapic", 0x1000);
 363
 364     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 365
 366     ioapics[ioapic_no] = s;
 367 }
 368
 369 static void ioapic_class_init(ObjectClass *klass, void *data)
 370 {
 371     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 372     DeviceClass *dc = DEVICE_CLASS(klass);
 373
 374     k->realize = ioapic_realize;
 375     dc->reset = ioapic_reset_common;
 376 }
 377
 378 static const TypeInfo ioapic_info = {
 379     .name          = "ioapic",
 380     .parent        = TYPE_IOAPIC_COMMON,
 381     .instance_size = sizeof(IOAPICCommonState),
 382     .class_init    = ioapic_class_init,
 383 };
 384
 385 static void ioapic_register_types(void)
 386 {
 387     type_register_static(&ioapic_info);
 388 }
 389
 390 type_init(ioapic_register_types)