4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
14 #include "internals.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/host-utils.h"
17 #include "qemu/main-loop.h"
18 #include "qemu/timer.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
36 #include "semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 static void switch_mode(CPUARMState
*env
, int mode
);
44 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
46 assert(ri
->fieldoffset
);
47 if (cpreg_field_is_64bit(ri
)) {
48 return CPREG_FIELD64(env
, ri
);
50 return CPREG_FIELD32(env
, ri
);
54 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
56 assert(ri
->fieldoffset
);
57 if (cpreg_field_is_64bit(ri
)) {
58 CPREG_FIELD64(env
, ri
) = value
;
60 CPREG_FIELD32(env
, ri
) = value
;
64 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
66 return (char *)env
+ ri
->fieldoffset
;
69 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
71 /* Raw read of a coprocessor register (as needed for migration, etc). */
72 if (ri
->type
& ARM_CP_CONST
) {
73 return ri
->resetvalue
;
74 } else if (ri
->raw_readfn
) {
75 return ri
->raw_readfn(env
, ri
);
76 } else if (ri
->readfn
) {
77 return ri
->readfn(env
, ri
);
79 return raw_read(env
, ri
);
83 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
86 /* Raw write of a coprocessor register (as needed for migration, etc).
87 * Note that constant registers are treated as write-ignored; the
88 * caller should check for success by whether a readback gives the
91 if (ri
->type
& ARM_CP_CONST
) {
93 } else if (ri
->raw_writefn
) {
94 ri
->raw_writefn(env
, ri
, v
);
95 } else if (ri
->writefn
) {
96 ri
->writefn(env
, ri
, v
);
98 raw_write(env
, ri
, v
);
102 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
104 /* Return true if the regdef would cause an assertion if you called
105 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
106 * program bug for it not to have the NO_RAW flag).
107 * NB that returning false here doesn't necessarily mean that calling
108 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
109 * read/write access functions which are safe for raw use" from "has
110 * read/write access functions which have side effects but has forgotten
111 * to provide raw access functions".
112 * The tests here line up with the conditions in read/write_raw_cp_reg()
113 * and assertions in raw_read()/raw_write().
115 if ((ri
->type
& ARM_CP_CONST
) ||
117 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
123 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
125 /* Write the coprocessor state from cpu->env to the (index,value) list. */
129 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
130 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
131 const ARMCPRegInfo
*ri
;
134 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
139 if (ri
->type
& ARM_CP_NO_RAW
) {
143 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
146 * Only sync if the previous list->cpustate sync succeeded.
147 * Rather than tracking the success/failure state for every
148 * item in the list, we just recheck "does the raw write we must
149 * have made in write_list_to_cpustate() read back OK" here.
151 uint64_t oldval
= cpu
->cpreg_values
[i
];
153 if (oldval
== newval
) {
157 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
158 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
162 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
164 cpu
->cpreg_values
[i
] = newval
;
169 bool write_list_to_cpustate(ARMCPU
*cpu
)
174 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
175 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
176 uint64_t v
= cpu
->cpreg_values
[i
];
177 const ARMCPRegInfo
*ri
;
179 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
184 if (ri
->type
& ARM_CP_NO_RAW
) {
187 /* Write value and confirm it reads back as written
188 * (to catch read-only registers and partially read-only
189 * registers where the incoming migration value doesn't match)
191 write_raw_cp_reg(&cpu
->env
, ri
, v
);
192 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
199 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
201 ARMCPU
*cpu
= opaque
;
202 uint32_t regidx
= (uintptr_t)key
;
203 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
205 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
206 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
207 /* The value array need not be initialized at this point */
208 cpu
->cpreg_array_len
++;
212 static void count_cpreg(gpointer key
, gpointer opaque
)
214 ARMCPU
*cpu
= opaque
;
215 const ARMCPRegInfo
*ri
;
217 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
219 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
220 cpu
->cpreg_array_len
++;
224 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
226 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
227 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
238 void init_cpreg_list(ARMCPU
*cpu
)
240 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
241 * Note that we require cpreg_tuples[] to be sorted by key ID.
246 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
247 keys
= g_list_sort(keys
, cpreg_key_compare
);
249 cpu
->cpreg_array_len
= 0;
251 g_list_foreach(keys
, count_cpreg
, cpu
);
253 arraylen
= cpu
->cpreg_array_len
;
254 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
257 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
258 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
259 cpu
->cpreg_array_len
= 0;
261 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
263 assert(cpu
->cpreg_array_len
== arraylen
);
269 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
271 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
272 const ARMCPRegInfo
*ri
,
275 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
276 arm_is_secure_below_el3(env
)) {
277 return CP_ACCESS_TRAP_UNCATEGORIZED
;
282 /* Some secure-only AArch32 registers trap to EL3 if used from
283 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
284 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
285 * We assume that the .access field is set to PL1_RW.
287 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
288 const ARMCPRegInfo
*ri
,
291 if (arm_current_el(env
) == 3) {
294 if (arm_is_secure_below_el3(env
)) {
295 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
296 return CP_ACCESS_TRAP_EL2
;
298 return CP_ACCESS_TRAP_EL3
;
300 /* This will be EL1 NS and EL2 NS, which just UNDEF */
301 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 /* Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
367 ARMCPU
*cpu
= env_archcpu(env
);
369 raw_write(env
, ri
, value
);
370 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
373 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
375 ARMCPU
*cpu
= env_archcpu(env
);
377 if (raw_read(env
, ri
) != value
) {
378 /* Unlike real hardware the qemu TLB uses virtual addresses,
379 * not modified virtual addresses, so this causes a TLB flush.
382 raw_write(env
, ri
, value
);
386 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
389 ARMCPU
*cpu
= env_archcpu(env
);
391 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
392 && !extended_addresses_enabled(env
)) {
393 /* For VMSA (when not using the LPAE long descriptor page table
394 * format) this register includes the ASID, so do a TLB flush.
395 * For PMSA it is purely a process ID and no action is needed.
399 raw_write(env
, ri
, value
);
402 /* IS variants of TLB operations must affect all cores */
403 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 CPUState
*cs
= env_cpu(env
);
408 tlb_flush_all_cpus_synced(cs
);
411 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 CPUState
*cs
= env_cpu(env
);
416 tlb_flush_all_cpus_synced(cs
);
419 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
422 CPUState
*cs
= env_cpu(env
);
424 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
427 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
430 CPUState
*cs
= env_cpu(env
);
432 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
436 * Non-IS variants of TLB operations are upgraded to
437 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
438 * force broadcast of these operations.
440 static bool tlb_force_broadcast(CPUARMState
*env
)
442 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
445 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
448 /* Invalidate all (TLBIALL) */
449 CPUState
*cs
= env_cpu(env
);
451 if (tlb_force_broadcast(env
)) {
452 tlb_flush_all_cpus_synced(cs
);
458 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
461 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
462 CPUState
*cs
= env_cpu(env
);
464 value
&= TARGET_PAGE_MASK
;
465 if (tlb_force_broadcast(env
)) {
466 tlb_flush_page_all_cpus_synced(cs
, value
);
468 tlb_flush_page(cs
, value
);
472 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 /* Invalidate by ASID (TLBIASID) */
476 CPUState
*cs
= env_cpu(env
);
478 if (tlb_force_broadcast(env
)) {
479 tlb_flush_all_cpus_synced(cs
);
485 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
489 CPUState
*cs
= env_cpu(env
);
491 value
&= TARGET_PAGE_MASK
;
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_page_all_cpus_synced(cs
, value
);
495 tlb_flush_page(cs
, value
);
499 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 CPUState
*cs
= env_cpu(env
);
504 tlb_flush_by_mmuidx(cs
,
506 ARMMMUIdxBit_E10_1_PAN
|
510 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
513 CPUState
*cs
= env_cpu(env
);
515 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
517 ARMMMUIdxBit_E10_1_PAN
|
522 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
525 CPUState
*cs
= env_cpu(env
);
527 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
530 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
533 CPUState
*cs
= env_cpu(env
);
535 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
538 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 CPUState
*cs
= env_cpu(env
);
542 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
544 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
547 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 CPUState
*cs
= env_cpu(env
);
551 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
553 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
557 static const ARMCPRegInfo cp_reginfo
[] = {
558 /* Define the secure and non-secure FCSE identifier CP registers
559 * separately because there is no secure bank in V8 (no _EL3). This allows
560 * the secure register to be properly reset and migrated. There is also no
561 * v8 EL1 version of the register so the non-secure instance stands alone.
564 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
565 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
566 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
567 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
568 { .name
= "FCSEIDR_S",
569 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
570 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
571 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
572 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
573 /* Define the secure and non-secure context identifier CP registers
574 * separately because there is no secure bank in V8 (no _EL3). This allows
575 * the secure register to be properly reset and migrated. In the
576 * non-secure case, the 32-bit register will have reset and migration
577 * disabled during registration as it is handled by the 64-bit instance.
579 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
580 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
581 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
582 .secure
= ARM_CP_SECSTATE_NS
,
583 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
584 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
585 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
586 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
587 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
588 .secure
= ARM_CP_SECSTATE_S
,
589 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
590 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
593 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
594 /* NB: Some of these registers exist in v8 but with more precise
595 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
597 /* MMU Domain access control / MPU write buffer control */
599 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
600 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
601 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
602 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
603 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
604 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
605 * For v6 and v5, these mappings are overly broad.
607 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
608 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
609 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
610 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
611 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
612 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
613 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
614 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
615 /* Cache maintenance ops; some of this space may be overridden later. */
616 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
617 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
618 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
621 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
622 /* Not all pre-v6 cores implemented this WFI, so this is slightly
625 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
626 .access
= PL1_W
, .type
= ARM_CP_WFI
},
629 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
630 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
631 * is UNPREDICTABLE; we choose to NOP as most implementations do).
633 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
634 .access
= PL1_W
, .type
= ARM_CP_WFI
},
635 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
636 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
637 * OMAPCP will override this space.
639 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
640 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
642 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
645 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
646 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
647 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
649 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
650 * implementing it as RAZ means the "debug architecture version" bits
651 * will read as a reserved value, which should cause Linux to not try
652 * to use the debug hardware.
654 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
655 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
656 /* MMU TLB control. Note that the wildcarding means we cover not just
657 * the unified TLB ops but also the dside/iside/inner-shareable variants.
659 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
660 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
661 .type
= ARM_CP_NO_RAW
},
662 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
663 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
664 .type
= ARM_CP_NO_RAW
},
665 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
666 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
667 .type
= ARM_CP_NO_RAW
},
668 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
669 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
670 .type
= ARM_CP_NO_RAW
},
671 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
672 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
674 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
677 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
682 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
683 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
684 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
685 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
686 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
688 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
689 /* VFP coprocessor: cp10 & cp11 [23:20] */
690 mask
|= R_CPACR_ASEDIS_MASK
|
691 R_CPACR_D32DIS_MASK
|
695 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
696 /* ASEDIS [31] bit is RAO/WI */
697 value
|= R_CPACR_ASEDIS_MASK
;
700 /* VFPv3 and upwards with NEON implement 32 double precision
701 * registers (D0-D31).
703 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
704 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
705 value
|= R_CPACR_D32DIS_MASK
;
712 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
713 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
715 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
716 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
717 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
718 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
721 env
->cp15
.cpacr_el1
= value
;
724 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
727 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
728 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
730 uint64_t value
= env
->cp15
.cpacr_el1
;
732 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
733 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
734 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
740 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
742 /* Call cpacr_write() so that we reset with the correct RAO bits set
743 * for our CPU features.
745 cpacr_write(env
, ri
, 0);
748 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
751 if (arm_feature(env
, ARM_FEATURE_V8
)) {
752 /* Check if CPACR accesses are to be trapped to EL2 */
753 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
754 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
755 return CP_ACCESS_TRAP_EL2
;
756 /* Check if CPACR accesses are to be trapped to EL3 */
757 } else if (arm_current_el(env
) < 3 &&
758 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
759 return CP_ACCESS_TRAP_EL3
;
766 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
769 /* Check if CPTR accesses are set to trap to EL3 */
770 if (arm_current_el(env
) == 2 &&
771 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
772 return CP_ACCESS_TRAP_EL3
;
778 static const ARMCPRegInfo v6_cp_reginfo
[] = {
779 /* prefetch by MVA in v6, NOP in v7 */
780 { .name
= "MVA_prefetch",
781 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
782 .access
= PL1_W
, .type
= ARM_CP_NOP
},
783 /* We need to break the TB after ISB to execute self-modifying code
784 * correctly and also to take any pending interrupts immediately.
785 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
787 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
788 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
789 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
790 .access
= PL0_W
, .type
= ARM_CP_NOP
},
791 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
792 .access
= PL0_W
, .type
= ARM_CP_NOP
},
793 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
794 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
795 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
796 offsetof(CPUARMState
, cp15
.ifar_ns
) },
798 /* Watchpoint Fault Address Register : should actually only be present
799 * for 1136, 1176, 11MPCore.
801 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
802 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
803 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
804 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
805 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
806 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
809 typedef struct pm_event
{
810 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
811 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
812 bool (*supported
)(CPUARMState
*);
814 * Retrieve the current count of the underlying event. The programmed
815 * counters hold a difference from the return value from this function
817 uint64_t (*get_count
)(CPUARMState
*);
819 * Return how many nanoseconds it will take (at a minimum) for count events
820 * to occur. A negative value indicates the counter will never overflow, or
821 * that the counter has otherwise arranged for the overflow bit to be set
822 * and the PMU interrupt to be raised on overflow.
824 int64_t (*ns_per_count
)(uint64_t);
827 static bool event_always_supported(CPUARMState
*env
)
832 static uint64_t swinc_get_count(CPUARMState
*env
)
835 * SW_INCR events are written directly to the pmevcntr's by writes to
836 * PMSWINC, so there is no underlying count maintained by the PMU itself
841 static int64_t swinc_ns_per(uint64_t ignored
)
847 * Return the underlying cycle count for the PMU cycle counters. If we're in
848 * usermode, simply return 0.
850 static uint64_t cycles_get_count(CPUARMState
*env
)
852 #ifndef CONFIG_USER_ONLY
853 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
854 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
856 return cpu_get_host_ticks();
860 #ifndef CONFIG_USER_ONLY
861 static int64_t cycles_ns_per(uint64_t cycles
)
863 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
866 static bool instructions_supported(CPUARMState
*env
)
868 return icount_enabled() == 1; /* Precise instruction counting */
871 static uint64_t instructions_get_count(CPUARMState
*env
)
873 return (uint64_t)icount_get_raw();
876 static int64_t instructions_ns_per(uint64_t icount
)
878 return icount_to_ns((int64_t)icount
);
882 static bool pmu_8_1_events_supported(CPUARMState
*env
)
884 /* For events which are supported in any v8.1 PMU */
885 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
888 static bool pmu_8_4_events_supported(CPUARMState
*env
)
890 /* For events which are supported in any v8.1 PMU */
891 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
894 static uint64_t zero_event_get_count(CPUARMState
*env
)
896 /* For events which on QEMU never fire, so their count is always zero */
900 static int64_t zero_event_ns_per(uint64_t cycles
)
902 /* An event which never fires can never overflow */
906 static const pm_event pm_events
[] = {
907 { .number
= 0x000, /* SW_INCR */
908 .supported
= event_always_supported
,
909 .get_count
= swinc_get_count
,
910 .ns_per_count
= swinc_ns_per
,
912 #ifndef CONFIG_USER_ONLY
913 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
914 .supported
= instructions_supported
,
915 .get_count
= instructions_get_count
,
916 .ns_per_count
= instructions_ns_per
,
918 { .number
= 0x011, /* CPU_CYCLES, Cycle */
919 .supported
= event_always_supported
,
920 .get_count
= cycles_get_count
,
921 .ns_per_count
= cycles_ns_per
,
924 { .number
= 0x023, /* STALL_FRONTEND */
925 .supported
= pmu_8_1_events_supported
,
926 .get_count
= zero_event_get_count
,
927 .ns_per_count
= zero_event_ns_per
,
929 { .number
= 0x024, /* STALL_BACKEND */
930 .supported
= pmu_8_1_events_supported
,
931 .get_count
= zero_event_get_count
,
932 .ns_per_count
= zero_event_ns_per
,
934 { .number
= 0x03c, /* STALL */
935 .supported
= pmu_8_4_events_supported
,
936 .get_count
= zero_event_get_count
,
937 .ns_per_count
= zero_event_ns_per
,
942 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
943 * events (i.e. the statistical profiling extension), this implementation
944 * should first be updated to something sparse instead of the current
945 * supported_event_map[] array.
947 #define MAX_EVENT_ID 0x3c
948 #define UNSUPPORTED_EVENT UINT16_MAX
949 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
952 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
953 * of ARM event numbers to indices in our pm_events array.
955 * Note: Events in the 0x40XX range are not currently supported.
957 void pmu_init(ARMCPU
*cpu
)
962 * Empty supported_event_map and cpu->pmceid[01] before adding supported
965 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
966 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
971 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
972 const pm_event
*cnt
= &pm_events
[i
];
973 assert(cnt
->number
<= MAX_EVENT_ID
);
974 /* We do not currently support events in the 0x40xx range */
975 assert(cnt
->number
<= 0x3f);
977 if (cnt
->supported(&cpu
->env
)) {
978 supported_event_map
[cnt
->number
] = i
;
979 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
980 if (cnt
->number
& 0x20) {
981 cpu
->pmceid1
|= event_mask
;
983 cpu
->pmceid0
|= event_mask
;
990 * Check at runtime whether a PMU event is supported for the current machine
992 static bool event_supported(uint16_t number
)
994 if (number
> MAX_EVENT_ID
) {
997 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1000 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1003 /* Performance monitor registers user accessibility is controlled
1004 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1005 * trapping to EL2 or EL3 for other accesses.
1007 int el
= arm_current_el(env
);
1008 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1010 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1011 return CP_ACCESS_TRAP
;
1013 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1014 return CP_ACCESS_TRAP_EL2
;
1016 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1017 return CP_ACCESS_TRAP_EL3
;
1020 return CP_ACCESS_OK
;
1023 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1024 const ARMCPRegInfo
*ri
,
1027 /* ER: event counter read trap control */
1028 if (arm_feature(env
, ARM_FEATURE_V8
)
1029 && arm_current_el(env
) == 0
1030 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1032 return CP_ACCESS_OK
;
1035 return pmreg_access(env
, ri
, isread
);
1038 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1039 const ARMCPRegInfo
*ri
,
1042 /* SW: software increment write trap control */
1043 if (arm_feature(env
, ARM_FEATURE_V8
)
1044 && arm_current_el(env
) == 0
1045 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1047 return CP_ACCESS_OK
;
1050 return pmreg_access(env
, ri
, isread
);
1053 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1054 const ARMCPRegInfo
*ri
,
1057 /* ER: event counter read trap control */
1058 if (arm_feature(env
, ARM_FEATURE_V8
)
1059 && arm_current_el(env
) == 0
1060 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1061 return CP_ACCESS_OK
;
1064 return pmreg_access(env
, ri
, isread
);
1067 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1068 const ARMCPRegInfo
*ri
,
1071 /* CR: cycle counter read trap control */
1072 if (arm_feature(env
, ARM_FEATURE_V8
)
1073 && arm_current_el(env
) == 0
1074 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1076 return CP_ACCESS_OK
;
1079 return pmreg_access(env
, ri
, isread
);
1082 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1083 * the current EL, security state, and register configuration.
1085 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1088 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1089 bool enabled
, prohibited
, filtered
;
1090 bool secure
= arm_is_secure(env
);
1091 int el
= arm_current_el(env
);
1092 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1093 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1095 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1099 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1100 (counter
< hpmn
|| counter
== 31)) {
1101 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1103 e
= mdcr_el2
& MDCR_HPME
;
1105 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1108 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1109 prohibited
= mdcr_el2
& MDCR_HPMD
;
1114 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1115 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1118 if (prohibited
&& counter
== 31) {
1119 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1122 if (counter
== 31) {
1123 filter
= env
->cp15
.pmccfiltr_el0
;
1125 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1128 p
= filter
& PMXEVTYPER_P
;
1129 u
= filter
& PMXEVTYPER_U
;
1130 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1131 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1132 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1133 m
= arm_el_is_aa64(env
, 1) &&
1134 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1137 filtered
= secure
? u
: u
!= nsu
;
1138 } else if (el
== 1) {
1139 filtered
= secure
? p
: p
!= nsk
;
1140 } else if (el
== 2) {
1146 if (counter
!= 31) {
1148 * If not checking PMCCNTR, ensure the counter is setup to an event we
1151 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1152 if (!event_supported(event
)) {
1157 return enabled
&& !prohibited
&& !filtered
;
1160 static void pmu_update_irq(CPUARMState
*env
)
1162 ARMCPU
*cpu
= env_archcpu(env
);
1163 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1164 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1168 * Ensure c15_ccnt is the guest-visible count so that operations such as
1169 * enabling/disabling the counter or filtering, modifying the count itself,
1170 * etc. can be done logically. This is essentially a no-op if the counter is
1171 * not enabled at the time of the call.
1173 static void pmccntr_op_start(CPUARMState
*env
)
1175 uint64_t cycles
= cycles_get_count(env
);
1177 if (pmu_counter_enabled(env
, 31)) {
1178 uint64_t eff_cycles
= cycles
;
1179 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1180 /* Increment once every 64 processor clock cycles */
1184 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1186 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1187 1ull << 63 : 1ull << 31;
1188 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1189 env
->cp15
.c9_pmovsr
|= (1 << 31);
1190 pmu_update_irq(env
);
1193 env
->cp15
.c15_ccnt
= new_pmccntr
;
1195 env
->cp15
.c15_ccnt_delta
= cycles
;
1199 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1200 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1203 static void pmccntr_op_finish(CPUARMState
*env
)
1205 if (pmu_counter_enabled(env
, 31)) {
1206 #ifndef CONFIG_USER_ONLY
1207 /* Calculate when the counter will next overflow */
1208 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1209 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1210 remaining_cycles
= (uint32_t)remaining_cycles
;
1212 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1214 if (overflow_in
> 0) {
1215 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1217 ARMCPU
*cpu
= env_archcpu(env
);
1218 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1222 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1223 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1224 /* Increment once every 64 processor clock cycles */
1227 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1231 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1234 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1236 if (event_supported(event
)) {
1237 uint16_t event_idx
= supported_event_map
[event
];
1238 count
= pm_events
[event_idx
].get_count(env
);
1241 if (pmu_counter_enabled(env
, counter
)) {
1242 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1244 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1245 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1246 pmu_update_irq(env
);
1248 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1250 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1253 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1255 if (pmu_counter_enabled(env
, counter
)) {
1256 #ifndef CONFIG_USER_ONLY
1257 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1258 uint16_t event_idx
= supported_event_map
[event
];
1259 uint64_t delta
= UINT32_MAX
-
1260 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1261 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1263 if (overflow_in
> 0) {
1264 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1266 ARMCPU
*cpu
= env_archcpu(env
);
1267 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1271 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1272 env
->cp15
.c14_pmevcntr
[counter
];
1276 void pmu_op_start(CPUARMState
*env
)
1279 pmccntr_op_start(env
);
1280 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1281 pmevcntr_op_start(env
, i
);
1285 void pmu_op_finish(CPUARMState
*env
)
1288 pmccntr_op_finish(env
);
1289 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1290 pmevcntr_op_finish(env
, i
);
1294 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1296 pmu_op_start(&cpu
->env
);
1299 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1301 pmu_op_finish(&cpu
->env
);
1304 void arm_pmu_timer_cb(void *opaque
)
1306 ARMCPU
*cpu
= opaque
;
1309 * Update all the counter values based on the current underlying counts,
1310 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1311 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1312 * counter may expire.
1314 pmu_op_start(&cpu
->env
);
1315 pmu_op_finish(&cpu
->env
);
1318 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1323 if (value
& PMCRC
) {
1324 /* The counter has been reset */
1325 env
->cp15
.c15_ccnt
= 0;
1328 if (value
& PMCRP
) {
1330 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1331 env
->cp15
.c14_pmevcntr
[i
] = 0;
1335 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1336 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1341 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1345 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1346 /* Increment a counter's count iff: */
1347 if ((value
& (1 << i
)) && /* counter's bit is set */
1348 /* counter is enabled and not filtered */
1349 pmu_counter_enabled(env
, i
) &&
1350 /* counter is SW_INCR */
1351 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1352 pmevcntr_op_start(env
, i
);
1355 * Detect if this write causes an overflow since we can't predict
1356 * PMSWINC overflows like we can for other events
1358 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1360 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1361 env
->cp15
.c9_pmovsr
|= (1 << i
);
1362 pmu_update_irq(env
);
1365 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1367 pmevcntr_op_finish(env
, i
);
1372 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1375 pmccntr_op_start(env
);
1376 ret
= env
->cp15
.c15_ccnt
;
1377 pmccntr_op_finish(env
);
1381 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1384 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1385 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1386 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1389 env
->cp15
.c9_pmselr
= value
& 0x1f;
1392 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1395 pmccntr_op_start(env
);
1396 env
->cp15
.c15_ccnt
= value
;
1397 pmccntr_op_finish(env
);
1400 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1403 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1405 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1408 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1411 pmccntr_op_start(env
);
1412 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1413 pmccntr_op_finish(env
);
1416 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1419 pmccntr_op_start(env
);
1420 /* M is not accessible from AArch32 */
1421 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1422 (value
& PMCCFILTR
);
1423 pmccntr_op_finish(env
);
1426 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1428 /* M is not visible in AArch32 */
1429 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1432 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1435 value
&= pmu_counter_mask(env
);
1436 env
->cp15
.c9_pmcnten
|= value
;
1439 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1442 value
&= pmu_counter_mask(env
);
1443 env
->cp15
.c9_pmcnten
&= ~value
;
1446 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1449 value
&= pmu_counter_mask(env
);
1450 env
->cp15
.c9_pmovsr
&= ~value
;
1451 pmu_update_irq(env
);
1454 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1457 value
&= pmu_counter_mask(env
);
1458 env
->cp15
.c9_pmovsr
|= value
;
1459 pmu_update_irq(env
);
1462 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1463 uint64_t value
, const uint8_t counter
)
1465 if (counter
== 31) {
1466 pmccfiltr_write(env
, ri
, value
);
1467 } else if (counter
< pmu_num_counters(env
)) {
1468 pmevcntr_op_start(env
, counter
);
1471 * If this counter's event type is changing, store the current
1472 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1473 * pmevcntr_op_finish has the correct baseline when it converts back to
1476 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1477 PMXEVTYPER_EVTCOUNT
;
1478 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1479 if (old_event
!= new_event
) {
1481 if (event_supported(new_event
)) {
1482 uint16_t event_idx
= supported_event_map
[new_event
];
1483 count
= pm_events
[event_idx
].get_count(env
);
1485 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1488 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1489 pmevcntr_op_finish(env
, counter
);
1491 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1492 * PMSELR value is equal to or greater than the number of implemented
1493 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1497 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1498 const uint8_t counter
)
1500 if (counter
== 31) {
1501 return env
->cp15
.pmccfiltr_el0
;
1502 } else if (counter
< pmu_num_counters(env
)) {
1503 return env
->cp15
.c14_pmevtyper
[counter
];
1506 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1507 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1513 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1516 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1517 pmevtyper_write(env
, ri
, value
, counter
);
1520 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1523 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1524 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1527 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1528 * pmu_op_finish calls when loading saved state for a migration. Because
1529 * we're potentially updating the type of event here, the value written to
1530 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1531 * different counter type. Therefore, we need to set this value to the
1532 * current count for the counter type we're writing so that pmu_op_finish
1533 * has the correct count for its calculation.
1535 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1536 if (event_supported(event
)) {
1537 uint16_t event_idx
= supported_event_map
[event
];
1538 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1539 pm_events
[event_idx
].get_count(env
);
1543 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1545 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1546 return pmevtyper_read(env
, ri
, counter
);
1549 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1552 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1555 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1557 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1560 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1561 uint64_t value
, uint8_t counter
)
1563 if (counter
< pmu_num_counters(env
)) {
1564 pmevcntr_op_start(env
, counter
);
1565 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1566 pmevcntr_op_finish(env
, counter
);
1569 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1570 * are CONSTRAINED UNPREDICTABLE.
1574 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1577 if (counter
< pmu_num_counters(env
)) {
1579 pmevcntr_op_start(env
, counter
);
1580 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1581 pmevcntr_op_finish(env
, counter
);
1584 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1585 * are CONSTRAINED UNPREDICTABLE. */
1590 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1593 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1594 pmevcntr_write(env
, ri
, value
, counter
);
1597 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1599 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1600 return pmevcntr_read(env
, ri
, counter
);
1603 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1606 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1607 assert(counter
< pmu_num_counters(env
));
1608 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1609 pmevcntr_write(env
, ri
, value
, counter
);
1612 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1614 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1615 assert(counter
< pmu_num_counters(env
));
1616 return env
->cp15
.c14_pmevcntr
[counter
];
1619 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1622 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1625 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1627 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1630 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1633 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1634 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1636 env
->cp15
.c9_pmuserenr
= value
& 1;
1640 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1643 /* We have no event counters so only the C bit can be changed */
1644 value
&= pmu_counter_mask(env
);
1645 env
->cp15
.c9_pminten
|= value
;
1646 pmu_update_irq(env
);
1649 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1652 value
&= pmu_counter_mask(env
);
1653 env
->cp15
.c9_pminten
&= ~value
;
1654 pmu_update_irq(env
);
1657 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1660 /* Note that even though the AArch64 view of this register has bits
1661 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1662 * architectural requirements for bits which are RES0 only in some
1663 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1664 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1666 raw_write(env
, ri
, value
& ~0x1FULL
);
1669 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1671 /* Begin with base v8.0 state. */
1672 uint32_t valid_mask
= 0x3fff;
1673 ARMCPU
*cpu
= env_archcpu(env
);
1676 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1677 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1678 * Instead, choose the format based on the mode of EL3.
1680 if (arm_el_is_aa64(env
, 3)) {
1681 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1682 valid_mask
&= ~SCR_NET
; /* RES0 */
1684 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1685 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1686 value
|= SCR_RW
; /* RAO/WI */
1688 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1689 valid_mask
|= SCR_TERR
;
1691 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1692 valid_mask
|= SCR_TLOR
;
1694 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1695 valid_mask
|= SCR_API
| SCR_APK
;
1697 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1698 valid_mask
|= SCR_EEL2
;
1700 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1701 valid_mask
|= SCR_ATA
;
1703 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1704 valid_mask
|= SCR_ENSCXT
;
1706 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1707 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1710 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1711 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1712 valid_mask
|= SCR_TERR
;
1716 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1717 valid_mask
&= ~SCR_HCE
;
1719 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1720 * supported if EL2 exists. The bit is UNK/SBZP when
1721 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1722 * when EL2 is unavailable.
1723 * On ARMv8, this bit is always available.
1725 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1726 !arm_feature(env
, ARM_FEATURE_V8
)) {
1727 valid_mask
&= ~SCR_SMD
;
1731 /* Clear all-context RES0 bits. */
1732 value
&= valid_mask
;
1733 raw_write(env
, ri
, value
);
1736 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1739 * scr_write will set the RES1 bits on an AArch64-only CPU.
1740 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1742 scr_write(env
, ri
, 0);
1745 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1746 const ARMCPRegInfo
*ri
,
1749 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1750 return CP_ACCESS_TRAP_EL2
;
1753 return CP_ACCESS_OK
;
1756 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1758 ARMCPU
*cpu
= env_archcpu(env
);
1760 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1763 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1764 ri
->secure
& ARM_CP_SECSTATE_S
);
1766 return cpu
->ccsidr
[index
];
1769 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1772 raw_write(env
, ri
, value
& 0xf);
1775 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1777 CPUState
*cs
= env_cpu(env
);
1778 bool el1
= arm_current_el(env
) == 1;
1779 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1782 if (hcr_el2
& HCR_IMO
) {
1783 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1787 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1792 if (hcr_el2
& HCR_FMO
) {
1793 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1797 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1802 if (hcr_el2
& HCR_AMO
) {
1803 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1811 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1814 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1815 return CP_ACCESS_TRAP_EL2
;
1818 return CP_ACCESS_OK
;
1821 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1824 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1825 return access_aa64_tid1(env
, ri
, isread
);
1828 return CP_ACCESS_OK
;
1831 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1832 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1833 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1834 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1835 /* Performance monitors are implementation defined in v7,
1836 * but with an ARM recommended set of registers, which we
1839 * Performance registers fall into three categories:
1840 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1841 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1842 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1843 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1844 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1846 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1847 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1848 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1849 .writefn
= pmcntenset_write
,
1850 .accessfn
= pmreg_access
,
1851 .raw_writefn
= raw_write
},
1852 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1853 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1854 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1855 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1856 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1857 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1859 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1860 .accessfn
= pmreg_access
,
1861 .writefn
= pmcntenclr_write
,
1862 .type
= ARM_CP_ALIAS
},
1863 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1864 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1865 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1866 .type
= ARM_CP_ALIAS
,
1867 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1868 .writefn
= pmcntenclr_write
},
1869 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1870 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1871 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1872 .accessfn
= pmreg_access
,
1873 .writefn
= pmovsr_write
,
1874 .raw_writefn
= raw_write
},
1875 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1876 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1877 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1878 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1879 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1880 .writefn
= pmovsr_write
,
1881 .raw_writefn
= raw_write
},
1882 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1883 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1884 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1885 .writefn
= pmswinc_write
},
1886 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1887 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1888 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1889 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1890 .writefn
= pmswinc_write
},
1891 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1892 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1893 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1894 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1895 .raw_writefn
= raw_write
},
1896 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1897 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1898 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1899 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1900 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1901 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1902 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1903 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1904 .accessfn
= pmreg_access_ccntr
},
1905 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1906 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1907 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1909 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1910 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1911 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1912 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1913 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
1914 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1915 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1917 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1918 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1919 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
1920 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1922 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1924 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1925 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1926 .accessfn
= pmreg_access
,
1927 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1928 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1929 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1930 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1931 .accessfn
= pmreg_access
,
1932 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1933 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1934 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1935 .accessfn
= pmreg_access_xevcntr
,
1936 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
1937 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1938 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
1939 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1940 .accessfn
= pmreg_access_xevcntr
,
1941 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
1942 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1943 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1944 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
1946 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1947 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1948 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1949 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1950 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1952 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1953 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1954 .access
= PL1_RW
, .accessfn
= access_tpm
,
1955 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1956 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1958 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1959 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1960 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1961 .access
= PL1_RW
, .accessfn
= access_tpm
,
1963 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1964 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1965 .resetvalue
= 0x0 },
1966 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1967 .access
= PL1_RW
, .accessfn
= access_tpm
,
1968 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
1969 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1970 .writefn
= pmintenclr_write
, },
1971 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1972 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1973 .access
= PL1_RW
, .accessfn
= access_tpm
,
1974 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
1975 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1976 .writefn
= pmintenclr_write
},
1977 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1978 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1980 .accessfn
= access_aa64_tid2
,
1981 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1982 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1983 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1985 .accessfn
= access_aa64_tid2
,
1986 .writefn
= csselr_write
, .resetvalue
= 0,
1987 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1988 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1989 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1990 * just RAZ for all cores:
1992 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1993 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1994 .access
= PL1_R
, .type
= ARM_CP_CONST
,
1995 .accessfn
= access_aa64_tid1
,
1997 /* Auxiliary fault status registers: these also are IMPDEF, and we
1998 * choose to RAZ/WI for all cores.
2000 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2001 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2002 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2003 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2004 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2005 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2006 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2007 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2008 /* MAIR can just read-as-written because we don't implement caches
2009 * and so don't need to care about memory attributes.
2011 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2012 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2013 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2014 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2016 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2017 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2018 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2020 /* For non-long-descriptor page tables these are PRRR and NMRR;
2021 * regardless they still act as reads-as-written for QEMU.
2023 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2024 * allows them to assign the correct fieldoffset based on the endianness
2025 * handled in the field definitions.
2027 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2028 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2029 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2030 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2031 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2032 .resetfn
= arm_cp_reset_ignore
},
2033 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2034 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2035 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2036 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2037 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2038 .resetfn
= arm_cp_reset_ignore
},
2039 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2040 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2041 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2042 /* 32 bit ITLB invalidates */
2043 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2044 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2045 .writefn
= tlbiall_write
},
2046 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2047 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2048 .writefn
= tlbimva_write
},
2049 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2050 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2051 .writefn
= tlbiasid_write
},
2052 /* 32 bit DTLB invalidates */
2053 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2054 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2055 .writefn
= tlbiall_write
},
2056 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2057 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2058 .writefn
= tlbimva_write
},
2059 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2060 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2061 .writefn
= tlbiasid_write
},
2062 /* 32 bit TLB invalidates */
2063 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2064 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2065 .writefn
= tlbiall_write
},
2066 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2067 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2068 .writefn
= tlbimva_write
},
2069 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2070 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2071 .writefn
= tlbiasid_write
},
2072 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2073 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2074 .writefn
= tlbimvaa_write
},
2077 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2078 /* 32 bit TLB invalidates, Inner Shareable */
2079 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2080 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2081 .writefn
= tlbiall_is_write
},
2082 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2083 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2084 .writefn
= tlbimva_is_write
},
2085 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2086 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2087 .writefn
= tlbiasid_is_write
},
2088 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2089 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2090 .writefn
= tlbimvaa_is_write
},
2093 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2094 /* PMOVSSET is not implemented in v7 before v7ve */
2095 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2096 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2097 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2098 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2099 .writefn
= pmovsset_write
,
2100 .raw_writefn
= raw_write
},
2101 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2102 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2103 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2104 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2105 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2106 .writefn
= pmovsset_write
,
2107 .raw_writefn
= raw_write
},
2110 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2117 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2121 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2122 * at all, so we don't need to check whether we're v8A.
2124 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2125 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2126 return CP_ACCESS_TRAP_EL2
;
2128 return CP_ACCESS_OK
;
2131 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2134 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2135 return CP_ACCESS_TRAP
;
2137 return teecr_access(env
, ri
, isread
);
2140 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2141 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2142 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2144 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2145 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2146 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2147 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2150 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2151 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2152 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2154 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2155 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2157 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2158 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2159 .resetfn
= arm_cp_reset_ignore
},
2160 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2161 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2162 .access
= PL0_R
|PL1_W
,
2163 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2165 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2166 .access
= PL0_R
|PL1_W
,
2167 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2168 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2169 .resetfn
= arm_cp_reset_ignore
},
2170 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2171 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2173 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2174 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2176 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2177 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2181 #ifndef CONFIG_USER_ONLY
2183 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2186 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2187 * Writable only at the highest implemented exception level.
2189 int el
= arm_current_el(env
);
2195 hcr
= arm_hcr_el2_eff(env
);
2196 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2197 cntkctl
= env
->cp15
.cnthctl_el2
;
2199 cntkctl
= env
->cp15
.c14_cntkctl
;
2201 if (!extract32(cntkctl
, 0, 2)) {
2202 return CP_ACCESS_TRAP
;
2206 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2207 arm_is_secure_below_el3(env
)) {
2208 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2209 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2217 if (!isread
&& el
< arm_highest_el(env
)) {
2218 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2221 return CP_ACCESS_OK
;
2224 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2227 unsigned int cur_el
= arm_current_el(env
);
2228 bool has_el2
= arm_is_el2_enabled(env
);
2229 uint64_t hcr
= arm_hcr_el2_eff(env
);
2233 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2234 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2235 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2236 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2239 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2240 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2241 return CP_ACCESS_TRAP
;
2244 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2245 if (hcr
& HCR_E2H
) {
2246 if (timeridx
== GTIMER_PHYS
&&
2247 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2248 return CP_ACCESS_TRAP_EL2
;
2251 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2252 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2253 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2254 return CP_ACCESS_TRAP_EL2
;
2260 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2261 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2263 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2264 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2265 return CP_ACCESS_TRAP_EL2
;
2269 return CP_ACCESS_OK
;
2272 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2275 unsigned int cur_el
= arm_current_el(env
);
2276 bool has_el2
= arm_is_el2_enabled(env
);
2277 uint64_t hcr
= arm_hcr_el2_eff(env
);
2281 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2282 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2283 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2284 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2288 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2289 * EL0 if EL0[PV]TEN is zero.
2291 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2292 return CP_ACCESS_TRAP
;
2297 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2298 if (hcr
& HCR_E2H
) {
2299 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2300 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2301 return CP_ACCESS_TRAP_EL2
;
2304 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2305 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2306 return CP_ACCESS_TRAP_EL2
;
2312 return CP_ACCESS_OK
;
2315 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2316 const ARMCPRegInfo
*ri
,
2319 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2322 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2323 const ARMCPRegInfo
*ri
,
2326 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2329 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2332 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2335 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2338 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2341 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2342 const ARMCPRegInfo
*ri
,
2345 /* The AArch64 register view of the secure physical timer is
2346 * always accessible from EL3, and configurably accessible from
2349 switch (arm_current_el(env
)) {
2351 if (!arm_is_secure(env
)) {
2352 return CP_ACCESS_TRAP
;
2354 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2355 return CP_ACCESS_TRAP_EL3
;
2357 return CP_ACCESS_OK
;
2360 return CP_ACCESS_TRAP
;
2362 return CP_ACCESS_OK
;
2364 g_assert_not_reached();
2368 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2370 ARMCPU
*cpu
= env_archcpu(env
);
2372 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2375 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2377 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2380 /* Timer enabled: calculate and set current ISTATUS, irq, and
2381 * reset timer to when ISTATUS next has to change
2383 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2384 cpu
->env
.cp15
.cntvoff_el2
: 0;
2385 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2386 /* Note that this must be unsigned 64 bit arithmetic: */
2387 int istatus
= count
- offset
>= gt
->cval
;
2391 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2393 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2394 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2397 /* Next transition is when count rolls back over to zero */
2398 nexttick
= UINT64_MAX
;
2400 /* Next transition is when we hit cval */
2401 nexttick
= gt
->cval
+ offset
;
2403 /* Note that the desired next expiry time might be beyond the
2404 * signed-64-bit range of a QEMUTimer -- in this case we just
2405 * set the timer for as far in the future as possible. When the
2406 * timer expires we will reset the timer for any remaining period.
2408 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2409 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2411 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2413 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2415 /* Timer disabled: ISTATUS and timer output always clear */
2417 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2418 timer_del(cpu
->gt_timer
[timeridx
]);
2419 trace_arm_gt_recalc_disabled(timeridx
);
2423 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2426 ARMCPU
*cpu
= env_archcpu(env
);
2428 timer_del(cpu
->gt_timer
[timeridx
]);
2431 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2433 return gt_get_countervalue(env
);
2436 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2440 switch (arm_current_el(env
)) {
2442 hcr
= arm_hcr_el2_eff(env
);
2443 if (hcr
& HCR_E2H
) {
2448 hcr
= arm_hcr_el2_eff(env
);
2449 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2455 return env
->cp15
.cntvoff_el2
;
2458 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2460 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2463 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2467 trace_arm_gt_cval_write(timeridx
, value
);
2468 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2469 gt_recalc_timer(env_archcpu(env
), timeridx
);
2472 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2475 uint64_t offset
= 0;
2479 case GTIMER_HYPVIRT
:
2480 offset
= gt_virt_cnt_offset(env
);
2484 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2485 (gt_get_countervalue(env
) - offset
));
2488 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2492 uint64_t offset
= 0;
2496 case GTIMER_HYPVIRT
:
2497 offset
= gt_virt_cnt_offset(env
);
2501 trace_arm_gt_tval_write(timeridx
, value
);
2502 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2503 sextract64(value
, 0, 32);
2504 gt_recalc_timer(env_archcpu(env
), timeridx
);
2507 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2511 ARMCPU
*cpu
= env_archcpu(env
);
2512 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2514 trace_arm_gt_ctl_write(timeridx
, value
);
2515 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2516 if ((oldval
^ value
) & 1) {
2517 /* Enable toggled */
2518 gt_recalc_timer(cpu
, timeridx
);
2519 } else if ((oldval
^ value
) & 2) {
2520 /* IMASK toggled: don't need to recalculate,
2521 * just set the interrupt line based on ISTATUS
2523 int irqstate
= (oldval
& 4) && !(value
& 2);
2525 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2526 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2530 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2532 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2535 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2538 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2541 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2543 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2546 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2549 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2552 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2555 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2558 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2560 switch (arm_mmu_idx(env
)) {
2561 case ARMMMUIdx_E20_0
:
2562 case ARMMMUIdx_E20_2
:
2563 case ARMMMUIdx_E20_2_PAN
:
2564 case ARMMMUIdx_SE20_0
:
2565 case ARMMMUIdx_SE20_2
:
2566 case ARMMMUIdx_SE20_2_PAN
:
2573 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2575 switch (arm_mmu_idx(env
)) {
2576 case ARMMMUIdx_E20_0
:
2577 case ARMMMUIdx_E20_2
:
2578 case ARMMMUIdx_E20_2_PAN
:
2579 case ARMMMUIdx_SE20_0
:
2580 case ARMMMUIdx_SE20_2
:
2581 case ARMMMUIdx_SE20_2_PAN
:
2582 return GTIMER_HYPVIRT
;
2588 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2589 const ARMCPRegInfo
*ri
)
2591 int timeridx
= gt_phys_redir_timeridx(env
);
2592 return env
->cp15
.c14_timer
[timeridx
].cval
;
2595 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2598 int timeridx
= gt_phys_redir_timeridx(env
);
2599 gt_cval_write(env
, ri
, timeridx
, value
);
2602 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2603 const ARMCPRegInfo
*ri
)
2605 int timeridx
= gt_phys_redir_timeridx(env
);
2606 return gt_tval_read(env
, ri
, timeridx
);
2609 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2612 int timeridx
= gt_phys_redir_timeridx(env
);
2613 gt_tval_write(env
, ri
, timeridx
, value
);
2616 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2617 const ARMCPRegInfo
*ri
)
2619 int timeridx
= gt_phys_redir_timeridx(env
);
2620 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2623 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2626 int timeridx
= gt_phys_redir_timeridx(env
);
2627 gt_ctl_write(env
, ri
, timeridx
, value
);
2630 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2632 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2635 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2638 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2641 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2643 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2646 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2649 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2652 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2655 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2658 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2661 ARMCPU
*cpu
= env_archcpu(env
);
2663 trace_arm_gt_cntvoff_write(value
);
2664 raw_write(env
, ri
, value
);
2665 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2668 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2669 const ARMCPRegInfo
*ri
)
2671 int timeridx
= gt_virt_redir_timeridx(env
);
2672 return env
->cp15
.c14_timer
[timeridx
].cval
;
2675 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2678 int timeridx
= gt_virt_redir_timeridx(env
);
2679 gt_cval_write(env
, ri
, timeridx
, value
);
2682 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2683 const ARMCPRegInfo
*ri
)
2685 int timeridx
= gt_virt_redir_timeridx(env
);
2686 return gt_tval_read(env
, ri
, timeridx
);
2689 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2692 int timeridx
= gt_virt_redir_timeridx(env
);
2693 gt_tval_write(env
, ri
, timeridx
, value
);
2696 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2697 const ARMCPRegInfo
*ri
)
2699 int timeridx
= gt_virt_redir_timeridx(env
);
2700 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2703 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2706 int timeridx
= gt_virt_redir_timeridx(env
);
2707 gt_ctl_write(env
, ri
, timeridx
, value
);
2710 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2712 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2715 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2718 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2721 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2723 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2726 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2729 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2732 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2735 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2738 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2740 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2743 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2746 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2749 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2751 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2754 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2757 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2760 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2763 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2766 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2768 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2771 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2774 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2777 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2779 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2782 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2785 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2788 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2791 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2794 void arm_gt_ptimer_cb(void *opaque
)
2796 ARMCPU
*cpu
= opaque
;
2798 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2801 void arm_gt_vtimer_cb(void *opaque
)
2803 ARMCPU
*cpu
= opaque
;
2805 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2808 void arm_gt_htimer_cb(void *opaque
)
2810 ARMCPU
*cpu
= opaque
;
2812 gt_recalc_timer(cpu
, GTIMER_HYP
);
2815 void arm_gt_stimer_cb(void *opaque
)
2817 ARMCPU
*cpu
= opaque
;
2819 gt_recalc_timer(cpu
, GTIMER_SEC
);
2822 void arm_gt_hvtimer_cb(void *opaque
)
2824 ARMCPU
*cpu
= opaque
;
2826 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2829 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2831 ARMCPU
*cpu
= env_archcpu(env
);
2833 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2836 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2837 /* Note that CNTFRQ is purely reads-as-written for the benefit
2838 * of software; writing it doesn't actually change the timer frequency.
2839 * Our reset value matches the fixed frequency we implement the timer at.
2841 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2842 .type
= ARM_CP_ALIAS
,
2843 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2844 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2846 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2847 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2848 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2849 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2850 .resetfn
= arm_gt_cntfrq_reset
,
2852 /* overall control: mostly access permissions */
2853 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2854 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2856 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2859 /* per-timer control */
2860 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2861 .secure
= ARM_CP_SECSTATE_NS
,
2862 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2863 .accessfn
= gt_ptimer_access
,
2864 .fieldoffset
= offsetoflow32(CPUARMState
,
2865 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2866 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2867 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2869 { .name
= "CNTP_CTL_S",
2870 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2871 .secure
= ARM_CP_SECSTATE_S
,
2872 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2873 .accessfn
= gt_ptimer_access
,
2874 .fieldoffset
= offsetoflow32(CPUARMState
,
2875 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2876 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2878 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2879 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2880 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2881 .accessfn
= gt_ptimer_access
,
2882 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2884 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2885 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2887 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2888 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2889 .accessfn
= gt_vtimer_access
,
2890 .fieldoffset
= offsetoflow32(CPUARMState
,
2891 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2892 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2893 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2895 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2896 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2897 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2898 .accessfn
= gt_vtimer_access
,
2899 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2901 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2902 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2904 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2905 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2906 .secure
= ARM_CP_SECSTATE_NS
,
2907 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2908 .accessfn
= gt_ptimer_access
,
2909 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2911 { .name
= "CNTP_TVAL_S",
2912 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2913 .secure
= ARM_CP_SECSTATE_S
,
2914 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2915 .accessfn
= gt_ptimer_access
,
2916 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2918 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2919 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2920 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2921 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2922 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2924 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2925 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2926 .accessfn
= gt_vtimer_access
,
2927 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2929 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2930 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2931 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2932 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2933 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2935 /* The counter itself */
2936 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2937 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2938 .accessfn
= gt_pct_access
,
2939 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2941 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2942 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2943 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2944 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2946 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2947 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2948 .accessfn
= gt_vct_access
,
2949 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2951 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2952 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2953 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2954 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2956 /* Comparison value, indicating when the timer goes off */
2957 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2958 .secure
= ARM_CP_SECSTATE_NS
,
2960 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2961 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2962 .accessfn
= gt_ptimer_access
,
2963 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
2964 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
2966 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2967 .secure
= ARM_CP_SECSTATE_S
,
2969 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2970 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2971 .accessfn
= gt_ptimer_access
,
2972 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2974 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2975 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2978 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2979 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2980 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
2981 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
2983 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2985 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2987 .accessfn
= gt_vtimer_access
,
2988 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
2989 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
2991 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2992 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2995 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2996 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2997 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
2998 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3000 /* Secure timer -- this is actually restricted to only EL3
3001 * and configurably Secure-EL1 via the accessfn.
3003 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3004 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3005 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3006 .accessfn
= gt_stimer_access
,
3007 .readfn
= gt_sec_tval_read
,
3008 .writefn
= gt_sec_tval_write
,
3009 .resetfn
= gt_sec_timer_reset
,
3011 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3012 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3013 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3014 .accessfn
= gt_stimer_access
,
3015 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3017 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3019 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3020 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3021 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3022 .accessfn
= gt_stimer_access
,
3023 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3024 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3028 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3031 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3032 return CP_ACCESS_TRAP
;
3034 return CP_ACCESS_OK
;
3039 /* In user-mode most of the generic timer registers are inaccessible
3040 * however modern kernels (4.12+) allow access to cntvct_el0
3043 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3045 ARMCPU
*cpu
= env_archcpu(env
);
3047 /* Currently we have no support for QEMUTimer in linux-user so we
3048 * can't call gt_get_countervalue(env), instead we directly
3049 * call the lower level functions.
3051 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3054 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3055 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3056 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3057 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3059 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3061 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3062 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3063 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3064 .readfn
= gt_virt_cnt_read
,
3070 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3072 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3073 raw_write(env
, ri
, value
);
3074 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3075 raw_write(env
, ri
, value
& 0xfffff6ff);
3077 raw_write(env
, ri
, value
& 0xfffff1ff);
3081 #ifndef CONFIG_USER_ONLY
3082 /* get_phys_addr() isn't present for user-mode-only targets */
3084 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3088 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3089 * Secure EL1 (which can only happen if EL3 is AArch64).
3090 * They are simply UNDEF if executed from NS EL1.
3091 * They function normally from EL2 or EL3.
3093 if (arm_current_el(env
) == 1) {
3094 if (arm_is_secure_below_el3(env
)) {
3095 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3096 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3098 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3100 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3103 return CP_ACCESS_OK
;
3107 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3108 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3111 target_ulong page_size
;
3115 bool format64
= false;
3116 MemTxAttrs attrs
= {};
3117 ARMMMUFaultInfo fi
= {};
3118 ARMCacheAttrs cacheattrs
= {};
3120 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3121 &prot
, &page_size
, &fi
, &cacheattrs
);
3124 * ATS operations only do S1 or S1+S2 translations, so we never
3125 * have to deal with the ARMCacheAttrs format for S2 only.
3127 assert(!cacheattrs
.is_s2_format
);
3131 * Some kinds of translation fault must cause exceptions rather
3132 * than being reported in the PAR.
3134 int current_el
= arm_current_el(env
);
3136 uint32_t syn
, fsr
, fsc
;
3137 bool take_exc
= false;
3139 if (fi
.s1ptw
&& current_el
== 1
3140 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3142 * Synchronous stage 2 fault on an access made as part of the
3143 * translation table walk for AT S1E0* or AT S1E1* insn
3144 * executed from NS EL1. If this is a synchronous external abort
3145 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3146 * to EL3. Otherwise the fault is taken as an exception to EL2,
3147 * and HPFAR_EL2 holds the faulting IPA.
3149 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3150 (env
->cp15
.scr_el3
& SCR_EA
)) {
3153 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3154 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3155 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3160 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3162 * Synchronous external aborts during a translation table walk
3163 * are taken as Data Abort exceptions.
3166 if (current_el
== 3) {
3172 target_el
= exception_target_el(env
);
3178 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3179 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3180 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3181 fsr
= arm_fi_to_lfsc(&fi
);
3182 fsc
= extract32(fsr
, 0, 6);
3184 fsr
= arm_fi_to_sfsc(&fi
);
3188 * Report exception with ESR indicating a fault due to a
3189 * translation table walk for a cache maintenance instruction.
3191 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3192 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3193 env
->exception
.vaddress
= value
;
3194 env
->exception
.fsr
= fsr
;
3195 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3201 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3204 * * TTBCR.EAE determines whether the result is returned using the
3205 * 32-bit or the 64-bit PAR format
3206 * * Instructions executed in Hyp mode always use the 64bit format
3208 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3209 * * The Non-secure TTBCR.EAE bit is set to 1
3210 * * The implementation includes EL2, and the value of HCR.VM is 1
3212 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3214 * ATS1Hx always uses the 64bit format.
3216 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3218 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3219 if (mmu_idx
== ARMMMUIdx_E10_0
||
3220 mmu_idx
== ARMMMUIdx_E10_1
||
3221 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3222 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3224 format64
|= arm_current_el(env
) == 2;
3230 /* Create a 64-bit PAR */
3231 par64
= (1 << 11); /* LPAE bit always set */
3233 par64
|= phys_addr
& ~0xfffULL
;
3234 if (!attrs
.secure
) {
3235 par64
|= (1 << 9); /* NS */
3237 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3238 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3240 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3243 par64
|= (fsr
& 0x3f) << 1; /* FS */
3245 par64
|= (1 << 9); /* S */
3248 par64
|= (1 << 8); /* PTW */
3252 /* fsr is a DFSR/IFSR value for the short descriptor
3253 * translation table format (with WnR always clear).
3254 * Convert it to a 32-bit PAR.
3257 /* We do not set any attribute bits in the PAR */
3258 if (page_size
== (1 << 24)
3259 && arm_feature(env
, ARM_FEATURE_V7
)) {
3260 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3262 par64
= phys_addr
& 0xfffff000;
3264 if (!attrs
.secure
) {
3265 par64
|= (1 << 9); /* NS */
3268 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3270 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3271 ((fsr
& 0xf) << 1) | 1;
3276 #endif /* CONFIG_TCG */
3278 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3281 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3284 int el
= arm_current_el(env
);
3285 bool secure
= arm_is_secure_below_el3(env
);
3287 switch (ri
->opc2
& 6) {
3289 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3292 mmu_idx
= ARMMMUIdx_SE3
;
3295 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3298 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3299 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3300 : ARMMMUIdx_Stage1_E1_PAN
);
3302 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3306 g_assert_not_reached();
3310 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3313 mmu_idx
= ARMMMUIdx_SE10_0
;
3316 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3317 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3320 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3323 g_assert_not_reached();
3327 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3328 mmu_idx
= ARMMMUIdx_E10_1
;
3331 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3332 mmu_idx
= ARMMMUIdx_E10_0
;
3335 g_assert_not_reached();
3338 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3340 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3342 /* Handled by hardware accelerator. */
3343 g_assert_not_reached();
3344 #endif /* CONFIG_TCG */
3347 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3351 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3354 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3356 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3358 /* Handled by hardware accelerator. */
3359 g_assert_not_reached();
3360 #endif /* CONFIG_TCG */
3363 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3366 if (arm_current_el(env
) == 3 &&
3367 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3368 return CP_ACCESS_TRAP
;
3370 return CP_ACCESS_OK
;
3373 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3377 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3379 int secure
= arm_is_secure_below_el3(env
);
3381 switch (ri
->opc2
& 6) {
3384 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3385 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3386 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3387 : ARMMMUIdx_Stage1_E1_PAN
);
3389 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3392 case 4: /* AT S1E2R, AT S1E2W */
3393 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3395 case 6: /* AT S1E3R, AT S1E3W */
3396 mmu_idx
= ARMMMUIdx_SE3
;
3399 g_assert_not_reached();
3402 case 2: /* AT S1E0R, AT S1E0W */
3403 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3405 case 4: /* AT S12E1R, AT S12E1W */
3406 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3408 case 6: /* AT S12E0R, AT S12E0W */
3409 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3412 g_assert_not_reached();
3415 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3417 /* Handled by hardware accelerator. */
3418 g_assert_not_reached();
3419 #endif /* CONFIG_TCG */
3423 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3424 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3425 .access
= PL1_RW
, .resetvalue
= 0,
3426 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3427 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3428 .writefn
= par_write
},
3429 #ifndef CONFIG_USER_ONLY
3430 /* This underdecoding is safe because the reginfo is NO_RAW. */
3431 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3432 .access
= PL1_W
, .accessfn
= ats_access
,
3433 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3437 /* Return basic MPU access permission bits. */
3438 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3445 for (i
= 0; i
< 16; i
+= 2) {
3446 ret
|= (val
>> i
) & mask
;
3452 /* Pad basic MPU access permission bits to extended format. */
3453 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3460 for (i
= 0; i
< 16; i
+= 2) {
3461 ret
|= (val
& mask
) << i
;
3467 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3470 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3473 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3475 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3478 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3481 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3484 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3486 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3489 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3491 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3497 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3501 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3504 ARMCPU
*cpu
= env_archcpu(env
);
3505 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3511 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3512 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3516 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3519 ARMCPU
*cpu
= env_archcpu(env
);
3520 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3522 if (value
>= nrgs
) {
3523 qemu_log_mask(LOG_GUEST_ERROR
,
3524 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3525 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3529 raw_write(env
, ri
, value
);
3532 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3533 /* Reset for all these registers is handled in arm_cpu_reset(),
3534 * because the PMSAv7 is also used by M-profile CPUs, which do
3535 * not register cpregs but still need the state to be reset.
3537 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3538 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3539 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3540 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3541 .resetfn
= arm_cp_reset_ignore
},
3542 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3543 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3544 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3545 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3546 .resetfn
= arm_cp_reset_ignore
},
3547 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3548 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3549 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3550 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3551 .resetfn
= arm_cp_reset_ignore
},
3552 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3554 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3555 .writefn
= pmsav7_rgnr_write
,
3556 .resetfn
= arm_cp_reset_ignore
},
3559 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3560 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3561 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3562 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3563 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3564 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3565 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3566 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3567 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3568 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3570 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3572 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3574 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3576 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3578 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3579 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3581 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3582 /* Protection region base and size registers */
3583 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3584 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3585 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3586 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3587 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3588 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3589 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3590 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3591 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3592 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3593 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3594 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3595 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3596 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3597 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3598 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3599 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3600 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3601 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3602 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3603 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3604 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3605 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3606 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3609 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3612 TCR
*tcr
= raw_ptr(env
, ri
);
3613 int maskshift
= extract32(value
, 0, 3);
3615 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3616 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3617 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3618 * using Long-desciptor translation table format */
3619 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3620 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3621 /* In an implementation that includes the Security Extensions
3622 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3623 * Short-descriptor translation table format.
3625 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3631 /* Update the masks corresponding to the TCR bank being written
3632 * Note that we always calculate mask and base_mask, but
3633 * they are only used for short-descriptor tables (ie if EAE is 0);
3634 * for long-descriptor tables the TCR fields are used differently
3635 * and the mask and base_mask values are meaningless.
3637 tcr
->raw_tcr
= value
;
3638 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3639 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3642 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3645 ARMCPU
*cpu
= env_archcpu(env
);
3646 TCR
*tcr
= raw_ptr(env
, ri
);
3648 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3649 /* With LPAE the TTBCR could result in a change of ASID
3650 * via the TTBCR.A1 bit, so do a TLB flush.
3652 tlb_flush(CPU(cpu
));
3654 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3655 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3656 vmsa_ttbcr_raw_write(env
, ri
, value
);
3659 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3661 TCR
*tcr
= raw_ptr(env
, ri
);
3663 /* Reset both the TCR as well as the masks corresponding to the bank of
3664 * the TCR being reset.
3668 tcr
->base_mask
= 0xffffc000u
;
3671 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3674 ARMCPU
*cpu
= env_archcpu(env
);
3675 TCR
*tcr
= raw_ptr(env
, ri
);
3677 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3678 tlb_flush(CPU(cpu
));
3679 tcr
->raw_tcr
= value
;
3682 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3685 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3686 if (cpreg_field_is_64bit(ri
) &&
3687 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3688 ARMCPU
*cpu
= env_archcpu(env
);
3689 tlb_flush(CPU(cpu
));
3691 raw_write(env
, ri
, value
);
3694 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3698 * If we are running with E2&0 regime, then an ASID is active.
3699 * Flush if that might be changing. Note we're not checking
3700 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3701 * holds the active ASID, only checking the field that might.
3703 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3704 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3705 uint16_t mask
= ARMMMUIdxBit_E20_2
|
3706 ARMMMUIdxBit_E20_2_PAN
|
3709 if (arm_is_secure_below_el3(env
)) {
3710 mask
>>= ARM_MMU_IDX_A_NS
;
3713 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
3715 raw_write(env
, ri
, value
);
3718 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3721 ARMCPU
*cpu
= env_archcpu(env
);
3722 CPUState
*cs
= CPU(cpu
);
3725 * A change in VMID to the stage2 page table (Stage2) invalidates
3726 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3728 if (raw_read(env
, ri
) != value
) {
3729 uint16_t mask
= ARMMMUIdxBit_E10_1
|
3730 ARMMMUIdxBit_E10_1_PAN
|
3733 if (arm_is_secure_below_el3(env
)) {
3734 mask
>>= ARM_MMU_IDX_A_NS
;
3737 tlb_flush_by_mmuidx(cs
, mask
);
3738 raw_write(env
, ri
, value
);
3742 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3743 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3744 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
3745 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3746 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3747 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3748 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3749 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3750 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3751 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3752 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3753 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3754 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3755 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3756 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3757 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3758 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3762 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3763 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3764 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3765 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3766 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3767 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3768 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3769 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3770 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3771 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3772 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3773 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3774 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3775 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3776 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3777 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3778 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3779 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3780 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3781 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3782 .writefn
= vmsa_tcr_el12_write
,
3783 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3784 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3785 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3786 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3787 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3788 .raw_writefn
= vmsa_ttbcr_raw_write
,
3789 /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
3790 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.tcr_el
[3]),
3791 offsetof(CPUARMState
, cp15
.tcr_el
[1])} },
3794 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3795 * qemu tlbs nor adjusting cached masks.
3797 static const ARMCPRegInfo ttbcr2_reginfo
= {
3798 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3799 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3800 .type
= ARM_CP_ALIAS
,
3801 .bank_fieldoffsets
= {
3802 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3].raw_tcr
),
3803 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1].raw_tcr
),
3807 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3810 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3811 /* The OS_TYPE bit in this register changes the reported CPUID! */
3812 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3813 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3816 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3819 env
->cp15
.c15_threadid
= value
& 0xffff;
3822 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3825 /* Wait-for-interrupt (deprecated) */
3826 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3829 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3832 /* On OMAP there are registers indicating the max/min index of dcache lines
3833 * containing a dirty line; cache flush operations have to reset these.
3835 env
->cp15
.c15_i_max
= 0x000;
3836 env
->cp15
.c15_i_min
= 0xff0;
3839 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3840 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3841 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3842 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3844 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3845 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3846 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3848 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3849 .writefn
= omap_ticonfig_write
},
3850 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3852 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3853 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3854 .access
= PL1_RW
, .resetvalue
= 0xff0,
3855 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3856 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3858 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3859 .writefn
= omap_threadid_write
},
3860 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3861 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3862 .type
= ARM_CP_NO_RAW
,
3863 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3864 /* TODO: Peripheral port remap register:
3865 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3866 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3869 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3870 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3871 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3872 .writefn
= omap_cachemaint_write
},
3873 { .name
= "C9", .cp
= 15, .crn
= 9,
3874 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3875 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3878 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3881 env
->cp15
.c15_cpar
= value
& 0x3fff;
3884 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3885 { .name
= "XSCALE_CPAR",
3886 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3887 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3888 .writefn
= xscale_cpar_write
, },
3889 { .name
= "XSCALE_AUXCR",
3890 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3891 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3893 /* XScale specific cache-lockdown: since we have no cache we NOP these
3894 * and hope the guest does not really rely on cache behaviour.
3896 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3897 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3898 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3899 { .name
= "XSCALE_UNLOCK_ICACHE",
3900 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3901 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3902 { .name
= "XSCALE_DCACHE_LOCK",
3903 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3904 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3905 { .name
= "XSCALE_UNLOCK_DCACHE",
3906 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3907 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3910 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3911 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3912 * implementation of this implementation-defined space.
3913 * Ideally this should eventually disappear in favour of actually
3914 * implementing the correct behaviour for all cores.
3916 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3917 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3919 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3923 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3924 /* Cache status: RAZ because we have no cache so it's always clean */
3925 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3926 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3930 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3931 /* We never have a a block transfer operation in progress */
3932 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3933 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3935 /* The cache ops themselves: these all NOP for QEMU */
3936 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3937 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3938 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3939 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3940 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3941 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3942 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3943 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3944 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3945 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3946 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3947 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3950 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3951 /* The cache test-and-clean instructions always return (1 << 30)
3952 * to indicate that there are no dirty cache lines.
3954 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
3955 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3956 .resetvalue
= (1 << 30) },
3957 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
3958 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3959 .resetvalue
= (1 << 30) },
3962 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
3963 /* Ignore ReadBuffer accesses */
3964 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
3965 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3966 .access
= PL1_RW
, .resetvalue
= 0,
3967 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
3970 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3972 unsigned int cur_el
= arm_current_el(env
);
3974 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
3975 return env
->cp15
.vpidr_el2
;
3977 return raw_read(env
, ri
);
3980 static uint64_t mpidr_read_val(CPUARMState
*env
)
3982 ARMCPU
*cpu
= env_archcpu(env
);
3983 uint64_t mpidr
= cpu
->mp_affinity
;
3985 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3986 mpidr
|= (1U << 31);
3987 /* Cores which are uniprocessor (non-coherent)
3988 * but still implement the MP extensions set
3989 * bit 30. (For instance, Cortex-R5).
3991 if (cpu
->mp_is_up
) {
3992 mpidr
|= (1u << 30);
3998 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4000 unsigned int cur_el
= arm_current_el(env
);
4002 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4003 return env
->cp15
.vmpidr_el2
;
4005 return mpidr_read_val(env
);
4008 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4010 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4011 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4012 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4013 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4014 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4015 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4016 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4017 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4018 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4019 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4020 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4021 offsetof(CPUARMState
, cp15
.par_ns
)} },
4022 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4023 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4024 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4025 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4026 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4027 .writefn
= vmsa_ttbr_write
, },
4028 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4029 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4030 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4031 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4032 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4033 .writefn
= vmsa_ttbr_write
, },
4036 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4038 return vfp_get_fpcr(env
);
4041 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4044 vfp_set_fpcr(env
, value
);
4047 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4049 return vfp_get_fpsr(env
);
4052 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4055 vfp_set_fpsr(env
, value
);
4058 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4061 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4062 return CP_ACCESS_TRAP
;
4064 return CP_ACCESS_OK
;
4067 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4070 env
->daif
= value
& PSTATE_DAIF
;
4073 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4075 return env
->pstate
& PSTATE_PAN
;
4078 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4081 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4084 static const ARMCPRegInfo pan_reginfo
= {
4085 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4086 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4087 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4088 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4091 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4093 return env
->pstate
& PSTATE_UAO
;
4096 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4099 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4102 static const ARMCPRegInfo uao_reginfo
= {
4103 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4104 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4105 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4106 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4109 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4111 return env
->pstate
& PSTATE_DIT
;
4114 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4117 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4120 static const ARMCPRegInfo dit_reginfo
= {
4121 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4122 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4123 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4124 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4127 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4129 return env
->pstate
& PSTATE_SSBS
;
4132 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4135 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4138 static const ARMCPRegInfo ssbs_reginfo
= {
4139 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4140 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4141 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4142 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4145 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4146 const ARMCPRegInfo
*ri
,
4149 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4150 switch (arm_current_el(env
)) {
4152 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4153 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4154 return CP_ACCESS_TRAP
;
4158 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4159 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4160 return CP_ACCESS_TRAP_EL2
;
4164 return CP_ACCESS_OK
;
4167 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4168 const ARMCPRegInfo
*ri
,
4171 /* Cache invalidate/clean to Point of Unification... */
4172 switch (arm_current_el(env
)) {
4174 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4175 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4176 return CP_ACCESS_TRAP
;
4180 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4181 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4182 return CP_ACCESS_TRAP_EL2
;
4186 return CP_ACCESS_OK
;
4189 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4190 * Page D4-1736 (DDI0487A.b)
4193 static int vae1_tlbmask(CPUARMState
*env
)
4195 uint64_t hcr
= arm_hcr_el2_eff(env
);
4198 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4199 mask
= ARMMMUIdxBit_E20_2
|
4200 ARMMMUIdxBit_E20_2_PAN
|
4203 mask
= ARMMMUIdxBit_E10_1
|
4204 ARMMMUIdxBit_E10_1_PAN
|
4208 if (arm_is_secure_below_el3(env
)) {
4209 mask
>>= ARM_MMU_IDX_A_NS
;
4215 /* Return 56 if TBI is enabled, 64 otherwise. */
4216 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4219 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4220 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4221 int select
= extract64(addr
, 55, 1);
4223 return (tbi
>> select
) & 1 ? 56 : 64;
4226 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4228 uint64_t hcr
= arm_hcr_el2_eff(env
);
4231 /* Only the regime of the mmu_idx below is significant. */
4232 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4233 mmu_idx
= ARMMMUIdx_E20_0
;
4235 mmu_idx
= ARMMMUIdx_E10_0
;
4238 if (arm_is_secure_below_el3(env
)) {
4239 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4242 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4245 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4248 CPUState
*cs
= env_cpu(env
);
4249 int mask
= vae1_tlbmask(env
);
4251 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4254 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4257 CPUState
*cs
= env_cpu(env
);
4258 int mask
= vae1_tlbmask(env
);
4260 if (tlb_force_broadcast(env
)) {
4261 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4263 tlb_flush_by_mmuidx(cs
, mask
);
4267 static int alle1_tlbmask(CPUARMState
*env
)
4270 * Note that the 'ALL' scope must invalidate both stage 1 and
4271 * stage 2 translations, whereas most other scopes only invalidate
4272 * stage 1 translations.
4274 if (arm_is_secure_below_el3(env
)) {
4275 return ARMMMUIdxBit_SE10_1
|
4276 ARMMMUIdxBit_SE10_1_PAN
|
4277 ARMMMUIdxBit_SE10_0
;
4279 return ARMMMUIdxBit_E10_1
|
4280 ARMMMUIdxBit_E10_1_PAN
|
4285 static int e2_tlbmask(CPUARMState
*env
)
4287 if (arm_is_secure_below_el3(env
)) {
4288 return ARMMMUIdxBit_SE20_0
|
4289 ARMMMUIdxBit_SE20_2
|
4290 ARMMMUIdxBit_SE20_2_PAN
|
4293 return ARMMMUIdxBit_E20_0
|
4294 ARMMMUIdxBit_E20_2
|
4295 ARMMMUIdxBit_E20_2_PAN
|
4300 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4303 CPUState
*cs
= env_cpu(env
);
4304 int mask
= alle1_tlbmask(env
);
4306 tlb_flush_by_mmuidx(cs
, mask
);
4309 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4312 CPUState
*cs
= env_cpu(env
);
4313 int mask
= e2_tlbmask(env
);
4315 tlb_flush_by_mmuidx(cs
, mask
);
4318 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4321 ARMCPU
*cpu
= env_archcpu(env
);
4322 CPUState
*cs
= CPU(cpu
);
4324 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4327 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4330 CPUState
*cs
= env_cpu(env
);
4331 int mask
= alle1_tlbmask(env
);
4333 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4336 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4339 CPUState
*cs
= env_cpu(env
);
4340 int mask
= e2_tlbmask(env
);
4342 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4345 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4348 CPUState
*cs
= env_cpu(env
);
4350 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4353 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4356 /* Invalidate by VA, EL2
4357 * Currently handles both VAE2 and VALE2, since we don't support
4358 * flush-last-level-only.
4360 CPUState
*cs
= env_cpu(env
);
4361 int mask
= e2_tlbmask(env
);
4362 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4364 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4367 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4370 /* Invalidate by VA, EL3
4371 * Currently handles both VAE3 and VALE3, since we don't support
4372 * flush-last-level-only.
4374 ARMCPU
*cpu
= env_archcpu(env
);
4375 CPUState
*cs
= CPU(cpu
);
4376 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4378 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4381 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4384 CPUState
*cs
= env_cpu(env
);
4385 int mask
= vae1_tlbmask(env
);
4386 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4387 int bits
= vae1_tlbbits(env
, pageaddr
);
4389 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4392 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4395 /* Invalidate by VA, EL1&0 (AArch64 version).
4396 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4397 * since we don't support flush-for-specific-ASID-only or
4398 * flush-last-level-only.
4400 CPUState
*cs
= env_cpu(env
);
4401 int mask
= vae1_tlbmask(env
);
4402 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4403 int bits
= vae1_tlbbits(env
, pageaddr
);
4405 if (tlb_force_broadcast(env
)) {
4406 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4408 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4412 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4415 CPUState
*cs
= env_cpu(env
);
4416 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4417 bool secure
= arm_is_secure_below_el3(env
);
4418 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4419 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4422 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4425 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4428 CPUState
*cs
= env_cpu(env
);
4429 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4430 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4432 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4433 ARMMMUIdxBit_SE3
, bits
);
4436 #ifdef TARGET_AARCH64
4442 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4445 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4446 /* Extract one bit to represent the va selector in use. */
4447 uint64_t select
= sextract64(value
, 36, 1);
4448 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4449 TLBIRange ret
= { };
4451 page_size_granule
= extract64(value
, 46, 2);
4453 /* The granule encoded in value must match the granule in use. */
4454 if (page_size_granule
!= (param
.using64k
? 3 : param
.using16k
? 2 : 1)) {
4455 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4460 page_shift
= (page_size_granule
- 1) * 2 + 12;
4461 num
= extract64(value
, 39, 5);
4462 scale
= extract64(value
, 44, 2);
4463 exponent
= (5 * scale
) + 1;
4465 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4468 ret
.base
= sextract64(value
, 0, 37);
4470 ret
.base
= extract64(value
, 0, 37);
4474 * With DS=1, BaseADDR is always shifted 16 so that it is able
4475 * to address all 52 va bits. The input address is perforce
4476 * aligned on a 64k boundary regardless of translation granule.
4480 ret
.base
<<= page_shift
;
4485 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4486 int idxmap
, bool synced
)
4488 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4492 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4493 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4496 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4502 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4503 range
.length
, idxmap
, bits
);
4507 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4508 const ARMCPRegInfo
*ri
,
4512 * Invalidate by VA range, EL1&0.
4513 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4514 * since we don't support flush-for-specific-ASID-only or
4515 * flush-last-level-only.
4518 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4519 tlb_force_broadcast(env
));
4522 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4523 const ARMCPRegInfo
*ri
,
4527 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4528 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4529 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4530 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4531 * shareable specific flushes.
4534 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4537 static int vae2_tlbmask(CPUARMState
*env
)
4539 return (arm_is_secure_below_el3(env
)
4540 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4543 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4544 const ARMCPRegInfo
*ri
,
4548 * Invalidate by VA range, EL2.
4549 * Currently handles all of RVAE2 and RVALE2,
4550 * since we don't support flush-for-specific-ASID-only or
4551 * flush-last-level-only.
4554 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4555 tlb_force_broadcast(env
));
4560 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4561 const ARMCPRegInfo
*ri
,
4565 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4566 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4567 * since we don't support flush-for-specific-ASID-only,
4568 * flush-last-level-only or inner/outer shareable specific flushes.
4571 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4575 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4576 const ARMCPRegInfo
*ri
,
4580 * Invalidate by VA range, EL3.
4581 * Currently handles all of RVAE3 and RVALE3,
4582 * since we don't support flush-for-specific-ASID-only or
4583 * flush-last-level-only.
4586 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4587 tlb_force_broadcast(env
));
4590 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4591 const ARMCPRegInfo
*ri
,
4595 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4596 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4597 * since we don't support flush-for-specific-ASID-only,
4598 * flush-last-level-only or inner/outer specific flushes.
4601 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4605 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4608 int cur_el
= arm_current_el(env
);
4611 uint64_t hcr
= arm_hcr_el2_eff(env
);
4614 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4615 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4616 return CP_ACCESS_TRAP_EL2
;
4619 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4620 return CP_ACCESS_TRAP
;
4622 if (hcr
& HCR_TDZ
) {
4623 return CP_ACCESS_TRAP_EL2
;
4626 } else if (hcr
& HCR_TDZ
) {
4627 return CP_ACCESS_TRAP_EL2
;
4630 return CP_ACCESS_OK
;
4633 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4635 ARMCPU
*cpu
= env_archcpu(env
);
4636 int dzp_bit
= 1 << 4;
4638 /* DZP indicates whether DC ZVA access is allowed */
4639 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4642 return cpu
->dcz_blocksize
| dzp_bit
;
4645 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4648 if (!(env
->pstate
& PSTATE_SP
)) {
4649 /* Access to SP_EL0 is undefined if it's being used as
4650 * the stack pointer.
4652 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4654 return CP_ACCESS_OK
;
4657 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4659 return env
->pstate
& PSTATE_SP
;
4662 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4664 update_spsel(env
, val
);
4667 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4670 ARMCPU
*cpu
= env_archcpu(env
);
4672 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4673 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4677 /* ??? Lots of these bits are not implemented. */
4679 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4680 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4681 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4683 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4684 SCTLR_ATA0
| SCTLR_ATA
);
4688 if (raw_read(env
, ri
) == value
) {
4689 /* Skip the TLB flush if nothing actually changed; Linux likes
4690 * to do a lot of pointless SCTLR writes.
4695 raw_write(env
, ri
, value
);
4697 /* This may enable/disable the MMU, so do a TLB flush. */
4698 tlb_flush(CPU(cpu
));
4700 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4702 * Normally we would always end the TB on an SCTLR write; see the
4703 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4704 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4705 * of hflags from the translator, so do it here.
4707 arm_rebuild_hflags(env
);
4711 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4714 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4717 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4718 /* Minimal set of EL0-visible registers. This will need to be expanded
4719 * significantly for system emulation of AArch64 CPUs.
4721 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4722 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4723 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4724 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4725 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4726 .type
= ARM_CP_NO_RAW
,
4727 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4728 .fieldoffset
= offsetof(CPUARMState
, daif
),
4729 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4730 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4731 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4732 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4733 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4734 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4735 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4736 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4737 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4738 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4739 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4740 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4741 .readfn
= aa64_dczid_read
},
4742 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4743 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4744 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4745 #ifndef CONFIG_USER_ONLY
4746 /* Avoid overhead of an access check that always passes in user-mode */
4747 .accessfn
= aa64_zva_access
,
4750 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4751 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4752 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4753 /* Cache ops: all NOPs since we don't emulate caches */
4754 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4755 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4756 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4757 .accessfn
= aa64_cacheop_pou_access
},
4758 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4759 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4760 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4761 .accessfn
= aa64_cacheop_pou_access
},
4762 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4763 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4764 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4765 .accessfn
= aa64_cacheop_pou_access
},
4766 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4767 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4768 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4769 .type
= ARM_CP_NOP
},
4770 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4771 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4772 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4773 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4774 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4775 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4776 .accessfn
= aa64_cacheop_poc_access
},
4777 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4778 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4779 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4780 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4781 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4782 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4783 .accessfn
= aa64_cacheop_pou_access
},
4784 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4785 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4786 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4787 .accessfn
= aa64_cacheop_poc_access
},
4788 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4789 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4790 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4791 /* TLBI operations */
4792 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4793 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4794 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4795 .writefn
= tlbi_aa64_vmalle1is_write
},
4796 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4797 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4798 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4799 .writefn
= tlbi_aa64_vae1is_write
},
4800 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4801 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4802 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4803 .writefn
= tlbi_aa64_vmalle1is_write
},
4804 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4805 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4806 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4807 .writefn
= tlbi_aa64_vae1is_write
},
4808 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4809 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4810 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4811 .writefn
= tlbi_aa64_vae1is_write
},
4812 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4813 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4814 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4815 .writefn
= tlbi_aa64_vae1is_write
},
4816 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4817 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4818 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4819 .writefn
= tlbi_aa64_vmalle1_write
},
4820 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4821 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4822 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4823 .writefn
= tlbi_aa64_vae1_write
},
4824 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4825 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4826 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4827 .writefn
= tlbi_aa64_vmalle1_write
},
4828 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4829 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4830 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4831 .writefn
= tlbi_aa64_vae1_write
},
4832 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4833 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4834 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4835 .writefn
= tlbi_aa64_vae1_write
},
4836 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4837 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4838 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4839 .writefn
= tlbi_aa64_vae1_write
},
4840 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4841 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4842 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4843 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4844 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4845 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4846 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4847 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4848 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4849 .writefn
= tlbi_aa64_alle1is_write
},
4850 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4852 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4853 .writefn
= tlbi_aa64_alle1is_write
},
4854 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4855 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4856 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4857 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4858 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4859 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4860 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4861 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4862 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4863 .writefn
= tlbi_aa64_alle1_write
},
4864 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4865 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4866 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4867 .writefn
= tlbi_aa64_alle1is_write
},
4868 #ifndef CONFIG_USER_ONLY
4869 /* 64 bit address translation operations */
4870 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4871 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4872 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4873 .writefn
= ats_write64
},
4874 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4875 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4876 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4877 .writefn
= ats_write64
},
4878 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4879 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4880 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4881 .writefn
= ats_write64
},
4882 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4883 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4884 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4885 .writefn
= ats_write64
},
4886 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4888 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4889 .writefn
= ats_write64
},
4890 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4891 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4892 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4893 .writefn
= ats_write64
},
4894 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4895 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4896 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4897 .writefn
= ats_write64
},
4898 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4899 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4900 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4901 .writefn
= ats_write64
},
4902 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4903 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4904 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4905 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4906 .writefn
= ats_write64
},
4907 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4908 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4909 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4910 .writefn
= ats_write64
},
4911 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4912 .type
= ARM_CP_ALIAS
,
4913 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4914 .access
= PL1_RW
, .resetvalue
= 0,
4915 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4916 .writefn
= par_write
},
4918 /* TLB invalidate last level of translation table walk */
4919 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4920 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4921 .writefn
= tlbimva_is_write
},
4922 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4923 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4924 .writefn
= tlbimvaa_is_write
},
4925 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4926 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4927 .writefn
= tlbimva_write
},
4928 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4929 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4930 .writefn
= tlbimvaa_write
},
4931 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4932 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4933 .writefn
= tlbimva_hyp_write
},
4934 { .name
= "TLBIMVALHIS",
4935 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4936 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4937 .writefn
= tlbimva_hyp_is_write
},
4938 { .name
= "TLBIIPAS2",
4939 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4940 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4941 { .name
= "TLBIIPAS2IS",
4942 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4943 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4944 { .name
= "TLBIIPAS2L",
4945 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4946 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4947 { .name
= "TLBIIPAS2LIS",
4948 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4949 .type
= ARM_CP_NOP
, .access
= PL2_W
},
4950 /* 32 bit cache operations */
4951 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4952 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
4953 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4954 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4955 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4956 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
4957 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4958 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
4959 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4960 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4961 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4962 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4963 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4964 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
4965 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4966 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
4967 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4968 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
4969 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4970 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
4971 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4972 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
4973 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4974 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
4975 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4976 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
4977 /* MMU Domain access control / MPU write buffer control */
4978 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4979 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4980 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4981 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4982 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4983 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4984 .type
= ARM_CP_ALIAS
,
4985 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4987 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4988 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4989 .type
= ARM_CP_ALIAS
,
4990 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4992 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4993 /* We rely on the access checks not allowing the guest to write to the
4994 * state field when SPSel indicates that it's being used as the stack
4997 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4998 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4999 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5000 .type
= ARM_CP_ALIAS
,
5001 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5002 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5003 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5004 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5005 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5006 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5007 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5008 .type
= ARM_CP_NO_RAW
,
5009 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5010 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5011 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5013 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5014 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5015 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5016 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5017 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5018 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5019 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5020 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5021 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5022 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5023 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5024 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5025 .type
= ARM_CP_ALIAS
,
5026 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5028 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5029 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5030 .type
= ARM_CP_ALIAS
,
5031 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5033 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5034 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5035 .type
= ARM_CP_ALIAS
,
5036 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5038 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5039 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5040 .type
= ARM_CP_ALIAS
,
5041 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5043 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5044 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5045 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5047 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5048 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5049 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5050 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5051 .writefn
= sdcr_write
,
5052 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5055 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5057 ARMCPU
*cpu
= env_archcpu(env
);
5059 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5060 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5062 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5065 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5066 valid_mask
&= ~HCR_HCD
;
5067 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5068 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5069 * However, if we're using the SMC PSCI conduit then QEMU is
5070 * effectively acting like EL3 firmware and so the guest at
5071 * EL2 should retain the ability to prevent EL1 from being
5072 * able to make SMC calls into the ersatz firmware, so in
5073 * that case HCR.TSC should be read/write.
5075 valid_mask
&= ~HCR_TSC
;
5078 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5079 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5080 valid_mask
|= HCR_E2H
;
5082 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5083 valid_mask
|= HCR_TERR
| HCR_TEA
;
5085 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5086 valid_mask
|= HCR_TLOR
;
5088 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5089 valid_mask
|= HCR_API
| HCR_APK
;
5091 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5092 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5094 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5095 valid_mask
|= HCR_ENSCXT
;
5097 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5098 valid_mask
|= HCR_FWB
;
5102 /* Clear RES0 bits. */
5103 value
&= valid_mask
;
5106 * These bits change the MMU setup:
5107 * HCR_VM enables stage 2 translation
5108 * HCR_PTW forbids certain page-table setups
5109 * HCR_DC disables stage1 and enables stage2 translation
5110 * HCR_DCT enables tagging on (disabled) stage1 translation
5111 * HCR_FWB changes the interpretation of stage2 descriptor bits
5113 if ((env
->cp15
.hcr_el2
^ value
) &
5114 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5115 tlb_flush(CPU(cpu
));
5117 env
->cp15
.hcr_el2
= value
;
5120 * Updates to VI and VF require us to update the status of
5121 * virtual interrupts, which are the logical OR of these bits
5122 * and the state of the input lines from the GIC. (This requires
5123 * that we have the iothread lock, which is done by marking the
5124 * reginfo structs as ARM_CP_IO.)
5125 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5126 * possible for it to be taken immediately, because VIRQ and
5127 * VFIQ are masked unless running at EL0 or EL1, and HCR
5128 * can only be written at EL2.
5130 g_assert(qemu_mutex_iothread_locked());
5131 arm_cpu_update_virq(cpu
);
5132 arm_cpu_update_vfiq(cpu
);
5133 arm_cpu_update_vserr(cpu
);
5136 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5138 do_hcr_write(env
, value
, 0);
5141 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5144 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5145 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5146 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5149 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5152 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5153 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5154 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5158 * Return the effective value of HCR_EL2.
5159 * Bits that are not included here:
5160 * RW (read from SCR_EL3.RW as needed)
5162 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5164 uint64_t ret
= env
->cp15
.hcr_el2
;
5166 if (!arm_is_el2_enabled(env
)) {
5168 * "This register has no effect if EL2 is not enabled in the
5169 * current Security state". This is ARMv8.4-SecEL2 speak for
5170 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5172 * Prior to that, the language was "In an implementation that
5173 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5174 * as if this field is 0 for all purposes other than a direct
5175 * read or write access of HCR_EL2". With lots of enumeration
5176 * on a per-field basis. In current QEMU, this is condition
5177 * is arm_is_secure_below_el3.
5179 * Since the v8.4 language applies to the entire register, and
5180 * appears to be backward compatible, use that.
5186 * For a cpu that supports both aarch64 and aarch32, we can set bits
5187 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5188 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5190 if (!arm_el_is_aa64(env
, 2)) {
5191 uint64_t aa32_valid
;
5194 * These bits are up-to-date as of ARMv8.6.
5195 * For HCR, it's easiest to list just the 2 bits that are invalid.
5196 * For HCR2, list those that are valid.
5198 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5199 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5200 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5204 if (ret
& HCR_TGE
) {
5205 /* These bits are up-to-date as of ARMv8.6. */
5206 if (ret
& HCR_E2H
) {
5207 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5208 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5209 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5210 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5211 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5212 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5214 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5216 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5217 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5218 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5226 * Corresponds to ARM pseudocode function ELIsInHost().
5228 bool el_is_in_host(CPUARMState
*env
, int el
)
5233 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5234 * Perform the simplest bit tests first, and validate EL2 afterward.
5237 return false; /* EL1 or EL3 */
5241 * Note that hcr_write() checks isar_feature_aa64_vh(),
5242 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5244 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5245 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5249 /* TGE and/or E2H set: double check those bits are currently legal. */
5250 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5253 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5256 uint64_t valid_mask
= 0;
5258 /* No features adding bits to HCRX are implemented. */
5260 /* Clear RES0 bits. */
5261 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5264 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5267 if (arm_current_el(env
) < 3
5268 && arm_feature(env
, ARM_FEATURE_EL3
)
5269 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5270 return CP_ACCESS_TRAP_EL3
;
5272 return CP_ACCESS_OK
;
5275 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5276 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5277 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5278 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5279 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5282 /* Return the effective value of HCRX_EL2. */
5283 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5286 * The bits in this register behave as 0 for all purposes other than
5287 * direct reads of the register if:
5288 * - EL2 is not enabled in the current security state,
5289 * - SCR_EL3.HXEn is 0.
5291 if (!arm_is_el2_enabled(env
)
5292 || (arm_feature(env
, ARM_FEATURE_EL3
)
5293 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5296 return env
->cp15
.hcrx_el2
;
5299 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5303 * For A-profile AArch32 EL3, if NSACR.CP10
5304 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5306 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5307 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5308 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5309 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5311 env
->cp15
.cptr_el
[2] = value
;
5314 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5317 * For A-profile AArch32 EL3, if NSACR.CP10
5318 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5320 uint64_t value
= env
->cp15
.cptr_el
[2];
5322 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5323 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5324 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5329 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5330 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5332 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5333 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5334 .writefn
= hcr_write
},
5335 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5336 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5337 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5338 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5339 .writefn
= hcr_writelow
},
5340 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5341 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5342 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5343 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5344 .type
= ARM_CP_ALIAS
,
5345 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5347 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5348 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5349 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5350 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5351 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5352 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5353 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5354 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5355 .type
= ARM_CP_ALIAS
,
5356 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5358 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5359 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5360 .type
= ARM_CP_ALIAS
,
5361 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5363 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5364 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5365 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5366 .access
= PL2_RW
, .writefn
= vbar_write
,
5367 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5369 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5370 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5371 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5372 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5373 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5374 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5375 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5376 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5377 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5378 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5379 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5380 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5382 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5383 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5384 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5385 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5386 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5387 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5388 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5390 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5391 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5392 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5393 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5395 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5396 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5397 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5399 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5400 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5401 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5403 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5404 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5405 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5406 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5407 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5408 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5409 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5410 .type
= ARM_CP_ALIAS
,
5411 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5412 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5413 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5414 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5416 /* no .writefn needed as this can't cause an ASID change;
5417 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5419 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5420 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5421 .cp
= 15, .opc1
= 6, .crm
= 2,
5422 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5423 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5424 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5425 .writefn
= vttbr_write
},
5426 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5427 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5428 .access
= PL2_RW
, .writefn
= vttbr_write
,
5429 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5430 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5431 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5432 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5433 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5434 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5435 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5436 .access
= PL2_RW
, .resetvalue
= 0,
5437 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5438 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5439 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5440 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5441 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5442 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5443 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5444 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5445 { .name
= "TLBIALLNSNH",
5446 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5447 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5448 .writefn
= tlbiall_nsnh_write
},
5449 { .name
= "TLBIALLNSNHIS",
5450 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5451 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5452 .writefn
= tlbiall_nsnh_is_write
},
5453 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5454 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5455 .writefn
= tlbiall_hyp_write
},
5456 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5457 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5458 .writefn
= tlbiall_hyp_is_write
},
5459 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5460 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5461 .writefn
= tlbimva_hyp_write
},
5462 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5463 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5464 .writefn
= tlbimva_hyp_is_write
},
5465 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5466 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5467 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5468 .writefn
= tlbi_aa64_alle2_write
},
5469 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5470 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5471 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5472 .writefn
= tlbi_aa64_vae2_write
},
5473 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5474 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5475 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5476 .writefn
= tlbi_aa64_vae2_write
},
5477 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5478 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5479 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5480 .writefn
= tlbi_aa64_alle2is_write
},
5481 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5482 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5483 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5484 .writefn
= tlbi_aa64_vae2is_write
},
5485 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5486 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5487 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5488 .writefn
= tlbi_aa64_vae2is_write
},
5489 #ifndef CONFIG_USER_ONLY
5490 /* Unlike the other EL2-related AT operations, these must
5491 * UNDEF from EL3 if EL2 is not implemented, which is why we
5492 * define them here rather than with the rest of the AT ops.
5494 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5495 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5496 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5497 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5498 .writefn
= ats_write64
},
5499 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5500 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5501 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5502 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5503 .writefn
= ats_write64
},
5504 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5505 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5506 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5507 * to behave as if SCR.NS was 1.
5509 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5511 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5512 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5514 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5515 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5516 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5517 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5518 * reset values as IMPDEF. We choose to reset to 3 to comply with
5519 * both ARMv7 and ARMv8.
5521 .access
= PL2_RW
, .resetvalue
= 3,
5522 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5523 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5524 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5525 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5526 .writefn
= gt_cntvoff_write
,
5527 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5528 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5529 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5530 .writefn
= gt_cntvoff_write
,
5531 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5532 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5533 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5534 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5535 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5536 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5537 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5539 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5540 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5541 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5542 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5543 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5544 .resetfn
= gt_hyp_timer_reset
,
5545 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5546 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5548 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5550 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5552 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5554 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5555 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5556 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5557 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5558 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5559 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5561 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5562 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5563 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5565 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5568 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5569 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5570 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5571 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5573 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5574 .writefn
= hcr_writehigh
},
5577 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5580 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5581 return CP_ACCESS_OK
;
5583 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5586 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5587 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5588 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5589 .access
= PL2_RW
, .accessfn
= sel2_access
,
5590 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5591 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5592 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5593 .access
= PL2_RW
, .accessfn
= sel2_access
,
5594 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5597 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5600 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5601 * At Secure EL1 it traps to EL3 or EL2.
5603 if (arm_current_el(env
) == 3) {
5604 return CP_ACCESS_OK
;
5606 if (arm_is_secure_below_el3(env
)) {
5607 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5608 return CP_ACCESS_TRAP_EL2
;
5610 return CP_ACCESS_TRAP_EL3
;
5612 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5614 return CP_ACCESS_OK
;
5616 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5619 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5620 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5621 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5622 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5623 .resetfn
= scr_reset
, .writefn
= scr_write
},
5624 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5625 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5626 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5627 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5628 .writefn
= scr_write
},
5629 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5630 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5631 .access
= PL3_RW
, .resetvalue
= 0,
5632 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5634 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5635 .access
= PL3_RW
, .resetvalue
= 0,
5636 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5637 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5638 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5639 .writefn
= vbar_write
, .resetvalue
= 0,
5640 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5641 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5642 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5643 .access
= PL3_RW
, .resetvalue
= 0,
5644 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5645 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5646 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5648 /* no .writefn needed as this can't cause an ASID change;
5649 * we must provide a .raw_writefn and .resetfn because we handle
5650 * reset and migration for the AArch32 TTBCR(S), which might be
5651 * using mask and base_mask.
5653 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5654 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5655 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5656 .type
= ARM_CP_ALIAS
,
5657 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5659 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5660 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5661 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5662 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5663 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5664 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5665 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5666 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5667 .type
= ARM_CP_ALIAS
,
5668 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5670 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5671 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5672 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5673 .access
= PL3_RW
, .writefn
= vbar_write
,
5674 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5676 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5677 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5678 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5679 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5680 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5681 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5682 .access
= PL3_RW
, .resetvalue
= 0,
5683 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5684 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5685 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5686 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5688 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5689 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5690 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5692 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5693 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5694 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5696 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5697 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5698 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5699 .writefn
= tlbi_aa64_alle3is_write
},
5700 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5701 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5702 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5703 .writefn
= tlbi_aa64_vae3is_write
},
5704 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5705 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5706 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5707 .writefn
= tlbi_aa64_vae3is_write
},
5708 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5709 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5710 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5711 .writefn
= tlbi_aa64_alle3_write
},
5712 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5713 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5714 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5715 .writefn
= tlbi_aa64_vae3_write
},
5716 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5717 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5718 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5719 .writefn
= tlbi_aa64_vae3_write
},
5722 #ifndef CONFIG_USER_ONLY
5723 /* Test if system register redirection is to occur in the current state. */
5724 static bool redirect_for_e2h(CPUARMState
*env
)
5726 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5729 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5733 if (redirect_for_e2h(env
)) {
5734 /* Switch to the saved EL2 version of the register. */
5736 readfn
= ri
->readfn
;
5738 readfn
= ri
->orig_readfn
;
5740 if (readfn
== NULL
) {
5743 return readfn(env
, ri
);
5746 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5751 if (redirect_for_e2h(env
)) {
5752 /* Switch to the saved EL2 version of the register. */
5754 writefn
= ri
->writefn
;
5756 writefn
= ri
->orig_writefn
;
5758 if (writefn
== NULL
) {
5759 writefn
= raw_write
;
5761 writefn(env
, ri
, value
);
5764 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5767 uint32_t src_key
, dst_key
, new_key
;
5768 const char *src_name
, *dst_name
, *new_name
;
5769 bool (*feature
)(const ARMISARegisters
*id
);
5772 #define K(op0, op1, crn, crm, op2) \
5773 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5775 static const struct E2HAlias aliases
[] = {
5776 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5777 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5778 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5779 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5780 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5781 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5782 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5783 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5784 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5785 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5786 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5787 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5788 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5789 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5790 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5791 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5792 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5793 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5794 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5795 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5796 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5797 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5798 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5799 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5800 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5801 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5802 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5803 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5804 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5805 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5806 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5807 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5810 * Note that redirection of ZCR is mentioned in the description
5811 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5812 * not in the summary table.
5814 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5815 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5816 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
5817 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
5819 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5820 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5822 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
5823 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
5824 isar_feature_aa64_scxtnum
},
5826 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5827 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5833 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5834 const struct E2HAlias
*a
= &aliases
[i
];
5835 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
5838 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5842 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5843 (gpointer
)(uintptr_t)a
->src_key
);
5844 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5845 (gpointer
)(uintptr_t)a
->dst_key
);
5846 g_assert(src_reg
!= NULL
);
5847 g_assert(dst_reg
!= NULL
);
5849 /* Cross-compare names to detect typos in the keys. */
5850 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5851 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5853 /* None of the core system registers use opaque; we will. */
5854 g_assert(src_reg
->opaque
== NULL
);
5856 /* Create alias before redirection so we dup the right data. */
5857 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5859 new_reg
->name
= a
->new_name
;
5860 new_reg
->type
|= ARM_CP_ALIAS
;
5861 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5862 new_reg
->access
&= PL2_RW
| PL3_RW
;
5864 ok
= g_hash_table_insert(cpu
->cp_regs
,
5865 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
5868 src_reg
->opaque
= dst_reg
;
5869 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5870 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5871 if (!src_reg
->raw_readfn
) {
5872 src_reg
->raw_readfn
= raw_read
;
5874 if (!src_reg
->raw_writefn
) {
5875 src_reg
->raw_writefn
= raw_write
;
5877 src_reg
->readfn
= el2_e2h_read
;
5878 src_reg
->writefn
= el2_e2h_write
;
5883 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5886 int cur_el
= arm_current_el(env
);
5889 uint64_t hcr
= arm_hcr_el2_eff(env
);
5892 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5893 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5894 return CP_ACCESS_TRAP_EL2
;
5897 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5898 return CP_ACCESS_TRAP
;
5900 if (hcr
& HCR_TID2
) {
5901 return CP_ACCESS_TRAP_EL2
;
5904 } else if (hcr
& HCR_TID2
) {
5905 return CP_ACCESS_TRAP_EL2
;
5909 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5910 return CP_ACCESS_TRAP_EL2
;
5913 return CP_ACCESS_OK
;
5917 * Check for traps to RAS registers, which are controlled
5918 * by HCR_EL2.TERR and SCR_EL3.TERR.
5920 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5923 int el
= arm_current_el(env
);
5925 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
5926 return CP_ACCESS_TRAP_EL2
;
5928 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
5929 return CP_ACCESS_TRAP_EL3
;
5931 return CP_ACCESS_OK
;
5934 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5936 int el
= arm_current_el(env
);
5938 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
5939 return env
->cp15
.vdisr_el2
;
5941 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
5942 return 0; /* RAZ/WI */
5944 return env
->cp15
.disr_el1
;
5947 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5949 int el
= arm_current_el(env
);
5951 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
5952 env
->cp15
.vdisr_el2
= val
;
5955 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
5956 return; /* RAZ/WI */
5958 env
->cp15
.disr_el1
= val
;
5962 * Minimal RAS implementation with no Error Records.
5963 * Which means that all of the Error Record registers:
5971 * ERXPFGCDN_EL1 (RASv1p1)
5972 * ERXPFGCTL_EL1 (RASv1p1)
5973 * ERXPFGF_EL1 (RASv1p1)
5977 * may generate UNDEFINED, which is the effect we get by not
5978 * listing them at all.
5980 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
5981 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
5982 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
5983 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
5984 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
5985 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5986 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
5987 .access
= PL1_R
, .accessfn
= access_terr
,
5988 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5989 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
5990 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
5991 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
5992 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5993 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
5994 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
5998 * Return the exception level to which exceptions should be taken
5999 * via SVEAccessTrap. This excludes the check for whether the exception
6000 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6001 * be found by testing 0 < fp_exception_el < sve_exception_el.
6003 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6004 * pseudocode does *not* separate out the FP trap checks, but has them
6005 * all in one function.
6007 int sve_exception_el(CPUARMState
*env
, int el
)
6009 #ifndef CONFIG_USER_ONLY
6010 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6011 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6023 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6024 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6025 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6026 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6028 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6037 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6043 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6044 if (arm_feature(env
, ARM_FEATURE_EL3
)
6045 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6053 * Return the exception level to which exceptions should be taken for SME.
6054 * C.f. the ARM pseudocode function CheckSMEAccess.
6056 int sme_exception_el(CPUARMState
*env
, int el
)
6058 #ifndef CONFIG_USER_ONLY
6059 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6060 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6072 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6073 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6074 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6075 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6077 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6086 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6092 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6093 if (arm_feature(env
, ARM_FEATURE_EL3
)
6094 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6101 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
6102 static bool sme_fa64(CPUARMState
*env
, int el
)
6104 if (!cpu_isar_feature(aa64_sme_fa64
, env_archcpu(env
))) {
6108 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6109 if (!FIELD_EX64(env
->vfp
.smcr_el
[1], SMCR
, FA64
)) {
6113 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6114 if (!FIELD_EX64(env
->vfp
.smcr_el
[2], SMCR
, FA64
)) {
6118 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6119 if (!FIELD_EX64(env
->vfp
.smcr_el
[3], SMCR
, FA64
)) {
6128 * Given that SVE is enabled, return the vector length for EL.
6130 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6132 ARMCPU
*cpu
= env_archcpu(env
);
6133 uint64_t *cr
= env
->vfp
.zcr_el
;
6134 uint32_t map
= cpu
->sve_vq
.map
;
6135 uint32_t len
= ARM_MAX_VQ
- 1;
6138 cr
= env
->vfp
.smcr_el
;
6139 map
= cpu
->sme_vq
.map
;
6142 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6143 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6145 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6146 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6148 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6149 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6152 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6154 return 31 - clz32(map
);
6157 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6159 return ctz32(cpu
->sme_vq
.map
);
6162 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6164 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6167 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6170 int cur_el
= arm_current_el(env
);
6171 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6174 /* Bits other than [3:0] are RAZ/WI. */
6175 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6176 raw_write(env
, ri
, value
& 0xf);
6179 * Because we arrived here, we know both FP and SVE are enabled;
6180 * otherwise we would have trapped access to the ZCR_ELn register.
6182 new_len
= sve_vqm1_for_el(env
, cur_el
);
6183 if (new_len
< old_len
) {
6184 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6188 static const ARMCPRegInfo zcr_reginfo
[] = {
6189 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6190 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6191 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6192 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6193 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6194 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6195 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6196 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6197 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6198 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6199 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6200 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6201 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6202 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6203 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6206 #ifdef TARGET_AARCH64
6207 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6210 int el
= arm_current_el(env
);
6213 uint64_t sctlr
= arm_sctlr(env
, el
);
6214 if (!(sctlr
& SCTLR_EnTP2
)) {
6215 return CP_ACCESS_TRAP
;
6218 /* TODO: FEAT_FGT */
6220 && arm_feature(env
, ARM_FEATURE_EL3
)
6221 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6222 return CP_ACCESS_TRAP_EL3
;
6224 return CP_ACCESS_OK
;
6227 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6230 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6231 if (arm_current_el(env
) < 3
6232 && arm_feature(env
, ARM_FEATURE_EL3
)
6233 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6234 return CP_ACCESS_TRAP_EL3
;
6236 return CP_ACCESS_OK
;
6239 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6242 helper_set_pstate_sm(env
, FIELD_EX64(value
, SVCR
, SM
));
6243 helper_set_pstate_za(env
, FIELD_EX64(value
, SVCR
, ZA
));
6244 arm_rebuild_hflags(env
);
6247 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6250 int cur_el
= arm_current_el(env
);
6251 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6254 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6255 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6256 raw_write(env
, ri
, value
);
6259 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6260 * when SVL is widened (old values kept, or zeros). Choose to keep the
6261 * current values for simplicity. But for QEMU internals, we must still
6262 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6263 * above aarch64_sve_narrow_vq.
6265 new_len
= sve_vqm1_for_el(env
, cur_el
);
6266 if (new_len
< old_len
) {
6267 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6271 static const ARMCPRegInfo sme_reginfo
[] = {
6272 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6273 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6274 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6275 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6276 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
6277 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
6278 .access
= PL0_RW
, .type
= ARM_CP_SME
,
6279 .fieldoffset
= offsetof(CPUARMState
, svcr
),
6280 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
6281 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
6282 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
6283 .access
= PL1_RW
, .type
= ARM_CP_SME
,
6284 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
6285 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6286 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
6287 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
6288 .access
= PL2_RW
, .type
= ARM_CP_SME
,
6289 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
6290 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6291 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
6292 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
6293 .access
= PL3_RW
, .type
= ARM_CP_SME
,
6294 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
6295 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6296 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
6297 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
6298 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
6300 * IMPLEMENTOR = 0 (software)
6301 * REVISION = 0 (implementation defined)
6302 * SMPS = 0 (no streaming execution priority in QEMU)
6303 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
6305 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
6307 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
6309 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
6310 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
6311 .access
= PL1_RW
, .accessfn
= access_esm
,
6312 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6313 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
6314 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
6315 .access
= PL2_RW
, .accessfn
= access_esm
,
6316 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6318 #endif /* TARGET_AARCH64 */
6320 static void define_pmu_regs(ARMCPU
*cpu
)
6323 * v7 performance monitor control register: same implementor
6324 * field as main ID register, and we implement four counters in
6325 * addition to the cycle count register.
6327 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6328 ARMCPRegInfo pmcr
= {
6329 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6331 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6332 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6333 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6334 .raw_writefn
= raw_write
,
6336 ARMCPRegInfo pmcr64
= {
6337 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6338 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6339 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6341 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6342 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6343 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6346 define_one_arm_cp_reg(cpu
, &pmcr
);
6347 define_one_arm_cp_reg(cpu
, &pmcr64
);
6348 for (i
= 0; i
< pmcrn
; i
++) {
6349 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6350 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6351 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6352 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6353 ARMCPRegInfo pmev_regs
[] = {
6354 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6355 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6356 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6357 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6358 .accessfn
= pmreg_access_xevcntr
},
6359 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6360 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6361 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6363 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6364 .raw_readfn
= pmevcntr_rawread
,
6365 .raw_writefn
= pmevcntr_rawwrite
},
6366 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6367 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6368 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6369 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6370 .accessfn
= pmreg_access
},
6371 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6372 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6373 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6375 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6376 .raw_writefn
= pmevtyper_rawwrite
},
6378 define_arm_cp_regs(cpu
, pmev_regs
);
6379 g_free(pmevcntr_name
);
6380 g_free(pmevcntr_el0_name
);
6381 g_free(pmevtyper_name
);
6382 g_free(pmevtyper_el0_name
);
6384 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6385 ARMCPRegInfo v81_pmu_regs
[] = {
6386 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6387 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6388 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6389 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6390 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6391 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6392 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6393 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6395 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6397 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6398 static const ARMCPRegInfo v84_pmmir
= {
6399 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6400 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6401 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6404 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6408 /* We don't know until after realize whether there's a GICv3
6409 * attached, and that is what registers the gicv3 sysregs.
6410 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6413 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6415 ARMCPU
*cpu
= env_archcpu(env
);
6416 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6418 if (env
->gicv3state
) {
6424 #ifndef CONFIG_USER_ONLY
6425 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6427 ARMCPU
*cpu
= env_archcpu(env
);
6428 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6430 if (env
->gicv3state
) {
6437 /* Shared logic between LORID and the rest of the LOR* registers.
6438 * Secure state exclusion has already been dealt with.
6440 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6441 const ARMCPRegInfo
*ri
, bool isread
)
6443 int el
= arm_current_el(env
);
6445 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6446 return CP_ACCESS_TRAP_EL2
;
6448 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6449 return CP_ACCESS_TRAP_EL3
;
6451 return CP_ACCESS_OK
;
6454 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6455 const ARMCPRegInfo
*ri
, bool isread
)
6457 if (arm_is_secure_below_el3(env
)) {
6458 /* Access denied in secure mode. */
6459 return CP_ACCESS_TRAP
;
6461 return access_lor_ns(env
, ri
, isread
);
6465 * A trivial implementation of ARMv8.1-LOR leaves all of these
6466 * registers fixed at 0, which indicates that there are zero
6467 * supported Limited Ordering regions.
6469 static const ARMCPRegInfo lor_reginfo
[] = {
6470 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6471 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6472 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6473 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6474 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6475 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6476 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6477 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6478 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6479 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6480 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6481 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6482 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6483 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6484 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6485 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6486 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6487 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6488 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6489 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6492 #ifdef TARGET_AARCH64
6493 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6496 int el
= arm_current_el(env
);
6499 arm_is_el2_enabled(env
) &&
6500 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6501 return CP_ACCESS_TRAP_EL2
;
6504 arm_feature(env
, ARM_FEATURE_EL3
) &&
6505 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6506 return CP_ACCESS_TRAP_EL3
;
6508 return CP_ACCESS_OK
;
6511 static const ARMCPRegInfo pauth_reginfo
[] = {
6512 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6513 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6514 .access
= PL1_RW
, .accessfn
= access_pauth
,
6515 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6516 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6517 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6518 .access
= PL1_RW
, .accessfn
= access_pauth
,
6519 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6520 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6521 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6522 .access
= PL1_RW
, .accessfn
= access_pauth
,
6523 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6524 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6525 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6526 .access
= PL1_RW
, .accessfn
= access_pauth
,
6527 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6528 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6529 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6530 .access
= PL1_RW
, .accessfn
= access_pauth
,
6531 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6532 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6533 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6534 .access
= PL1_RW
, .accessfn
= access_pauth
,
6535 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6536 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6537 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6538 .access
= PL1_RW
, .accessfn
= access_pauth
,
6539 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6540 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6541 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6542 .access
= PL1_RW
, .accessfn
= access_pauth
,
6543 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6544 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6545 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6546 .access
= PL1_RW
, .accessfn
= access_pauth
,
6547 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6548 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6549 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6550 .access
= PL1_RW
, .accessfn
= access_pauth
,
6551 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6554 static const ARMCPRegInfo tlbirange_reginfo
[] = {
6555 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
6556 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
6557 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6558 .writefn
= tlbi_aa64_rvae1is_write
},
6559 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
6560 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
6561 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6562 .writefn
= tlbi_aa64_rvae1is_write
},
6563 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
6564 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
6565 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6566 .writefn
= tlbi_aa64_rvae1is_write
},
6567 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
6568 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
6569 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6570 .writefn
= tlbi_aa64_rvae1is_write
},
6571 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
6572 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
6573 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6574 .writefn
= tlbi_aa64_rvae1is_write
},
6575 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
6576 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
6577 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6578 .writefn
= tlbi_aa64_rvae1is_write
},
6579 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
6580 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
6581 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6582 .writefn
= tlbi_aa64_rvae1is_write
},
6583 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
6584 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
6585 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6586 .writefn
= tlbi_aa64_rvae1is_write
},
6587 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
6588 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
6589 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6590 .writefn
= tlbi_aa64_rvae1_write
},
6591 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
6592 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
6593 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6594 .writefn
= tlbi_aa64_rvae1_write
},
6595 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
6596 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
6597 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6598 .writefn
= tlbi_aa64_rvae1_write
},
6599 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
6600 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
6601 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6602 .writefn
= tlbi_aa64_rvae1_write
},
6603 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
6604 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
6605 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6606 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
6607 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
6608 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6609 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
6610 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
6611 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6612 .writefn
= tlbi_aa64_rvae2is_write
},
6613 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
6614 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
6615 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6616 .writefn
= tlbi_aa64_rvae2is_write
},
6617 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
6618 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
6619 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6620 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
6621 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
6622 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6623 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
6624 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
6625 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6626 .writefn
= tlbi_aa64_rvae2is_write
},
6627 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
6628 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
6629 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6630 .writefn
= tlbi_aa64_rvae2is_write
},
6631 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
6632 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
6633 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6634 .writefn
= tlbi_aa64_rvae2_write
},
6635 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
6636 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
6637 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6638 .writefn
= tlbi_aa64_rvae2_write
},
6639 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
6640 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
6641 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6642 .writefn
= tlbi_aa64_rvae3is_write
},
6643 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
6644 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
6645 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6646 .writefn
= tlbi_aa64_rvae3is_write
},
6647 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
6648 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
6649 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6650 .writefn
= tlbi_aa64_rvae3is_write
},
6651 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
6652 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
6653 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6654 .writefn
= tlbi_aa64_rvae3is_write
},
6655 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
6656 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
6657 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6658 .writefn
= tlbi_aa64_rvae3_write
},
6659 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
6660 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
6661 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6662 .writefn
= tlbi_aa64_rvae3_write
},
6665 static const ARMCPRegInfo tlbios_reginfo
[] = {
6666 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
6667 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
6668 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6669 .writefn
= tlbi_aa64_vmalle1is_write
},
6670 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
6671 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
6672 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6673 .writefn
= tlbi_aa64_vae1is_write
},
6674 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
6675 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
6676 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6677 .writefn
= tlbi_aa64_vmalle1is_write
},
6678 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
6679 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
6680 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6681 .writefn
= tlbi_aa64_vae1is_write
},
6682 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
6683 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
6684 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6685 .writefn
= tlbi_aa64_vae1is_write
},
6686 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
6687 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
6688 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6689 .writefn
= tlbi_aa64_vae1is_write
},
6690 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
6691 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
6692 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6693 .writefn
= tlbi_aa64_alle2is_write
},
6694 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
6695 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
6696 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6697 .writefn
= tlbi_aa64_vae2is_write
},
6698 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
6699 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
6700 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6701 .writefn
= tlbi_aa64_alle1is_write
},
6702 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
6703 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
6704 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6705 .writefn
= tlbi_aa64_vae2is_write
},
6706 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
6707 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
6708 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6709 .writefn
= tlbi_aa64_alle1is_write
},
6710 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6711 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
6712 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6713 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6714 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
6715 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6716 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6717 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
6718 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6719 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6720 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
6721 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6722 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
6723 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
6724 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6725 .writefn
= tlbi_aa64_alle3is_write
},
6726 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
6727 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
6728 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6729 .writefn
= tlbi_aa64_vae3is_write
},
6730 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
6731 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
6732 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6733 .writefn
= tlbi_aa64_vae3is_write
},
6736 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6741 /* Success sets NZCV = 0000. */
6742 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6744 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6746 * ??? Failed, for unknown reasons in the crypto subsystem.
6747 * The best we can do is log the reason and return the
6748 * timed-out indication to the guest. There is no reason
6749 * we know to expect this failure to be transitory, so the
6750 * guest may well hang retrying the operation.
6752 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6753 ri
->name
, error_get_pretty(err
));
6756 env
->ZF
= 0; /* NZCF = 0100 */
6762 /* We do not support re-seeding, so the two registers operate the same. */
6763 static const ARMCPRegInfo rndr_reginfo
[] = {
6764 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6765 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6766 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6767 .access
= PL0_R
, .readfn
= rndr_readfn
},
6768 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6769 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6770 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6771 .access
= PL0_R
, .readfn
= rndr_readfn
},
6774 #ifndef CONFIG_USER_ONLY
6775 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6778 ARMCPU
*cpu
= env_archcpu(env
);
6779 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6780 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6781 uint64_t vaddr_in
= (uint64_t) value
;
6782 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6784 int mem_idx
= cpu_mmu_index(env
, false);
6786 /* This won't be crossing page boundaries */
6787 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6793 /* RCU lock is already being held */
6794 mr
= memory_region_from_host(haddr
, &offset
);
6797 memory_region_writeback(mr
, offset
, dline_size
);
6802 static const ARMCPRegInfo dcpop_reg
[] = {
6803 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6804 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6805 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6806 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6809 static const ARMCPRegInfo dcpodp_reg
[] = {
6810 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6811 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6812 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6813 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6815 #endif /*CONFIG_USER_ONLY*/
6817 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6820 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
6821 return CP_ACCESS_TRAP_EL2
;
6824 return CP_ACCESS_OK
;
6827 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6830 int el
= arm_current_el(env
);
6832 if (el
< 2 && arm_is_el2_enabled(env
)) {
6833 uint64_t hcr
= arm_hcr_el2_eff(env
);
6834 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
6835 return CP_ACCESS_TRAP_EL2
;
6839 arm_feature(env
, ARM_FEATURE_EL3
) &&
6840 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
6841 return CP_ACCESS_TRAP_EL3
;
6843 return CP_ACCESS_OK
;
6846 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6848 return env
->pstate
& PSTATE_TCO
;
6851 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6853 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
6856 static const ARMCPRegInfo mte_reginfo
[] = {
6857 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
6858 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
6859 .access
= PL1_RW
, .accessfn
= access_mte
,
6860 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
6861 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
6862 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
6863 .access
= PL1_RW
, .accessfn
= access_mte
,
6864 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
6865 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
6866 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
6867 .access
= PL2_RW
, .accessfn
= access_mte
,
6868 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
6869 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
6870 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
6872 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
6873 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
6874 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
6875 .access
= PL1_RW
, .accessfn
= access_mte
,
6876 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
6877 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
6878 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
6879 .access
= PL1_RW
, .accessfn
= access_mte
,
6880 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
6881 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
6882 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
6883 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
6884 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
6885 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6886 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6887 .type
= ARM_CP_NO_RAW
,
6888 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
6889 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
6890 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
6891 .type
= ARM_CP_NOP
, .access
= PL1_W
,
6892 .accessfn
= aa64_cacheop_poc_access
},
6893 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
6894 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
6895 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6896 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
6897 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
6898 .type
= ARM_CP_NOP
, .access
= PL1_W
,
6899 .accessfn
= aa64_cacheop_poc_access
},
6900 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
6901 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
6902 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6903 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
6904 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
6905 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6906 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
6907 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
6908 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6909 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
6910 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
6911 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6912 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
6913 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
6914 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6917 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
6918 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6919 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6920 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
6923 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
6924 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
6925 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
6926 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6927 .accessfn
= aa64_cacheop_poc_access
},
6928 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
6929 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
6930 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6931 .accessfn
= aa64_cacheop_poc_access
},
6932 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
6933 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
6934 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6935 .accessfn
= aa64_cacheop_poc_access
},
6936 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
6937 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
6938 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6939 .accessfn
= aa64_cacheop_poc_access
},
6940 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
6941 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
6942 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6943 .accessfn
= aa64_cacheop_poc_access
},
6944 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
6945 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
6946 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6947 .accessfn
= aa64_cacheop_poc_access
},
6948 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
6949 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
6950 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6951 .accessfn
= aa64_cacheop_poc_access
},
6952 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
6953 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
6954 .type
= ARM_CP_NOP
, .access
= PL0_W
,
6955 .accessfn
= aa64_cacheop_poc_access
},
6956 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
6957 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
6958 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
6959 #ifndef CONFIG_USER_ONLY
6960 /* Avoid overhead of an access check that always passes in user-mode */
6961 .accessfn
= aa64_zva_access
,
6964 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
6965 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
6966 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
6967 #ifndef CONFIG_USER_ONLY
6968 /* Avoid overhead of an access check that always passes in user-mode */
6969 .accessfn
= aa64_zva_access
,
6974 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6977 uint64_t hcr
= arm_hcr_el2_eff(env
);
6978 int el
= arm_current_el(env
);
6980 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
6981 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
6982 if (hcr
& HCR_TGE
) {
6983 return CP_ACCESS_TRAP_EL2
;
6985 return CP_ACCESS_TRAP
;
6987 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
6988 return CP_ACCESS_TRAP_EL2
;
6990 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
6991 return CP_ACCESS_TRAP_EL2
;
6994 && arm_feature(env
, ARM_FEATURE_EL3
)
6995 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
6996 return CP_ACCESS_TRAP_EL3
;
6998 return CP_ACCESS_OK
;
7001 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7002 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7003 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7004 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7005 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7006 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7007 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7008 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7009 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7010 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7011 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7012 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7013 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7014 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7015 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7017 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7019 #endif /* TARGET_AARCH64 */
7021 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7024 int el
= arm_current_el(env
);
7027 uint64_t sctlr
= arm_sctlr(env
, el
);
7028 if (!(sctlr
& SCTLR_EnRCTX
)) {
7029 return CP_ACCESS_TRAP
;
7031 } else if (el
== 1) {
7032 uint64_t hcr
= arm_hcr_el2_eff(env
);
7034 return CP_ACCESS_TRAP_EL2
;
7037 return CP_ACCESS_OK
;
7040 static const ARMCPRegInfo predinv_reginfo
[] = {
7041 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7042 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7043 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7044 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7045 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7046 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7047 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7048 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7049 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7051 * Note the AArch32 opcodes have a different OPC1.
7053 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7054 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7055 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7056 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7057 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7058 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7059 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7060 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7061 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7064 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7066 /* Read the high 32 bits of the current CCSIDR */
7067 return extract64(ccsidr_read(env
, ri
), 32, 32);
7070 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7071 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7072 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7074 .accessfn
= access_aa64_tid2
,
7075 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7078 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7081 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7082 return CP_ACCESS_TRAP_EL2
;
7085 return CP_ACCESS_OK
;
7088 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7091 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7092 return access_aa64_tid3(env
, ri
, isread
);
7095 return CP_ACCESS_OK
;
7098 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7101 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7102 return CP_ACCESS_TRAP_EL2
;
7105 return CP_ACCESS_OK
;
7108 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7109 const ARMCPRegInfo
*ri
, bool isread
)
7112 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7113 * in v7A, not in v8A.
7115 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7116 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7117 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7118 return CP_ACCESS_TRAP_EL2
;
7120 return CP_ACCESS_OK
;
7123 static const ARMCPRegInfo jazelle_regs
[] = {
7125 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7126 .access
= PL1_R
, .accessfn
= access_jazelle
,
7127 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7129 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7130 .accessfn
= access_joscr_jmcr
,
7131 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7133 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7134 .accessfn
= access_joscr_jmcr
,
7135 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7138 static const ARMCPRegInfo contextidr_el2
= {
7139 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7140 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7142 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7145 static const ARMCPRegInfo vhe_reginfo
[] = {
7146 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7147 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7148 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7149 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7150 #ifndef CONFIG_USER_ONLY
7151 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7152 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7154 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7155 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7156 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7157 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7158 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7159 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7160 .resetfn
= gt_hv_timer_reset
,
7161 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7162 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7164 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7166 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7167 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7168 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7170 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7171 .access
= PL2_RW
, .accessfn
= e2h_access
,
7172 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7173 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7174 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7175 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7176 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7177 .access
= PL2_RW
, .accessfn
= e2h_access
,
7178 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7179 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7180 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7181 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7182 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7183 .access
= PL2_RW
, .accessfn
= e2h_access
,
7184 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7185 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7186 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7187 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7188 .access
= PL2_RW
, .accessfn
= e2h_access
,
7189 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7190 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7191 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7192 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7193 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7194 .access
= PL2_RW
, .accessfn
= e2h_access
,
7195 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7196 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7198 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7199 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7200 .access
= PL2_RW
, .accessfn
= e2h_access
,
7201 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7205 #ifndef CONFIG_USER_ONLY
7206 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7207 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7208 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7209 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7210 .writefn
= ats_write64
},
7211 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7212 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7213 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7214 .writefn
= ats_write64
},
7217 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7218 { .name
= "ATS1CPRP",
7219 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7220 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7221 .writefn
= ats_write
},
7222 { .name
= "ATS1CPWP",
7223 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7224 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7225 .writefn
= ats_write
},
7230 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7231 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7232 * is non-zero, which is never for ARMv7, optionally in ARMv8
7233 * and mandatorily for ARMv8.2 and up.
7234 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7235 * implementation is RAZ/WI we can ignore this detail, as we
7238 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7239 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7240 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7241 .access
= PL1_RW
, .accessfn
= access_tacr
,
7242 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7243 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7244 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7245 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7249 void register_cp_regs_for_features(ARMCPU
*cpu
)
7251 /* Register all the coprocessor registers based on feature bits */
7252 CPUARMState
*env
= &cpu
->env
;
7253 if (arm_feature(env
, ARM_FEATURE_M
)) {
7254 /* M profile has no coprocessor registers */
7258 define_arm_cp_regs(cpu
, cp_reginfo
);
7259 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7260 /* Must go early as it is full of wildcards that may be
7261 * overridden by later definitions.
7263 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7266 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7267 /* The ID registers all have impdef reset values */
7268 ARMCPRegInfo v6_idregs
[] = {
7269 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7270 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7271 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7272 .accessfn
= access_aa32_tid3
,
7273 .resetvalue
= cpu
->isar
.id_pfr0
},
7274 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7275 * the value of the GIC field until after we define these regs.
7277 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7278 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7279 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7280 .accessfn
= access_aa32_tid3
,
7281 .readfn
= id_pfr1_read
,
7282 .writefn
= arm_cp_write_ignore
},
7283 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7284 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7285 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7286 .accessfn
= access_aa32_tid3
,
7287 .resetvalue
= cpu
->isar
.id_dfr0
},
7288 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7289 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7290 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7291 .accessfn
= access_aa32_tid3
,
7292 .resetvalue
= cpu
->id_afr0
},
7293 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7294 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7295 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7296 .accessfn
= access_aa32_tid3
,
7297 .resetvalue
= cpu
->isar
.id_mmfr0
},
7298 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7299 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7300 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7301 .accessfn
= access_aa32_tid3
,
7302 .resetvalue
= cpu
->isar
.id_mmfr1
},
7303 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7304 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7305 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7306 .accessfn
= access_aa32_tid3
,
7307 .resetvalue
= cpu
->isar
.id_mmfr2
},
7308 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7309 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7310 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7311 .accessfn
= access_aa32_tid3
,
7312 .resetvalue
= cpu
->isar
.id_mmfr3
},
7313 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7314 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7315 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7316 .accessfn
= access_aa32_tid3
,
7317 .resetvalue
= cpu
->isar
.id_isar0
},
7318 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7319 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7320 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7321 .accessfn
= access_aa32_tid3
,
7322 .resetvalue
= cpu
->isar
.id_isar1
},
7323 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7324 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7325 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7326 .accessfn
= access_aa32_tid3
,
7327 .resetvalue
= cpu
->isar
.id_isar2
},
7328 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7329 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7330 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7331 .accessfn
= access_aa32_tid3
,
7332 .resetvalue
= cpu
->isar
.id_isar3
},
7333 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7334 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7335 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7336 .accessfn
= access_aa32_tid3
,
7337 .resetvalue
= cpu
->isar
.id_isar4
},
7338 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7339 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7340 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7341 .accessfn
= access_aa32_tid3
,
7342 .resetvalue
= cpu
->isar
.id_isar5
},
7343 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7344 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7345 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7346 .accessfn
= access_aa32_tid3
,
7347 .resetvalue
= cpu
->isar
.id_mmfr4
},
7348 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7349 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7350 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7351 .accessfn
= access_aa32_tid3
,
7352 .resetvalue
= cpu
->isar
.id_isar6
},
7354 define_arm_cp_regs(cpu
, v6_idregs
);
7355 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7357 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7359 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7360 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7362 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7363 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7364 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7366 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7367 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7369 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7370 ARMCPRegInfo clidr
= {
7371 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7372 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7373 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7374 .accessfn
= access_aa64_tid2
,
7375 .resetvalue
= cpu
->clidr
7377 define_one_arm_cp_reg(cpu
, &clidr
);
7378 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7379 define_debug_regs(cpu
);
7380 define_pmu_regs(cpu
);
7382 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7384 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7385 /* AArch64 ID registers, which all have impdef reset values.
7386 * Note that within the ID register ranges the unused slots
7387 * must all RAZ, not UNDEF; future architecture versions may
7388 * define new registers here.
7390 ARMCPRegInfo v8_idregs
[] = {
7392 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7393 * emulation because we don't know the right value for the
7394 * GIC field until after we define these regs.
7396 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7397 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7399 #ifdef CONFIG_USER_ONLY
7400 .type
= ARM_CP_CONST
,
7401 .resetvalue
= cpu
->isar
.id_aa64pfr0
7403 .type
= ARM_CP_NO_RAW
,
7404 .accessfn
= access_aa64_tid3
,
7405 .readfn
= id_aa64pfr0_read
,
7406 .writefn
= arm_cp_write_ignore
7409 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7410 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7411 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7412 .accessfn
= access_aa64_tid3
,
7413 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7414 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7415 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7416 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7417 .accessfn
= access_aa64_tid3
,
7419 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7420 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7421 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7422 .accessfn
= access_aa64_tid3
,
7424 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7425 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7426 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7427 .accessfn
= access_aa64_tid3
,
7428 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7429 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7430 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7431 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7432 .accessfn
= access_aa64_tid3
,
7433 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
7434 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7435 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7436 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7437 .accessfn
= access_aa64_tid3
,
7439 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7440 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7441 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7442 .accessfn
= access_aa64_tid3
,
7444 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7445 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7446 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7447 .accessfn
= access_aa64_tid3
,
7448 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7449 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7450 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7451 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7452 .accessfn
= access_aa64_tid3
,
7453 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7454 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7455 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7456 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7457 .accessfn
= access_aa64_tid3
,
7459 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7460 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7461 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7462 .accessfn
= access_aa64_tid3
,
7464 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7465 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7466 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7467 .accessfn
= access_aa64_tid3
,
7468 .resetvalue
= cpu
->id_aa64afr0
},
7469 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7470 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7471 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7472 .accessfn
= access_aa64_tid3
,
7473 .resetvalue
= cpu
->id_aa64afr1
},
7474 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7475 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7476 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7477 .accessfn
= access_aa64_tid3
,
7479 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7480 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7481 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7482 .accessfn
= access_aa64_tid3
,
7484 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7485 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7486 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7487 .accessfn
= access_aa64_tid3
,
7488 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7489 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7490 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7491 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7492 .accessfn
= access_aa64_tid3
,
7493 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7494 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7495 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7496 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7497 .accessfn
= access_aa64_tid3
,
7499 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7500 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7501 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7502 .accessfn
= access_aa64_tid3
,
7504 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7505 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7506 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7507 .accessfn
= access_aa64_tid3
,
7509 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7510 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7511 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7512 .accessfn
= access_aa64_tid3
,
7514 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7515 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7516 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7517 .accessfn
= access_aa64_tid3
,
7519 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7520 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7521 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7522 .accessfn
= access_aa64_tid3
,
7524 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7525 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7526 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7527 .accessfn
= access_aa64_tid3
,
7528 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7529 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7531 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7532 .accessfn
= access_aa64_tid3
,
7533 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7534 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7535 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7536 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7537 .accessfn
= access_aa64_tid3
,
7538 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7539 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7540 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7541 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7542 .accessfn
= access_aa64_tid3
,
7544 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7545 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7546 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7547 .accessfn
= access_aa64_tid3
,
7549 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7550 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7551 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7552 .accessfn
= access_aa64_tid3
,
7554 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7557 .accessfn
= access_aa64_tid3
,
7559 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7562 .accessfn
= access_aa64_tid3
,
7564 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7567 .accessfn
= access_aa64_tid3
,
7568 .resetvalue
= cpu
->isar
.mvfr0
},
7569 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7570 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7571 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7572 .accessfn
= access_aa64_tid3
,
7573 .resetvalue
= cpu
->isar
.mvfr1
},
7574 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7575 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7576 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7577 .accessfn
= access_aa64_tid3
,
7578 .resetvalue
= cpu
->isar
.mvfr2
},
7579 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7580 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7581 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7582 .accessfn
= access_aa64_tid3
,
7584 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7585 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7586 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7587 .accessfn
= access_aa64_tid3
,
7588 .resetvalue
= cpu
->isar
.id_pfr2
},
7589 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7590 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7591 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7592 .accessfn
= access_aa64_tid3
,
7594 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7595 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7596 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7597 .accessfn
= access_aa64_tid3
,
7599 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7600 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7601 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7602 .accessfn
= access_aa64_tid3
,
7604 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7605 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7606 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7607 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7608 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7609 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7610 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7611 .resetvalue
= cpu
->pmceid0
},
7612 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7613 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7614 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7615 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7616 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7617 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7618 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7619 .resetvalue
= cpu
->pmceid1
},
7621 #ifdef CONFIG_USER_ONLY
7622 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7623 { .name
= "ID_AA64PFR0_EL1",
7624 .exported_bits
= 0x000f000f00ff0000,
7625 .fixed_bits
= 0x0000000000000011 },
7626 { .name
= "ID_AA64PFR1_EL1",
7627 .exported_bits
= 0x00000000000000f0 },
7628 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7630 { .name
= "ID_AA64ZFR0_EL1" },
7631 { .name
= "ID_AA64MMFR0_EL1",
7632 .fixed_bits
= 0x00000000ff000000 },
7633 { .name
= "ID_AA64MMFR1_EL1" },
7634 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7636 { .name
= "ID_AA64DFR0_EL1",
7637 .fixed_bits
= 0x0000000000000006 },
7638 { .name
= "ID_AA64DFR1_EL1" },
7639 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7641 { .name
= "ID_AA64AFR*",
7643 { .name
= "ID_AA64ISAR0_EL1",
7644 .exported_bits
= 0x00fffffff0fffff0 },
7645 { .name
= "ID_AA64ISAR1_EL1",
7646 .exported_bits
= 0x000000f0ffffffff },
7647 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7650 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7652 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7653 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7654 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7655 ARMCPRegInfo rvbar
= {
7656 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7657 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7659 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7661 define_one_arm_cp_reg(cpu
, &rvbar
);
7663 define_arm_cp_regs(cpu
, v8_idregs
);
7664 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7668 * Register the base EL2 cpregs.
7669 * Pre v8, these registers are implemented only as part of the
7670 * Virtualization Extensions (EL2 present). Beginning with v8,
7671 * if EL2 is missing but EL3 is enabled, mostly these become
7672 * RES0 from EL3, with some specific exceptions.
7674 if (arm_feature(env
, ARM_FEATURE_EL2
)
7675 || (arm_feature(env
, ARM_FEATURE_EL3
)
7676 && arm_feature(env
, ARM_FEATURE_V8
))) {
7677 uint64_t vmpidr_def
= mpidr_read_val(env
);
7678 ARMCPRegInfo vpidr_regs
[] = {
7679 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7680 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7681 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7682 .resetvalue
= cpu
->midr
,
7683 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7684 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7685 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7686 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7687 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7688 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7689 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7690 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7691 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7692 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7693 .resetvalue
= vmpidr_def
,
7694 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7695 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7696 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7697 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7698 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
7699 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7700 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7703 * The only field of MDCR_EL2 that has a defined architectural reset
7704 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
7706 ARMCPRegInfo mdcr_el2
= {
7707 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
7708 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
7709 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
7710 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
7712 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
7713 define_arm_cp_regs(cpu
, vpidr_regs
);
7714 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7715 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7716 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7718 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
7719 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
7721 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7722 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7723 ARMCPRegInfo rvbar
= {
7724 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7725 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7727 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7729 define_one_arm_cp_reg(cpu
, &rvbar
);
7733 /* Register the base EL3 cpregs. */
7734 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7735 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7736 ARMCPRegInfo el3_regs
[] = {
7737 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7738 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7740 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7742 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7743 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7745 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7746 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7747 .resetvalue
= cpu
->reset_sctlr
},
7750 define_arm_cp_regs(cpu
, el3_regs
);
7752 /* The behaviour of NSACR is sufficiently various that we don't
7753 * try to describe it in a single reginfo:
7754 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7755 * reads as constant 0xc00 from NS EL1 and NS EL2
7756 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7757 * if v7 without EL3, register doesn't exist
7758 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7760 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7761 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7762 static const ARMCPRegInfo nsacr
= {
7763 .name
= "NSACR", .type
= ARM_CP_CONST
,
7764 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7765 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7768 define_one_arm_cp_reg(cpu
, &nsacr
);
7770 static const ARMCPRegInfo nsacr
= {
7772 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7773 .access
= PL3_RW
| PL1_R
,
7775 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7777 define_one_arm_cp_reg(cpu
, &nsacr
);
7780 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7781 static const ARMCPRegInfo nsacr
= {
7782 .name
= "NSACR", .type
= ARM_CP_CONST
,
7783 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7787 define_one_arm_cp_reg(cpu
, &nsacr
);
7791 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7792 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7793 /* PMSAv6 not implemented */
7794 assert(arm_feature(env
, ARM_FEATURE_V7
));
7795 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7796 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7798 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7801 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7802 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7803 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7804 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
7805 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7808 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7809 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7811 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7812 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7814 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7815 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7817 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7818 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7820 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7821 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7823 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7824 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7826 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7827 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7829 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7830 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7832 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7833 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7835 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7836 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7838 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7839 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7841 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
7842 define_arm_cp_regs(cpu
, jazelle_regs
);
7844 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7845 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7846 * be read-only (ie write causes UNDEF exception).
7849 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7850 /* Pre-v8 MIDR space.
7851 * Note that the MIDR isn't a simple constant register because
7852 * of the TI925 behaviour where writes to another register can
7853 * cause the MIDR value to change.
7855 * Unimplemented registers in the c15 0 0 0 space default to
7856 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7857 * and friends override accordingly.
7860 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7861 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7862 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7863 .readfn
= midr_read
,
7864 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7865 .type
= ARM_CP_OVERRIDE
},
7866 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7868 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7869 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7871 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
7872 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7874 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
7875 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7877 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
7878 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7880 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
7881 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7883 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
7884 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7885 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
7886 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
7887 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7888 .readfn
= midr_read
},
7889 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7890 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7891 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7892 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7893 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7894 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
7895 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7896 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7897 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
7899 .accessfn
= access_aa64_tid1
,
7900 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
7902 ARMCPRegInfo id_cp_reginfo
[] = {
7903 /* These are common to v8 and pre-v8 */
7905 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
7906 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
7907 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7908 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
7909 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
7910 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
7911 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
7912 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7914 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
7916 .accessfn
= access_aa32_tid1
,
7917 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7919 /* TLBTR is specific to VMSA */
7920 ARMCPRegInfo id_tlbtr_reginfo
= {
7922 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
7924 .accessfn
= access_aa32_tid1
,
7925 .type
= ARM_CP_CONST
, .resetvalue
= 0,
7927 /* MPUIR is specific to PMSA V6+ */
7928 ARMCPRegInfo id_mpuir_reginfo
= {
7930 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7931 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7932 .resetvalue
= cpu
->pmsav7_dregion
<< 8
7934 static const ARMCPRegInfo crn0_wi_reginfo
= {
7935 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
7936 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
7937 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
7939 #ifdef CONFIG_USER_ONLY
7940 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
7941 { .name
= "MIDR_EL1",
7942 .exported_bits
= 0x00000000ffffffff },
7943 { .name
= "REVIDR_EL1" },
7945 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
7947 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
7948 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7950 /* Register the blanket "writes ignored" value first to cover the
7951 * whole space. Then update the specific ID registers to allow write
7952 * access, so that they ignore writes rather than causing them to
7955 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
7956 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
7957 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
7959 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
7960 id_cp_reginfo
[i
].access
= PL1_RW
;
7962 id_mpuir_reginfo
.access
= PL1_RW
;
7963 id_tlbtr_reginfo
.access
= PL1_RW
;
7965 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7966 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
7968 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
7970 define_arm_cp_regs(cpu
, id_cp_reginfo
);
7971 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
7972 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
7973 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7974 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
7978 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
7979 ARMCPRegInfo mpidr_cp_reginfo
[] = {
7980 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7981 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
7982 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
7984 #ifdef CONFIG_USER_ONLY
7985 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
7986 { .name
= "MPIDR_EL1",
7987 .fixed_bits
= 0x0000000080000000 },
7989 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
7991 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
7994 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
7995 ARMCPRegInfo auxcr_reginfo
[] = {
7996 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
7997 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
7998 .access
= PL1_RW
, .accessfn
= access_tacr
,
7999 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8000 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8001 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8002 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8004 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8005 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8006 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8009 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8010 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8011 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8015 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8017 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8018 * There are two flavours:
8019 * (1) older 32-bit only cores have a simple 32-bit CBAR
8020 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8021 * 32-bit register visible to AArch32 at a different encoding
8022 * to the "flavour 1" register and with the bits rearranged to
8023 * be able to squash a 64-bit address into the 32-bit view.
8024 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8025 * in future if we support AArch32-only configs of some of the
8026 * AArch64 cores we might need to add a specific feature flag
8027 * to indicate cores with "flavour 2" CBAR.
8029 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8030 /* 32 bit view is [31:18] 0...0 [43:32]. */
8031 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8032 | extract64(cpu
->reset_cbar
, 32, 12);
8033 ARMCPRegInfo cbar_reginfo
[] = {
8035 .type
= ARM_CP_CONST
,
8036 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8037 .access
= PL1_R
, .resetvalue
= cbar32
},
8038 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8039 .type
= ARM_CP_CONST
,
8040 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8041 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8043 /* We don't implement a r/w 64 bit CBAR currently */
8044 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8045 define_arm_cp_regs(cpu
, cbar_reginfo
);
8047 ARMCPRegInfo cbar
= {
8049 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8050 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8051 .fieldoffset
= offsetof(CPUARMState
,
8052 cp15
.c15_config_base_address
)
8054 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8055 cbar
.access
= PL1_R
;
8056 cbar
.fieldoffset
= 0;
8057 cbar
.type
= ARM_CP_CONST
;
8059 define_one_arm_cp_reg(cpu
, &cbar
);
8063 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8064 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8065 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8066 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8067 .access
= PL1_RW
, .writefn
= vbar_write
,
8068 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8069 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8072 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8075 /* Generic registers whose values depend on the implementation */
8077 ARMCPRegInfo sctlr
= {
8078 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8079 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8080 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8081 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8082 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8083 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8084 .raw_writefn
= raw_write
,
8086 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8087 /* Normally we would always end the TB on an SCTLR write, but Linux
8088 * arch/arm/mach-pxa/sleep.S expects two instructions following
8089 * an MMU enable to execute from cache. Imitate this behaviour.
8091 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8093 define_one_arm_cp_reg(cpu
, &sctlr
);
8096 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8097 define_arm_cp_regs(cpu
, lor_reginfo
);
8099 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8100 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8102 #ifndef CONFIG_USER_ONLY
8103 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8104 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8106 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8107 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8110 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8111 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8114 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8115 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8117 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8118 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8120 if (cpu_isar_feature(any_ras
, cpu
)) {
8121 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8124 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8125 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8126 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8128 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8129 define_arm_cp_regs(cpu
, vhe_reginfo
);
8132 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8133 define_arm_cp_regs(cpu
, zcr_reginfo
);
8136 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
8137 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
8140 #ifdef TARGET_AARCH64
8141 if (cpu_isar_feature(aa64_sme
, cpu
)) {
8142 define_arm_cp_regs(cpu
, sme_reginfo
);
8144 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8145 define_arm_cp_regs(cpu
, pauth_reginfo
);
8147 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8148 define_arm_cp_regs(cpu
, rndr_reginfo
);
8150 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8151 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8153 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8154 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8156 #ifndef CONFIG_USER_ONLY
8157 /* Data Cache clean instructions up to PoP */
8158 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8159 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8161 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8162 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8165 #endif /*CONFIG_USER_ONLY*/
8168 * If full MTE is enabled, add all of the system registers.
8169 * If only "instructions available at EL0" are enabled,
8170 * then define only a RAZ/WI version of PSTATE.TCO.
8172 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8173 define_arm_cp_regs(cpu
, mte_reginfo
);
8174 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8175 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8176 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8177 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8180 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
8181 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
8185 if (cpu_isar_feature(any_predinv
, cpu
)) {
8186 define_arm_cp_regs(cpu
, predinv_reginfo
);
8189 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8190 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8193 #ifndef CONFIG_USER_ONLY
8195 * Register redirections and aliases must be done last,
8196 * after the registers from the other extensions have been defined.
8198 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8199 define_arm_vh_e2h_redirects_aliases(cpu
);
8204 /* Sort alphabetically by type name, except for "any". */
8205 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8207 ObjectClass
*class_a
= (ObjectClass
*)a
;
8208 ObjectClass
*class_b
= (ObjectClass
*)b
;
8209 const char *name_a
, *name_b
;
8211 name_a
= object_class_get_name(class_a
);
8212 name_b
= object_class_get_name(class_b
);
8213 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8215 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8218 return strcmp(name_a
, name_b
);
8222 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8224 ObjectClass
*oc
= data
;
8225 const char *typename
;
8228 typename
= object_class_get_name(oc
);
8229 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8230 qemu_printf(" %s\n", name
);
8234 void arm_cpu_list(void)
8238 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8239 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8240 qemu_printf("Available CPUs:\n");
8241 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8245 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8247 ObjectClass
*oc
= data
;
8248 CpuDefinitionInfoList
**cpu_list
= user_data
;
8249 CpuDefinitionInfo
*info
;
8250 const char *typename
;
8252 typename
= object_class_get_name(oc
);
8253 info
= g_malloc0(sizeof(*info
));
8254 info
->name
= g_strndup(typename
,
8255 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8256 info
->q_typename
= g_strdup(typename
);
8258 QAPI_LIST_PREPEND(*cpu_list
, info
);
8261 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8263 CpuDefinitionInfoList
*cpu_list
= NULL
;
8266 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8267 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8274 * Private utility function for define_one_arm_cp_reg_with_opaque():
8275 * add a single reginfo struct to the hash table.
8277 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8278 void *opaque
, CPState state
,
8279 CPSecureState secstate
,
8280 int crm
, int opc1
, int opc2
,
8283 CPUARMState
*env
= &cpu
->env
;
8286 bool is64
= r
->type
& ARM_CP_64BIT
;
8287 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
8293 case ARM_CP_STATE_AA32
:
8294 /* We assume it is a cp15 register if the .cp field is left unset. */
8295 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
8298 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
8300 case ARM_CP_STATE_AA64
:
8302 * To allow abbreviation of ARMCPRegInfo definitions, we treat
8303 * cp == 0 as equivalent to the value for "standard guest-visible
8304 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
8305 * in their AArch64 view (the .cp value may be non-zero for the
8306 * benefit of the AArch32 view).
8308 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8309 cp
= CP_REG_ARM64_SYSREG_CP
;
8311 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
8314 g_assert_not_reached();
8317 /* Overriding of an existing definition must be explicitly requested. */
8318 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8319 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
8321 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
8326 * Eliminate registers that are not present because the EL is missing.
8327 * Doing this here makes it easier to put all registers for a given
8328 * feature into the same ARMCPRegInfo array and define them all at once.
8331 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8333 * An EL2 register without EL2 but with EL3 is (usually) RES0.
8334 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
8336 int min_el
= ctz32(r
->access
) / 2;
8337 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
8338 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
8341 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
8344 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
8346 if ((r
->access
& max_el
) == 0) {
8351 /* Combine cpreg and name into one allocation. */
8352 name_len
= strlen(name
) + 1;
8353 r2
= g_malloc(sizeof(*r2
) + name_len
);
8355 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
8358 * Update fields to match the instantiation, overwiting wildcards
8359 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
8366 r2
->secure
= secstate
;
8368 r2
->opaque
= opaque
;
8372 /* This should not have been a very special register to begin. */
8373 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
8374 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
8376 * Set the special function to CONST, retaining the other flags.
8377 * This is important for e.g. ARM_CP_SVE so that we still
8378 * take the SVE trap if CPTR_EL3.EZ == 0.
8380 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
8382 * Usually, these registers become RES0, but there are a few
8383 * special cases like VPIDR_EL2 which have a constant non-zero
8384 * value with writes ignored.
8386 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
8390 * ARM_CP_CONST has precedence, so removing the callbacks and
8391 * offsets are not strictly necessary, but it is potentially
8392 * less confusing to debug later.
8396 r2
->raw_readfn
= NULL
;
8397 r2
->raw_writefn
= NULL
;
8399 r2
->fieldoffset
= 0;
8400 r2
->bank_fieldoffsets
[0] = 0;
8401 r2
->bank_fieldoffsets
[1] = 0;
8403 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
8407 * Register is banked (using both entries in array).
8408 * Overwriting fieldoffset as the array is only used to define
8409 * banked registers but later only fieldoffset is used.
8411 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8413 if (state
== ARM_CP_STATE_AA32
) {
8416 * If the register is banked then we don't need to migrate or
8417 * reset the 32-bit instance in certain cases:
8419 * 1) If the register has both 32-bit and 64-bit instances
8420 * then we can count on the 64-bit instance taking care
8421 * of the non-secure bank.
8422 * 2) If ARMv8 is enabled then we can count on a 64-bit
8423 * version taking care of the secure bank. This requires
8424 * that separate 32 and 64-bit definitions are provided.
8426 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8427 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
8428 r2
->type
|= ARM_CP_ALIAS
;
8430 } else if ((secstate
!= r
->secure
) && !ns
) {
8432 * The register is not banked so we only want to allow
8433 * migration of the non-secure instance.
8435 r2
->type
|= ARM_CP_ALIAS
;
8438 if (HOST_BIG_ENDIAN
&&
8439 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
8440 r2
->fieldoffset
+= sizeof(uint32_t);
8446 * By convention, for wildcarded registers only the first
8447 * entry is used for migration; the others are marked as
8448 * ALIAS so we don't try to transfer the register
8449 * multiple times. Special registers (ie NOP/WFI) are
8450 * never migratable and not even raw-accessible.
8452 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
8453 r2
->type
|= ARM_CP_NO_RAW
;
8455 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8456 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8457 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8458 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8462 * Check that raw accesses are either forbidden or handled. Note that
8463 * we can't assert this earlier because the setup of fieldoffset for
8464 * banked registers has to be done first.
8466 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8467 assert(!raw_accessors_invalid(r2
));
8470 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
8474 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8475 const ARMCPRegInfo
*r
, void *opaque
)
8477 /* Define implementations of coprocessor registers.
8478 * We store these in a hashtable because typically
8479 * there are less than 150 registers in a space which
8480 * is 16*16*16*8*8 = 262144 in size.
8481 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8482 * If a register is defined twice then the second definition is
8483 * used, so this can be used to define some generic registers and
8484 * then override them with implementation specific variations.
8485 * At least one of the original and the second definition should
8486 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8487 * against accidental use.
8489 * The state field defines whether the register is to be
8490 * visible in the AArch32 or AArch64 execution state. If the
8491 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8492 * reginfo structure for the AArch32 view, which sees the lower
8493 * 32 bits of the 64 bit register.
8495 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8496 * be wildcarded. AArch64 registers are always considered to be 64
8497 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8498 * the register, if any.
8500 int crm
, opc1
, opc2
;
8501 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8502 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8503 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8504 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8505 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8506 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8509 /* 64 bit registers have only CRm and Opc1 fields */
8510 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8511 /* op0 only exists in the AArch64 encodings */
8512 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8513 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8514 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8516 * This API is only for Arm's system coprocessors (14 and 15) or
8517 * (M-profile or v7A-and-earlier only) for implementation defined
8518 * coprocessors in the range 0..7. Our decode assumes this, since
8519 * 8..13 can be used for other insns including VFP and Neon. See
8520 * valid_cp() in translate.c. Assert here that we haven't tried
8521 * to use an invalid coprocessor number.
8524 case ARM_CP_STATE_BOTH
:
8525 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8530 case ARM_CP_STATE_AA32
:
8531 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8532 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8533 assert(r
->cp
>= 14 && r
->cp
<= 15);
8535 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8538 case ARM_CP_STATE_AA64
:
8539 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8542 g_assert_not_reached();
8544 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8545 * encodes a minimum access level for the register. We roll this
8546 * runtime check into our general permission check code, so check
8547 * here that the reginfo's specified permissions are strict enough
8548 * to encompass the generic architectural permission check.
8550 if (r
->state
!= ARM_CP_STATE_AA32
) {
8551 CPAccessRights mask
;
8554 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8555 mask
= PL0U_R
| PL1_RW
;
8575 /* min_EL EL1, secure mode only (we don't check the latter) */
8579 /* broken reginfo with out-of-range opc1 */
8580 g_assert_not_reached();
8582 /* assert our permissions are not too lax (stricter is fine) */
8583 assert((r
->access
& ~mask
) == 0);
8586 /* Check that the register definition has enough info to handle
8587 * reads and writes if they are permitted.
8589 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
8590 if (r
->access
& PL3_R
) {
8591 assert((r
->fieldoffset
||
8592 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8595 if (r
->access
& PL3_W
) {
8596 assert((r
->fieldoffset
||
8597 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8602 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8603 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8604 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8605 for (state
= ARM_CP_STATE_AA32
;
8606 state
<= ARM_CP_STATE_AA64
; state
++) {
8607 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8610 if (state
== ARM_CP_STATE_AA32
) {
8611 /* Under AArch32 CP registers can be common
8612 * (same for secure and non-secure world) or banked.
8616 switch (r
->secure
) {
8617 case ARM_CP_SECSTATE_S
:
8618 case ARM_CP_SECSTATE_NS
:
8619 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8620 r
->secure
, crm
, opc1
, opc2
,
8623 case ARM_CP_SECSTATE_BOTH
:
8624 name
= g_strdup_printf("%s_S", r
->name
);
8625 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8627 crm
, opc1
, opc2
, name
);
8629 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8631 crm
, opc1
, opc2
, r
->name
);
8634 g_assert_not_reached();
8637 /* AArch64 registers get mapped to non-secure instance
8639 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8641 crm
, opc1
, opc2
, r
->name
);
8649 /* Define a whole list of registers */
8650 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
8651 void *opaque
, size_t len
)
8654 for (i
= 0; i
< len
; ++i
) {
8655 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
8660 * Modify ARMCPRegInfo for access from userspace.
8662 * This is a data driven modification directed by
8663 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8664 * user-space cannot alter any values and dynamic values pertaining to
8665 * execution state are hidden from user space view anyway.
8667 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
8668 const ARMCPRegUserSpaceInfo
*mods
,
8671 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
8672 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
8673 GPatternSpec
*pat
= NULL
;
8676 pat
= g_pattern_spec_new(m
->name
);
8678 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
8679 ARMCPRegInfo
*r
= regs
+ ri
;
8681 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8682 r
->type
= ARM_CP_CONST
;
8686 } else if (strcmp(r
->name
, m
->name
) == 0) {
8687 r
->type
= ARM_CP_CONST
;
8689 r
->resetvalue
&= m
->exported_bits
;
8690 r
->resetvalue
|= m
->fixed_bits
;
8695 g_pattern_spec_free(pat
);
8700 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8702 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
8705 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8708 /* Helper coprocessor write function for write-ignore registers */
8711 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8713 /* Helper coprocessor write function for read-as-zero registers */
8717 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8719 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8722 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8724 /* Return true if it is not valid for us to switch to
8725 * this CPU mode (ie all the UNPREDICTABLE cases in
8726 * the ARM ARM CPSRWriteByInstr pseudocode).
8729 /* Changes to or from Hyp via MSR and CPS are illegal. */
8730 if (write_type
== CPSRWriteByInstr
&&
8731 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8732 mode
== ARM_CPU_MODE_HYP
)) {
8737 case ARM_CPU_MODE_USR
:
8739 case ARM_CPU_MODE_SYS
:
8740 case ARM_CPU_MODE_SVC
:
8741 case ARM_CPU_MODE_ABT
:
8742 case ARM_CPU_MODE_UND
:
8743 case ARM_CPU_MODE_IRQ
:
8744 case ARM_CPU_MODE_FIQ
:
8745 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8746 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8748 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8749 * and CPS are treated as illegal mode changes.
8751 if (write_type
== CPSRWriteByInstr
&&
8752 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8753 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8757 case ARM_CPU_MODE_HYP
:
8758 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
8759 case ARM_CPU_MODE_MON
:
8760 return arm_current_el(env
) < 3;
8766 uint32_t cpsr_read(CPUARMState
*env
)
8769 ZF
= (env
->ZF
== 0);
8770 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8771 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8772 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8773 | ((env
->condexec_bits
& 0xfc) << 8)
8774 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8777 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8778 CPSRWriteType write_type
)
8780 uint32_t changed_daif
;
8781 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
8782 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
8784 if (mask
& CPSR_NZCV
) {
8785 env
->ZF
= (~val
) & CPSR_Z
;
8787 env
->CF
= (val
>> 29) & 1;
8788 env
->VF
= (val
<< 3) & 0x80000000;
8791 env
->QF
= ((val
& CPSR_Q
) != 0);
8793 env
->thumb
= ((val
& CPSR_T
) != 0);
8794 if (mask
& CPSR_IT_0_1
) {
8795 env
->condexec_bits
&= ~3;
8796 env
->condexec_bits
|= (val
>> 25) & 3;
8798 if (mask
& CPSR_IT_2_7
) {
8799 env
->condexec_bits
&= 3;
8800 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8802 if (mask
& CPSR_GE
) {
8803 env
->GE
= (val
>> 16) & 0xf;
8806 /* In a V7 implementation that includes the security extensions but does
8807 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8808 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8809 * bits respectively.
8811 * In a V8 implementation, it is permitted for privileged software to
8812 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8814 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8815 arm_feature(env
, ARM_FEATURE_EL3
) &&
8816 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8817 !arm_is_secure(env
)) {
8819 changed_daif
= (env
->daif
^ val
) & mask
;
8821 if (changed_daif
& CPSR_A
) {
8822 /* Check to see if we are allowed to change the masking of async
8823 * abort exceptions from a non-secure state.
8825 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8826 qemu_log_mask(LOG_GUEST_ERROR
,
8827 "Ignoring attempt to switch CPSR_A flag from "
8828 "non-secure world with SCR.AW bit clear\n");
8833 if (changed_daif
& CPSR_F
) {
8834 /* Check to see if we are allowed to change the masking of FIQ
8835 * exceptions from a non-secure state.
8837 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8838 qemu_log_mask(LOG_GUEST_ERROR
,
8839 "Ignoring attempt to switch CPSR_F flag from "
8840 "non-secure world with SCR.FW bit clear\n");
8844 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8845 * If this bit is set software is not allowed to mask
8846 * FIQs, but is allowed to set CPSR_F to 0.
8848 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8850 qemu_log_mask(LOG_GUEST_ERROR
,
8851 "Ignoring attempt to enable CPSR_F flag "
8852 "(non-maskable FIQ [NMFI] support enabled)\n");
8858 env
->daif
&= ~(CPSR_AIF
& mask
);
8859 env
->daif
|= val
& CPSR_AIF
& mask
;
8861 if (write_type
!= CPSRWriteRaw
&&
8862 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8863 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8864 /* Note that we can only get here in USR mode if this is a
8865 * gdb stub write; for this case we follow the architectural
8866 * behaviour for guest writes in USR mode of ignoring an attempt
8867 * to switch mode. (Those are caught by translate.c for writes
8868 * triggered by guest instructions.)
8871 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
8872 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8873 * v7, and has defined behaviour in v8:
8874 * + leave CPSR.M untouched
8875 * + allow changes to the other CPSR fields
8877 * For user changes via the GDB stub, we don't set PSTATE.IL,
8878 * as this would be unnecessarily harsh for a user error.
8881 if (write_type
!= CPSRWriteByGDBStub
&&
8882 arm_feature(env
, ARM_FEATURE_V8
)) {
8886 qemu_log_mask(LOG_GUEST_ERROR
,
8887 "Illegal AArch32 mode switch attempt from %s to %s\n",
8888 aarch32_mode_name(env
->uncached_cpsr
),
8889 aarch32_mode_name(val
));
8891 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
8892 write_type
== CPSRWriteExceptionReturn
?
8893 "Exception return from AArch32" :
8894 "AArch32 mode switch from",
8895 aarch32_mode_name(env
->uncached_cpsr
),
8896 aarch32_mode_name(val
), env
->regs
[15]);
8897 switch_mode(env
, val
& CPSR_M
);
8900 mask
&= ~CACHED_CPSR_BITS
;
8901 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
8902 if (rebuild_hflags
) {
8903 arm_rebuild_hflags(env
);
8907 /* Sign/zero extend */
8908 uint32_t HELPER(sxtb16
)(uint32_t x
)
8911 res
= (uint16_t)(int8_t)x
;
8912 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
8916 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
8919 * Take a division-by-zero exception if necessary; otherwise return
8920 * to get the usual non-trapping division behaviour (result of 0)
8922 if (arm_feature(env
, ARM_FEATURE_M
)
8923 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
8924 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
8928 uint32_t HELPER(uxtb16
)(uint32_t x
)
8931 res
= (uint16_t)(uint8_t)x
;
8932 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
8936 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
8939 handle_possible_div0_trap(env
, GETPC());
8942 if (num
== INT_MIN
&& den
== -1) {
8948 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
8951 handle_possible_div0_trap(env
, GETPC());
8957 uint32_t HELPER(rbit
)(uint32_t x
)
8962 #ifdef CONFIG_USER_ONLY
8964 static void switch_mode(CPUARMState
*env
, int mode
)
8966 ARMCPU
*cpu
= env_archcpu(env
);
8968 if (mode
!= ARM_CPU_MODE_USR
) {
8969 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
8973 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8974 uint32_t cur_el
, bool secure
)
8979 void aarch64_sync_64_to_32(CPUARMState
*env
)
8981 g_assert_not_reached();
8986 static void switch_mode(CPUARMState
*env
, int mode
)
8991 old_mode
= env
->uncached_cpsr
& CPSR_M
;
8992 if (mode
== old_mode
)
8995 if (old_mode
== ARM_CPU_MODE_FIQ
) {
8996 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
8997 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
8998 } else if (mode
== ARM_CPU_MODE_FIQ
) {
8999 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9000 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9003 i
= bank_number(old_mode
);
9004 env
->banked_r13
[i
] = env
->regs
[13];
9005 env
->banked_spsr
[i
] = env
->spsr
;
9007 i
= bank_number(mode
);
9008 env
->regs
[13] = env
->banked_r13
[i
];
9009 env
->spsr
= env
->banked_spsr
[i
];
9011 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9012 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9015 /* Physical Interrupt Target EL Lookup Table
9017 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9019 * The below multi-dimensional table is used for looking up the target
9020 * exception level given numerous condition criteria. Specifically, the
9021 * target EL is based on SCR and HCR routing controls as well as the
9022 * currently executing EL and secure state.
9025 * target_el_table[2][2][2][2][2][4]
9026 * | | | | | +--- Current EL
9027 * | | | | +------ Non-secure(0)/Secure(1)
9028 * | | | +--------- HCR mask override
9029 * | | +------------ SCR exec state control
9030 * | +--------------- SCR mask override
9031 * +------------------ 32-bit(0)/64-bit(1) EL3
9033 * The table values are as such:
9037 * The ARM ARM target EL table includes entries indicating that an "exception
9038 * is not taken". The two cases where this is applicable are:
9039 * 1) An exception is taken from EL3 but the SCR does not have the exception
9041 * 2) An exception is taken from EL2 but the HCR does not have the exception
9043 * In these two cases, the below table contain a target of EL1. This value is
9044 * returned as it is expected that the consumer of the table data will check
9045 * for "target EL >= current EL" to ensure the exception is not taken.
9049 * BIT IRQ IMO Non-secure Secure
9050 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9052 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9053 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9054 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9055 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9056 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9057 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9058 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9059 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9060 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9061 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9062 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9063 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9064 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9065 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9066 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9067 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9068 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9072 * Determine the target EL for physical exceptions
9074 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9075 uint32_t cur_el
, bool secure
)
9077 CPUARMState
*env
= cs
->env_ptr
;
9082 /* Is the highest EL AArch64? */
9083 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9086 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9087 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9089 /* Either EL2 is the highest EL (and so the EL2 register width
9090 * is given by is64); or there is no EL2 or EL3, in which case
9091 * the value of 'rw' does not affect the table lookup anyway.
9096 hcr_el2
= arm_hcr_el2_eff(env
);
9099 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9100 hcr
= hcr_el2
& HCR_IMO
;
9103 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9104 hcr
= hcr_el2
& HCR_FMO
;
9107 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9108 hcr
= hcr_el2
& HCR_AMO
;
9113 * For these purposes, TGE and AMO/IMO/FMO both force the
9114 * interrupt to EL2. Fold TGE into the bit extracted above.
9116 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9118 /* Perform a table-lookup for the target EL given the current state */
9119 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9121 assert(target_el
> 0);
9126 void arm_log_exception(CPUState
*cs
)
9128 int idx
= cs
->exception_index
;
9130 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9131 const char *exc
= NULL
;
9132 static const char * const excnames
[] = {
9133 [EXCP_UDEF
] = "Undefined Instruction",
9135 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9136 [EXCP_DATA_ABORT
] = "Data Abort",
9139 [EXCP_BKPT
] = "Breakpoint",
9140 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9141 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9142 [EXCP_HVC
] = "Hypervisor Call",
9143 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9144 [EXCP_SMC
] = "Secure Monitor Call",
9145 [EXCP_VIRQ
] = "Virtual IRQ",
9146 [EXCP_VFIQ
] = "Virtual FIQ",
9147 [EXCP_SEMIHOST
] = "Semihosting call",
9148 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9149 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9150 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9151 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9152 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9153 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9154 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
9155 [EXCP_VSERR
] = "Virtual SERR",
9158 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9159 exc
= excnames
[idx
];
9164 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
9165 idx
, exc
, cs
->cpu_index
);
9170 * Function used to synchronize QEMU's AArch64 register set with AArch32
9171 * register set. This is necessary when switching between AArch32 and AArch64
9174 void aarch64_sync_32_to_64(CPUARMState
*env
)
9177 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9179 /* We can blanket copy R[0:7] to X[0:7] */
9180 for (i
= 0; i
< 8; i
++) {
9181 env
->xregs
[i
] = env
->regs
[i
];
9185 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9186 * Otherwise, they come from the banked user regs.
9188 if (mode
== ARM_CPU_MODE_FIQ
) {
9189 for (i
= 8; i
< 13; i
++) {
9190 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9193 for (i
= 8; i
< 13; i
++) {
9194 env
->xregs
[i
] = env
->regs
[i
];
9199 * Registers x13-x23 are the various mode SP and FP registers. Registers
9200 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9201 * from the mode banked register.
9203 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9204 env
->xregs
[13] = env
->regs
[13];
9205 env
->xregs
[14] = env
->regs
[14];
9207 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9208 /* HYP is an exception in that it is copied from r14 */
9209 if (mode
== ARM_CPU_MODE_HYP
) {
9210 env
->xregs
[14] = env
->regs
[14];
9212 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9216 if (mode
== ARM_CPU_MODE_HYP
) {
9217 env
->xregs
[15] = env
->regs
[13];
9219 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9222 if (mode
== ARM_CPU_MODE_IRQ
) {
9223 env
->xregs
[16] = env
->regs
[14];
9224 env
->xregs
[17] = env
->regs
[13];
9226 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9227 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9230 if (mode
== ARM_CPU_MODE_SVC
) {
9231 env
->xregs
[18] = env
->regs
[14];
9232 env
->xregs
[19] = env
->regs
[13];
9234 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9235 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9238 if (mode
== ARM_CPU_MODE_ABT
) {
9239 env
->xregs
[20] = env
->regs
[14];
9240 env
->xregs
[21] = env
->regs
[13];
9242 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9243 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9246 if (mode
== ARM_CPU_MODE_UND
) {
9247 env
->xregs
[22] = env
->regs
[14];
9248 env
->xregs
[23] = env
->regs
[13];
9250 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9251 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9255 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9256 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9257 * FIQ bank for r8-r14.
9259 if (mode
== ARM_CPU_MODE_FIQ
) {
9260 for (i
= 24; i
< 31; i
++) {
9261 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9264 for (i
= 24; i
< 29; i
++) {
9265 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9267 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9268 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9271 env
->pc
= env
->regs
[15];
9275 * Function used to synchronize QEMU's AArch32 register set with AArch64
9276 * register set. This is necessary when switching between AArch32 and AArch64
9279 void aarch64_sync_64_to_32(CPUARMState
*env
)
9282 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9284 /* We can blanket copy X[0:7] to R[0:7] */
9285 for (i
= 0; i
< 8; i
++) {
9286 env
->regs
[i
] = env
->xregs
[i
];
9290 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9291 * Otherwise, we copy x8-x12 into the banked user regs.
9293 if (mode
== ARM_CPU_MODE_FIQ
) {
9294 for (i
= 8; i
< 13; i
++) {
9295 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9298 for (i
= 8; i
< 13; i
++) {
9299 env
->regs
[i
] = env
->xregs
[i
];
9304 * Registers r13 & r14 depend on the current mode.
9305 * If we are in a given mode, we copy the corresponding x registers to r13
9306 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9309 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9310 env
->regs
[13] = env
->xregs
[13];
9311 env
->regs
[14] = env
->xregs
[14];
9313 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9316 * HYP is an exception in that it does not have its own banked r14 but
9317 * shares the USR r14
9319 if (mode
== ARM_CPU_MODE_HYP
) {
9320 env
->regs
[14] = env
->xregs
[14];
9322 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9326 if (mode
== ARM_CPU_MODE_HYP
) {
9327 env
->regs
[13] = env
->xregs
[15];
9329 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9332 if (mode
== ARM_CPU_MODE_IRQ
) {
9333 env
->regs
[14] = env
->xregs
[16];
9334 env
->regs
[13] = env
->xregs
[17];
9336 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9337 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9340 if (mode
== ARM_CPU_MODE_SVC
) {
9341 env
->regs
[14] = env
->xregs
[18];
9342 env
->regs
[13] = env
->xregs
[19];
9344 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9345 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9348 if (mode
== ARM_CPU_MODE_ABT
) {
9349 env
->regs
[14] = env
->xregs
[20];
9350 env
->regs
[13] = env
->xregs
[21];
9352 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9353 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9356 if (mode
== ARM_CPU_MODE_UND
) {
9357 env
->regs
[14] = env
->xregs
[22];
9358 env
->regs
[13] = env
->xregs
[23];
9360 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9361 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9364 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9365 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9366 * FIQ bank for r8-r14.
9368 if (mode
== ARM_CPU_MODE_FIQ
) {
9369 for (i
= 24; i
< 31; i
++) {
9370 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9373 for (i
= 24; i
< 29; i
++) {
9374 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9376 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9377 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9380 env
->regs
[15] = env
->pc
;
9383 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9384 uint32_t mask
, uint32_t offset
,
9389 /* Change the CPU state so as to actually take the exception. */
9390 switch_mode(env
, new_mode
);
9393 * For exceptions taken to AArch32 we must clear the SS bit in both
9394 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9396 env
->pstate
&= ~PSTATE_SS
;
9397 env
->spsr
= cpsr_read(env
);
9398 /* Clear IT bits. */
9399 env
->condexec_bits
= 0;
9400 /* Switch to the new mode, and to the correct instruction set. */
9401 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9403 /* This must be after mode switching. */
9404 new_el
= arm_current_el(env
);
9406 /* Set new mode endianness */
9407 env
->uncached_cpsr
&= ~CPSR_E
;
9408 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9409 env
->uncached_cpsr
|= CPSR_E
;
9411 /* J and IL must always be cleared for exception entry */
9412 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9415 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9416 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9417 env
->uncached_cpsr
|= CPSR_SSBS
;
9419 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9423 if (new_mode
== ARM_CPU_MODE_HYP
) {
9424 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9425 env
->elr_el
[2] = env
->regs
[15];
9427 /* CPSR.PAN is normally preserved preserved unless... */
9428 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9431 if (!arm_is_secure_below_el3(env
)) {
9432 /* ... the target is EL3, from non-secure state. */
9433 env
->uncached_cpsr
&= ~CPSR_PAN
;
9436 /* ... the target is EL3, from secure state ... */
9439 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9440 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9441 env
->uncached_cpsr
|= CPSR_PAN
;
9447 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9448 * and we should just guard the thumb mode on V4
9450 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9452 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9454 env
->regs
[14] = env
->regs
[15] + offset
;
9456 env
->regs
[15] = newpc
;
9457 arm_rebuild_hflags(env
);
9460 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9463 * Handle exception entry to Hyp mode; this is sufficiently
9464 * different to entry to other AArch32 modes that we handle it
9467 * The vector table entry used is always the 0x14 Hyp mode entry point,
9468 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
9469 * The offset applied to the preferred return address is always zero
9470 * (see DDI0487C.a section G1.12.3).
9471 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9473 uint32_t addr
, mask
;
9474 ARMCPU
*cpu
= ARM_CPU(cs
);
9475 CPUARMState
*env
= &cpu
->env
;
9477 switch (cs
->exception_index
) {
9485 /* Fall through to prefetch abort. */
9486 case EXCP_PREFETCH_ABORT
:
9487 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9488 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9489 (uint32_t)env
->exception
.vaddress
);
9492 case EXCP_DATA_ABORT
:
9493 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9494 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9495 (uint32_t)env
->exception
.vaddress
);
9511 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9514 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9515 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9517 * QEMU syndrome values are v8-style. v7 has the IL bit
9518 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9519 * If this is a v7 CPU, squash the IL bit in those cases.
9521 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9522 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9523 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9524 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9525 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9528 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9531 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9536 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9539 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9542 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9546 addr
+= env
->cp15
.hvbar
;
9548 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9551 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9553 ARMCPU
*cpu
= ARM_CPU(cs
);
9554 CPUARMState
*env
= &cpu
->env
;
9561 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9562 switch (syn_get_ec(env
->exception
.syndrome
)) {
9564 case EC_BREAKPOINT_SAME_EL
:
9568 case EC_WATCHPOINT_SAME_EL
:
9574 case EC_VECTORCATCH
:
9583 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9586 if (env
->exception
.target_el
== 2) {
9587 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9591 switch (cs
->exception_index
) {
9593 new_mode
= ARM_CPU_MODE_UND
;
9602 new_mode
= ARM_CPU_MODE_SVC
;
9605 /* The PC already points to the next instruction. */
9609 /* Fall through to prefetch abort. */
9610 case EXCP_PREFETCH_ABORT
:
9611 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9612 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9613 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9614 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9615 new_mode
= ARM_CPU_MODE_ABT
;
9617 mask
= CPSR_A
| CPSR_I
;
9620 case EXCP_DATA_ABORT
:
9621 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9622 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9623 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9625 (uint32_t)env
->exception
.vaddress
);
9626 new_mode
= ARM_CPU_MODE_ABT
;
9628 mask
= CPSR_A
| CPSR_I
;
9632 new_mode
= ARM_CPU_MODE_IRQ
;
9634 /* Disable IRQ and imprecise data aborts. */
9635 mask
= CPSR_A
| CPSR_I
;
9637 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9638 /* IRQ routed to monitor mode */
9639 new_mode
= ARM_CPU_MODE_MON
;
9644 new_mode
= ARM_CPU_MODE_FIQ
;
9646 /* Disable FIQ, IRQ and imprecise data aborts. */
9647 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9648 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9649 /* FIQ routed to monitor mode */
9650 new_mode
= ARM_CPU_MODE_MON
;
9655 new_mode
= ARM_CPU_MODE_IRQ
;
9657 /* Disable IRQ and imprecise data aborts. */
9658 mask
= CPSR_A
| CPSR_I
;
9662 new_mode
= ARM_CPU_MODE_FIQ
;
9664 /* Disable FIQ, IRQ and imprecise data aborts. */
9665 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9671 * Note that this is reported as a data abort, but the DFAR
9672 * has an UNKNOWN value. Construct the SError syndrome from
9673 * AET and ExT fields.
9675 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
9677 if (extended_addresses_enabled(env
)) {
9678 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
9680 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
9682 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
9683 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9684 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
9685 env
->exception
.fsr
);
9687 new_mode
= ARM_CPU_MODE_ABT
;
9689 mask
= CPSR_A
| CPSR_I
;
9694 new_mode
= ARM_CPU_MODE_MON
;
9696 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9700 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9701 return; /* Never happens. Keep compiler happy. */
9704 if (new_mode
== ARM_CPU_MODE_MON
) {
9705 addr
+= env
->cp15
.mvbar
;
9706 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9707 /* High vectors. When enabled, base address cannot be remapped. */
9710 /* ARM v7 architectures provide a vector base address register to remap
9711 * the interrupt vector table.
9712 * This register is only followed in non-monitor mode, and is banked.
9713 * Note: only bits 31:5 are valid.
9715 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9718 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9719 env
->cp15
.scr_el3
&= ~SCR_NS
;
9722 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9725 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
9728 * Return the register number of the AArch64 view of the AArch32
9729 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9730 * be that of the AArch32 mode the exception came from.
9732 int mode
= env
->uncached_cpsr
& CPSR_M
;
9734 switch (aarch32_reg
) {
9738 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
9741 case ARM_CPU_MODE_USR
:
9742 case ARM_CPU_MODE_SYS
:
9744 case ARM_CPU_MODE_HYP
:
9746 case ARM_CPU_MODE_IRQ
:
9748 case ARM_CPU_MODE_SVC
:
9750 case ARM_CPU_MODE_ABT
:
9752 case ARM_CPU_MODE_UND
:
9754 case ARM_CPU_MODE_FIQ
:
9757 g_assert_not_reached();
9761 case ARM_CPU_MODE_USR
:
9762 case ARM_CPU_MODE_SYS
:
9763 case ARM_CPU_MODE_HYP
:
9765 case ARM_CPU_MODE_IRQ
:
9767 case ARM_CPU_MODE_SVC
:
9769 case ARM_CPU_MODE_ABT
:
9771 case ARM_CPU_MODE_UND
:
9773 case ARM_CPU_MODE_FIQ
:
9776 g_assert_not_reached();
9781 g_assert_not_reached();
9785 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
9787 uint32_t ret
= cpsr_read(env
);
9789 /* Move DIT to the correct location for SPSR_ELx */
9790 if (ret
& CPSR_DIT
) {
9794 /* Merge PSTATE.SS into SPSR_ELx */
9795 ret
|= env
->pstate
& PSTATE_SS
;
9800 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
9802 /* Return true if this syndrome value is a synchronous external abort */
9803 switch (syn_get_ec(syndrome
)) {
9805 case EC_INSNABORT_SAME_EL
:
9807 case EC_DATAABORT_SAME_EL
:
9808 /* Look at fault status code for all the synchronous ext abort cases */
9809 switch (syndrome
& 0x3f) {
9825 /* Handle exception entry to a target EL which is using AArch64 */
9826 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9828 ARMCPU
*cpu
= ARM_CPU(cs
);
9829 CPUARMState
*env
= &cpu
->env
;
9830 unsigned int new_el
= env
->exception
.target_el
;
9831 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9832 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9833 unsigned int old_mode
;
9834 unsigned int cur_el
= arm_current_el(env
);
9838 * Note that new_el can never be 0. If cur_el is 0, then
9839 * el0_a64 is is_a64(), else el0_a64 is ignored.
9841 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9843 if (cur_el
< new_el
) {
9844 /* Entry vector offset depends on whether the implemented EL
9845 * immediately lower than the target level is using AArch32 or AArch64
9852 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9855 hcr
= arm_hcr_el2_eff(env
);
9856 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9857 is_aa64
= (hcr
& HCR_RW
) != 0;
9862 is_aa64
= is_a64(env
);
9865 g_assert_not_reached();
9873 } else if (pstate_read(env
) & PSTATE_SP
) {
9877 switch (cs
->exception_index
) {
9878 case EXCP_PREFETCH_ABORT
:
9879 case EXCP_DATA_ABORT
:
9881 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
9882 * to be taken to the SError vector entrypoint.
9884 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
9885 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
9888 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9889 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9890 env
->cp15
.far_el
[new_el
]);
9898 switch (syn_get_ec(env
->exception
.syndrome
)) {
9899 case EC_ADVSIMDFPACCESSTRAP
:
9901 * QEMU internal FP/SIMD syndromes from AArch32 include the
9902 * TA and coproc fields which are only exposed if the exception
9903 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9904 * AArch64 format syndrome.
9906 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9912 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
9913 * the raw register field from the insn; when taking this to
9914 * AArch64 we must convert it to the AArch64 view of the register
9915 * number. Notice that we read a 4-bit AArch32 register number and
9916 * write back a 5-bit AArch64 one.
9918 rt
= extract32(env
->exception
.syndrome
, 5, 4);
9919 rt
= aarch64_regnum(env
, rt
);
9920 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9923 case EC_CP15RRTTRAP
:
9924 case EC_CP14RRTTRAP
:
9925 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
9926 rt
= extract32(env
->exception
.syndrome
, 5, 4);
9927 rt
= aarch64_regnum(env
, rt
);
9928 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9930 rt
= extract32(env
->exception
.syndrome
, 10, 4);
9931 rt
= aarch64_regnum(env
, rt
);
9932 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9936 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9948 /* Construct the SError syndrome from IDS and ISS fields. */
9949 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
9950 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9953 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9957 old_mode
= pstate_read(env
);
9958 aarch64_save_sp(env
, arm_current_el(env
));
9959 env
->elr_el
[new_el
] = env
->pc
;
9961 old_mode
= cpsr_read_for_spsr_elx(env
);
9962 env
->elr_el
[new_el
] = env
->regs
[15];
9964 aarch64_sync_32_to_64(env
);
9966 env
->condexec_bits
= 0;
9968 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
9970 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9971 env
->elr_el
[new_el
]);
9973 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9974 /* The value of PSTATE.PAN is normally preserved, except when ... */
9975 new_mode
|= old_mode
& PSTATE_PAN
;
9978 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9979 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
9980 != (HCR_E2H
| HCR_TGE
)) {
9985 /* ... the target is EL1 ... */
9986 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9987 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
9988 new_mode
|= PSTATE_PAN
;
9993 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9994 new_mode
|= PSTATE_TCO
;
9997 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9998 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
9999 new_mode
|= PSTATE_SSBS
;
10001 new_mode
&= ~PSTATE_SSBS
;
10005 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10006 env
->aarch64
= true;
10007 aarch64_restore_sp(env
, new_el
);
10008 helper_rebuild_hflags_a64(env
, new_el
);
10012 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10013 new_el
, env
->pc
, pstate_read(env
));
10017 * Do semihosting call and set the appropriate return value. All the
10018 * permission and validity checks have been done at translate time.
10020 * We only see semihosting exceptions in TCG only as they are not
10021 * trapped to the hypervisor in KVM.
10024 static void handle_semihosting(CPUState
*cs
)
10026 ARMCPU
*cpu
= ARM_CPU(cs
);
10027 CPUARMState
*env
= &cpu
->env
;
10030 qemu_log_mask(CPU_LOG_INT
,
10031 "...handling as semihosting call 0x%" PRIx64
"\n",
10033 do_common_semihosting(cs
);
10036 qemu_log_mask(CPU_LOG_INT
,
10037 "...handling as semihosting call 0x%x\n",
10039 do_common_semihosting(cs
);
10040 env
->regs
[15] += env
->thumb
? 2 : 4;
10045 /* Handle a CPU exception for A and R profile CPUs.
10046 * Do any appropriate logging, handle PSCI calls, and then hand off
10047 * to the AArch64-entry or AArch32-entry function depending on the
10048 * target exception level's register width.
10050 * Note: this is used for both TCG (as the do_interrupt tcg op),
10051 * and KVM to re-inject guest debug exceptions, and to
10052 * inject a Synchronous-External-Abort.
10054 void arm_cpu_do_interrupt(CPUState
*cs
)
10056 ARMCPU
*cpu
= ARM_CPU(cs
);
10057 CPUARMState
*env
= &cpu
->env
;
10058 unsigned int new_el
= env
->exception
.target_el
;
10060 assert(!arm_feature(env
, ARM_FEATURE_M
));
10062 arm_log_exception(cs
);
10063 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10065 if (qemu_loglevel_mask(CPU_LOG_INT
)
10066 && !excp_is_internal(cs
->exception_index
)) {
10067 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10068 syn_get_ec(env
->exception
.syndrome
),
10069 env
->exception
.syndrome
);
10072 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10073 arm_handle_psci_call(cpu
);
10074 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10079 * Semihosting semantics depend on the register width of the code
10080 * that caused the exception, not the target exception level, so
10081 * must be handled here.
10084 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10085 handle_semihosting(cs
);
10090 /* Hooks may change global state so BQL should be held, also the
10091 * BQL needs to be held for any modification of
10092 * cs->interrupt_request.
10094 g_assert(qemu_mutex_iothread_locked());
10096 arm_call_pre_el_change_hook(cpu
);
10098 assert(!excp_is_internal(cs
->exception_index
));
10099 if (arm_el_is_aa64(env
, new_el
)) {
10100 arm_cpu_do_interrupt_aarch64(cs
);
10102 arm_cpu_do_interrupt_aarch32(cs
);
10105 arm_call_el_change_hook(cpu
);
10107 if (!kvm_enabled()) {
10108 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10111 #endif /* !CONFIG_USER_ONLY */
10113 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10115 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10117 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10118 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10121 return env
->cp15
.sctlr_el
[el
];
10124 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10126 if (regime_has_2_ranges(mmu_idx
)) {
10127 return extract64(tcr
, 37, 2);
10128 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10129 return 0; /* VTCR_EL2 */
10131 /* Replicate the single TBI bit so we always have 2 bits. */
10132 return extract32(tcr
, 20, 1) * 3;
10136 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10138 if (regime_has_2_ranges(mmu_idx
)) {
10139 return extract64(tcr
, 51, 2);
10140 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10141 return 0; /* VTCR_EL2 */
10143 /* Replicate the single TBID bit so we always have 2 bits. */
10144 return extract32(tcr
, 29, 1) * 3;
10148 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10150 if (regime_has_2_ranges(mmu_idx
)) {
10151 return extract64(tcr
, 57, 2);
10153 /* Replicate the single TCMA bit so we always have 2 bits. */
10154 return extract32(tcr
, 30, 1) * 3;
10158 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10159 ARMMMUIdx mmu_idx
, bool data
)
10161 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
10162 bool epd
, hpd
, using16k
, using64k
, tsz_oob
, ds
;
10163 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
10164 ARMCPU
*cpu
= env_archcpu(env
);
10166 if (!regime_has_2_ranges(mmu_idx
)) {
10168 tsz
= extract32(tcr
, 0, 6);
10169 using64k
= extract32(tcr
, 14, 1);
10170 using16k
= extract32(tcr
, 15, 1);
10171 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10175 hpd
= extract32(tcr
, 24, 1);
10178 sh
= extract32(tcr
, 12, 2);
10179 ps
= extract32(tcr
, 16, 3);
10180 ds
= extract64(tcr
, 32, 1);
10183 * Bit 55 is always between the two regions, and is canonical for
10184 * determining if address tagging is enabled.
10186 select
= extract64(va
, 55, 1);
10188 tsz
= extract32(tcr
, 0, 6);
10189 epd
= extract32(tcr
, 7, 1);
10190 sh
= extract32(tcr
, 12, 2);
10191 using64k
= extract32(tcr
, 14, 1);
10192 using16k
= extract32(tcr
, 15, 1);
10193 hpd
= extract64(tcr
, 41, 1);
10195 int tg
= extract32(tcr
, 30, 2);
10196 using16k
= tg
== 1;
10197 using64k
= tg
== 3;
10198 tsz
= extract32(tcr
, 16, 6);
10199 epd
= extract32(tcr
, 23, 1);
10200 sh
= extract32(tcr
, 28, 2);
10201 hpd
= extract64(tcr
, 42, 1);
10203 ps
= extract64(tcr
, 32, 3);
10204 ds
= extract64(tcr
, 59, 1);
10207 if (cpu_isar_feature(aa64_st
, cpu
)) {
10208 max_tsz
= 48 - using64k
;
10214 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
10215 * adjust the effective value of DS, as documented.
10219 if (cpu_isar_feature(aa64_lva
, cpu
)) {
10225 case ARMMMUIdx_Stage2
:
10226 case ARMMMUIdx_Stage2_S
:
10228 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
10230 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
10235 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
10237 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
10246 if (tsz
> max_tsz
) {
10249 } else if (tsz
< min_tsz
) {
10256 /* Present TBI as a composite with TBID. */
10257 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10259 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10261 tbi
= (tbi
>> select
) & 1;
10263 return (ARMVAParameters
) {
10271 .using16k
= using16k
,
10272 .using64k
= using64k
,
10273 .tsz_oob
= tsz_oob
,
10278 /* Note that signed overflow is undefined in C. The following routines are
10279 careful to use unsigned types where modulo arithmetic is required.
10280 Failure to do so _will_ break on newer gcc. */
10282 /* Signed saturating arithmetic. */
10284 /* Perform 16-bit signed saturating addition. */
10285 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10290 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10299 /* Perform 8-bit signed saturating addition. */
10300 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10305 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10314 /* Perform 16-bit signed saturating subtraction. */
10315 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10320 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10329 /* Perform 8-bit signed saturating subtraction. */
10330 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10335 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10344 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10345 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10346 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10347 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10350 #include "op_addsub.h"
10352 /* Unsigned saturating arithmetic. */
10353 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10362 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10370 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10379 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10387 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10388 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10389 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10390 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10393 #include "op_addsub.h"
10395 /* Signed modulo arithmetic. */
10396 #define SARITH16(a, b, n, op) do { \
10398 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10399 RESULT(sum, n, 16); \
10401 ge |= 3 << (n * 2); \
10404 #define SARITH8(a, b, n, op) do { \
10406 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10407 RESULT(sum, n, 8); \
10413 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10414 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10415 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10416 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10420 #include "op_addsub.h"
10422 /* Unsigned modulo arithmetic. */
10423 #define ADD16(a, b, n) do { \
10425 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10426 RESULT(sum, n, 16); \
10427 if ((sum >> 16) == 1) \
10428 ge |= 3 << (n * 2); \
10431 #define ADD8(a, b, n) do { \
10433 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10434 RESULT(sum, n, 8); \
10435 if ((sum >> 8) == 1) \
10439 #define SUB16(a, b, n) do { \
10441 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10442 RESULT(sum, n, 16); \
10443 if ((sum >> 16) == 0) \
10444 ge |= 3 << (n * 2); \
10447 #define SUB8(a, b, n) do { \
10449 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10450 RESULT(sum, n, 8); \
10451 if ((sum >> 8) == 0) \
10458 #include "op_addsub.h"
10460 /* Halved signed arithmetic. */
10461 #define ADD16(a, b, n) \
10462 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10463 #define SUB16(a, b, n) \
10464 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10465 #define ADD8(a, b, n) \
10466 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10467 #define SUB8(a, b, n) \
10468 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10471 #include "op_addsub.h"
10473 /* Halved unsigned arithmetic. */
10474 #define ADD16(a, b, n) \
10475 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10476 #define SUB16(a, b, n) \
10477 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10478 #define ADD8(a, b, n) \
10479 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10480 #define SUB8(a, b, n) \
10481 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10484 #include "op_addsub.h"
10486 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10494 /* Unsigned sum of absolute byte differences. */
10495 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10498 sum
= do_usad(a
, b
);
10499 sum
+= do_usad(a
>> 8, b
>> 8);
10500 sum
+= do_usad(a
>> 16, b
>> 16);
10501 sum
+= do_usad(a
>> 24, b
>> 24);
10505 /* For ARMv6 SEL instruction. */
10506 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10518 mask
|= 0xff000000;
10519 return (a
& mask
) | (b
& ~mask
);
10523 * The upper bytes of val (above the number specified by 'bytes') must have
10524 * been zeroed out by the caller.
10526 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10530 stl_le_p(buf
, val
);
10532 /* zlib crc32 converts the accumulator and output to one's complement. */
10533 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10536 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10540 stl_le_p(buf
, val
);
10542 /* Linux crc32c converts the output to one's complement. */
10543 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
10546 /* Return the exception level to which FP-disabled exceptions should
10547 * be taken, or 0 if FP is enabled.
10549 int fp_exception_el(CPUARMState
*env
, int cur_el
)
10551 #ifndef CONFIG_USER_ONLY
10554 /* CPACR and the CPTR registers don't exist before v6, so FP is
10555 * always accessible
10557 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
10561 if (arm_feature(env
, ARM_FEATURE_M
)) {
10562 /* CPACR can cause a NOCP UsageFault taken to current security state */
10563 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
10567 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
10568 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
10569 /* FP insns cause a NOCP UsageFault taken to Secure */
10577 hcr_el2
= arm_hcr_el2_eff(env
);
10579 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
10580 * 0, 2 : trap EL0 and EL1/PL1 accesses
10581 * 1 : trap only EL0 accesses
10582 * 3 : trap no accesses
10583 * This register is ignored if E2H+TGE are both set.
10585 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10586 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
10596 /* Trap from Secure PL0 or PL1 to Secure PL1. */
10597 if (!arm_el_is_aa64(env
, 3)
10598 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
10609 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
10610 * to control non-secure access to the FPU. It doesn't have any
10611 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
10613 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
10614 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
10615 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
10616 /* FP insns act as UNDEF */
10617 return cur_el
== 2 ? 2 : 1;
10622 * CPTR_EL2 is present in v7VE or v8, and changes format
10623 * with HCR_EL2.E2H (regardless of TGE).
10626 if (hcr_el2
& HCR_E2H
) {
10627 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
10629 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
10637 } else if (arm_is_el2_enabled(env
)) {
10638 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
10644 /* CPTR_EL3 : present in v8 */
10645 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
10646 /* Trap all FP ops to EL3 */
10653 /* Return the exception level we're running at if this is our mmu_idx */
10654 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
10656 if (mmu_idx
& ARM_MMU_IDX_M
) {
10657 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
10661 case ARMMMUIdx_E10_0
:
10662 case ARMMMUIdx_E20_0
:
10663 case ARMMMUIdx_SE10_0
:
10664 case ARMMMUIdx_SE20_0
:
10666 case ARMMMUIdx_E10_1
:
10667 case ARMMMUIdx_E10_1_PAN
:
10668 case ARMMMUIdx_SE10_1
:
10669 case ARMMMUIdx_SE10_1_PAN
:
10672 case ARMMMUIdx_E20_2
:
10673 case ARMMMUIdx_E20_2_PAN
:
10674 case ARMMMUIdx_SE2
:
10675 case ARMMMUIdx_SE20_2
:
10676 case ARMMMUIdx_SE20_2_PAN
:
10678 case ARMMMUIdx_SE3
:
10681 g_assert_not_reached();
10686 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
10688 g_assert_not_reached();
10692 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
10697 if (arm_feature(env
, ARM_FEATURE_M
)) {
10698 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
10701 /* See ARM pseudo-function ELIsInHost. */
10704 hcr
= arm_hcr_el2_eff(env
);
10705 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
10706 idx
= ARMMMUIdx_E20_0
;
10708 idx
= ARMMMUIdx_E10_0
;
10712 if (env
->pstate
& PSTATE_PAN
) {
10713 idx
= ARMMMUIdx_E10_1_PAN
;
10715 idx
= ARMMMUIdx_E10_1
;
10719 /* Note that TGE does not apply at EL2. */
10720 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
10721 if (env
->pstate
& PSTATE_PAN
) {
10722 idx
= ARMMMUIdx_E20_2_PAN
;
10724 idx
= ARMMMUIdx_E20_2
;
10727 idx
= ARMMMUIdx_E2
;
10731 return ARMMMUIdx_SE3
;
10733 g_assert_not_reached();
10736 if (arm_is_secure_below_el3(env
)) {
10737 idx
&= ~ARM_MMU_IDX_A_NS
;
10743 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
10745 return arm_mmu_idx_el(env
, arm_current_el(env
));
10748 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
10750 CPUARMTBFlags flags
)
10752 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
10753 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
10755 if (arm_singlestep_active(env
)) {
10756 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
10761 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
10763 CPUARMTBFlags flags
)
10765 bool sctlr_b
= arm_sctlr_b(env
);
10768 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
10770 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
10771 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
10773 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
10775 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
10778 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
10781 CPUARMTBFlags flags
= {};
10782 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
10784 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
10785 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
10786 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
10789 if (arm_v7m_is_handler_mode(env
)) {
10790 DP_TBFLAG_M32(flags
, HANDLER
, 1);
10794 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
10795 * is suppressing them because the requested execution priority
10798 if (arm_feature(env
, ARM_FEATURE_V8
) &&
10799 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
10800 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
10801 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
10804 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
10807 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
10810 CPUARMTBFlags flags
= {};
10811 int el
= arm_current_el(env
);
10813 if (arm_sctlr(env
, el
) & SCTLR_A
) {
10814 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
10817 if (arm_el_is_aa64(env
, 1)) {
10818 DP_TBFLAG_A32(flags
, VFPEN
, 1);
10821 if (el
< 2 && env
->cp15
.hstr_el2
&&
10822 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10823 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
10826 if (env
->uncached_cpsr
& CPSR_IL
) {
10827 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
10831 * The SME exception we are testing for is raised via
10832 * AArch64.CheckFPAdvSIMDEnabled(), as called from
10833 * AArch32.CheckAdvSIMDOrFPEnabled().
10836 && FIELD_EX64(env
->svcr
, SVCR
, SM
)
10837 && (!arm_is_el2_enabled(env
)
10838 || (arm_el_is_aa64(env
, 2) && !(env
->cp15
.hcr_el2
& HCR_TGE
)))
10839 && arm_el_is_aa64(env
, 1)
10840 && !sme_fa64(env
, el
)) {
10841 DP_TBFLAG_A32(flags
, SME_TRAP_NONSTREAMING
, 1);
10844 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
10847 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
10850 CPUARMTBFlags flags
= {};
10851 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
10852 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
10856 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
10858 /* Get control bits for tagged addresses. */
10859 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10860 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10862 DP_TBFLAG_A64(flags
, TBII
, tbii
);
10863 DP_TBFLAG_A64(flags
, TBID
, tbid
);
10865 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
10866 int sve_el
= sve_exception_el(env
, el
);
10869 * If either FP or SVE are disabled, translator does not need len.
10870 * If SVE EL > FP EL, FP exception has precedence, and translator
10871 * does not need SVE EL. Save potential re-translations by forcing
10872 * the unneeded data to zero.
10875 if (sve_el
> fp_el
) {
10878 } else if (sve_el
== 0) {
10879 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
10881 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
10883 if (cpu_isar_feature(aa64_sme
, env_archcpu(env
))) {
10884 int sme_el
= sme_exception_el(env
, el
);
10885 bool sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
10887 DP_TBFLAG_A64(flags
, SMEEXC_EL
, sme_el
);
10889 /* Similarly, do not compute SVL if SME is disabled. */
10890 int svl
= sve_vqm1_for_el_sm(env
, el
, true);
10891 DP_TBFLAG_A64(flags
, SVL
, svl
);
10893 /* If SVE is disabled, we will not have set VL above. */
10894 DP_TBFLAG_A64(flags
, VL
, svl
);
10898 DP_TBFLAG_A64(flags
, PSTATE_SM
, 1);
10899 DP_TBFLAG_A64(flags
, SME_TRAP_NONSTREAMING
, !sme_fa64(env
, el
));
10901 DP_TBFLAG_A64(flags
, PSTATE_ZA
, FIELD_EX64(env
->svcr
, SVCR
, ZA
));
10904 sctlr
= regime_sctlr(env
, stage1
);
10906 if (sctlr
& SCTLR_A
) {
10907 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
10910 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
10911 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
10914 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
10916 * In order to save space in flags, we record only whether
10917 * pauth is "inactive", meaning all insns are implemented as
10918 * a nop, or "active" when some action must be performed.
10919 * The decision of which action to take is left to a helper.
10921 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
10922 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
10926 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
10927 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
10928 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
10929 DP_TBFLAG_A64(flags
, BT
, 1);
10933 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
10934 if (!(env
->pstate
& PSTATE_UAO
)) {
10936 case ARMMMUIdx_E10_1
:
10937 case ARMMMUIdx_E10_1_PAN
:
10938 case ARMMMUIdx_SE10_1
:
10939 case ARMMMUIdx_SE10_1_PAN
:
10940 /* TODO: ARMv8.3-NV */
10941 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
10943 case ARMMMUIdx_E20_2
:
10944 case ARMMMUIdx_E20_2_PAN
:
10945 case ARMMMUIdx_SE20_2
:
10946 case ARMMMUIdx_SE20_2_PAN
:
10948 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
10949 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
10951 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
10952 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
10960 if (env
->pstate
& PSTATE_IL
) {
10961 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
10964 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
10966 * Set MTE_ACTIVE if any access may be Checked, and leave clear
10967 * if all accesses must be Unchecked:
10968 * 1) If no TBI, then there are no tags in the address to check,
10969 * 2) If Tag Check Override, then all accesses are Unchecked,
10970 * 3) If Tag Check Fail == 0, then Checked access have no effect,
10971 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
10973 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
10974 DP_TBFLAG_A64(flags
, ATA
, 1);
10976 && !(env
->pstate
& PSTATE_TCO
)
10977 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
10978 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
10981 /* And again for unprivileged accesses, if required. */
10982 if (EX_TBFLAG_A64(flags
, UNPRIV
)
10984 && !(env
->pstate
& PSTATE_TCO
)
10985 && (sctlr
& SCTLR_TCF0
)
10986 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
10987 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
10989 /* Cache TCMA as well as TBI. */
10990 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
10993 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
10996 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
10998 int el
= arm_current_el(env
);
10999 int fp_el
= fp_exception_el(env
, el
);
11000 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11003 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11004 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11005 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11007 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11011 void arm_rebuild_hflags(CPUARMState
*env
)
11013 env
->hflags
= rebuild_hflags_internal(env
);
11017 * If we have triggered a EL state change we can't rely on the
11018 * translator having passed it to us, we need to recompute.
11020 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
11022 int el
= arm_current_el(env
);
11023 int fp_el
= fp_exception_el(env
, el
);
11024 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11026 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11029 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11031 int fp_el
= fp_exception_el(env
, el
);
11032 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11034 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11038 * If we have triggered a EL state change we can't rely on the
11039 * translator having passed it to us, we need to recompute.
11041 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
11043 int el
= arm_current_el(env
);
11044 int fp_el
= fp_exception_el(env
, el
);
11045 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11046 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11049 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11051 int fp_el
= fp_exception_el(env
, el
);
11052 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11054 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11057 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11059 int fp_el
= fp_exception_el(env
, el
);
11060 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11062 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11065 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
11067 #ifdef CONFIG_DEBUG_TCG
11068 CPUARMTBFlags c
= env
->hflags
;
11069 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
11071 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
11072 fprintf(stderr
, "TCG hflags mismatch "
11073 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
11074 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
11075 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
11081 static bool mve_no_pred(CPUARMState
*env
)
11084 * Return true if there is definitely no predication of MVE
11085 * instructions by VPR or LTPSIZE. (Returning false even if there
11086 * isn't any predication is OK; generated code will just be
11088 * If the CPU does not implement MVE then this TB flag is always 0.
11090 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
11091 * logic in gen_update_fp_context() needs to be updated to match.
11093 * We do not include the effect of the ECI bits here -- they are
11094 * tracked in other TB flags. This simplifies the logic for
11095 * "when did we emit code that changes the MVE_NO_PRED TB flag
11096 * and thus need to end the TB?".
11098 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
11101 if (env
->v7m
.vpr
) {
11104 if (env
->v7m
.ltpsize
< 4) {
11110 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11111 target_ulong
*cs_base
, uint32_t *pflags
)
11113 CPUARMTBFlags flags
;
11115 assert_hflags_rebuild_correctly(env
);
11116 flags
= env
->hflags
;
11118 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
11120 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11121 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
11124 *pc
= env
->regs
[15];
11126 if (arm_feature(env
, ARM_FEATURE_M
)) {
11127 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11128 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11129 != env
->v7m
.secure
) {
11130 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
11133 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11134 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11135 (env
->v7m
.secure
&&
11136 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11138 * ASPEN is set, but FPCA/SFPA indicate that there is no
11139 * active FP context; we must create a new FP context before
11140 * executing any FP insn.
11142 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
11145 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11146 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11147 DP_TBFLAG_M32(flags
, LSPACT
, 1);
11150 if (mve_no_pred(env
)) {
11151 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
11155 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11156 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11158 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11159 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11161 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
11162 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
11164 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11165 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11169 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
11170 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
11174 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11175 * states defined in the ARM ARM for software singlestep:
11176 * SS_ACTIVE PSTATE.SS State
11177 * 0 x Inactive (the TB flag for SS is always 0)
11178 * 1 0 Active-pending
11179 * 1 1 Active-not-pending
11180 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
11182 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
11183 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
11186 *pflags
= flags
.flags
;
11187 *cs_base
= flags
.flags2
;
11190 #ifdef TARGET_AARCH64
11192 * The manual says that when SVE is enabled and VQ is widened the
11193 * implementation is allowed to zero the previously inaccessible
11194 * portion of the registers. The corollary to that is that when
11195 * SVE is enabled and VQ is narrowed we are also allowed to zero
11196 * the now inaccessible portion of the registers.
11198 * The intent of this is that no predicate bit beyond VQ is ever set.
11199 * Which means that some operations on predicate registers themselves
11200 * may operate on full uint64_t or even unrolled across the maximum
11201 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11202 * may well be cheaper than conditionals to restrict the operation
11203 * to the relevant portion of a uint16_t[16].
11205 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11210 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11211 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11213 /* Zap the high bits of the zregs. */
11214 for (i
= 0; i
< 32; i
++) {
11215 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11218 /* Zap the high bits of the pregs and ffr. */
11221 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11223 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11224 for (i
= 0; i
< 17; ++i
) {
11225 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11231 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
11236 exc_el
= sme_exception_el(env
, el
);
11238 exc_el
= sve_exception_el(env
, el
);
11241 return 0; /* disabled */
11243 return sve_vqm1_for_el_sm(env
, el
, sm
);
11247 * Notice a change in SVE vector size when changing EL.
11249 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11250 int new_el
, bool el0_a64
)
11252 ARMCPU
*cpu
= env_archcpu(env
);
11253 int old_len
, new_len
;
11254 bool old_a64
, new_a64
, sm
;
11256 /* Nothing to do if no SVE. */
11257 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11261 /* Nothing to do if FP is disabled in either EL. */
11262 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11266 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11267 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11270 * Both AArch64.TakeException and AArch64.ExceptionReturn
11271 * invoke ResetSVEState when taking an exception from, or
11272 * returning to, AArch32 state when PSTATE.SM is enabled.
11274 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
11275 if (old_a64
!= new_a64
&& sm
) {
11276 arm_reset_sve_state(env
);
11281 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11282 * at ELx, or not available because the EL is in AArch32 state, then
11283 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11284 * has an effective value of 0".
11286 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11287 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11288 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11289 * we already have the correct register contents when encountering the
11290 * vq0->vq0 transition between EL0->EL1.
11292 old_len
= new_len
= 0;
11294 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
11297 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
11300 /* When changing vector length, clear inaccessible state. */
11301 if (new_len
< old_len
) {
11302 aarch64_sve_narrow_vq(env
, new_len
+ 1);