4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
24 #include "cpu_loop-common.h"
25 #include "semihosting/common-semi.h"
27 #define get_user_code_u32(x, gaddr, env) \
28 ({ abi_long __r = get_user_u32((x), (gaddr)); \
29 if (!__r && bswap_code(arm_sctlr_b(env))) { \
35 #define get_user_code_u16(x, gaddr, env) \
36 ({ abi_long __r = get_user_u16((x), (gaddr)); \
37 if (!__r && bswap_code(arm_sctlr_b(env))) { \
43 #define get_user_data_u32(x, gaddr, env) \
44 ({ abi_long __r = get_user_u32((x), (gaddr)); \
45 if (!__r && arm_cpu_bswap_data(env)) { \
51 #define get_user_data_u16(x, gaddr, env) \
52 ({ abi_long __r = get_user_u16((x), (gaddr)); \
53 if (!__r && arm_cpu_bswap_data(env)) { \
59 #define put_user_data_u32(x, gaddr, env) \
60 ({ typeof(x) __x = (x); \
61 if (arm_cpu_bswap_data(env)) { \
64 put_user_u32(__x, (gaddr)); \
67 #define put_user_data_u16(x, gaddr, env) \
68 ({ typeof(x) __x = (x); \
69 if (arm_cpu_bswap_data(env)) { \
72 put_user_u16(__x, (gaddr)); \
75 /* Commpage handling -- there is no commpage for AArch64 */
78 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
80 * r0 = pointer to oldval
81 * r1 = pointer to newval
82 * r2 = pointer to target value
85 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
86 * C set if *ptr was changed, clear if no exchange happened
88 * Note segv's in kernel helpers are a bit tricky, we can set the
89 * data address sensibly but the PC address is just the entry point.
91 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
93 uint64_t oldval
, newval
, val
;
95 target_siginfo_t info
;
97 /* Based on the 32 bit code in do_kernel_trap */
99 /* XXX: This only works between threads, not between processes.
100 It's probably possible to implement this with native host
101 operations. However things like ldrex/strex are much harder so
102 there's not much point trying. */
104 cpsr
= cpsr_read(env
);
107 if (get_user_u64(oldval
, env
->regs
[0])) {
108 env
->exception
.vaddress
= env
->regs
[0];
112 if (get_user_u64(newval
, env
->regs
[1])) {
113 env
->exception
.vaddress
= env
->regs
[1];
117 if (get_user_u64(val
, addr
)) {
118 env
->exception
.vaddress
= addr
;
125 if (put_user_u64(val
, addr
)) {
126 env
->exception
.vaddress
= addr
;
136 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
142 /* We get the PC of the entry address - which is as good as anything,
143 on a real kernel what you get depends on which mode it uses. */
144 info
.si_signo
= TARGET_SIGSEGV
;
146 /* XXX: check env->error_code */
147 info
.si_code
= TARGET_SEGV_MAPERR
;
148 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
149 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
152 /* Handle a jump to the kernel code page. */
154 do_kernel_trap(CPUARMState
*env
)
160 switch (env
->regs
[15]) {
161 case 0xffff0fa0: /* __kernel_memory_barrier */
162 /* ??? No-op. Will need to do better for SMP. */
164 case 0xffff0fc0: /* __kernel_cmpxchg */
165 /* XXX: This only works between threads, not between processes.
166 It's probably possible to implement this with native host
167 operations. However things like ldrex/strex are much harder so
168 there's not much point trying. */
170 cpsr
= cpsr_read(env
);
172 /* FIXME: This should SEGV if the access fails. */
173 if (get_user_u32(val
, addr
))
175 if (val
== env
->regs
[0]) {
177 /* FIXME: Check for segfaults. */
178 put_user_u32(val
, addr
);
185 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
188 case 0xffff0fe0: /* __kernel_get_tls */
189 env
->regs
[0] = cpu_get_tls(env
);
191 case 0xffff0f60: /* __kernel_cmpxchg64 */
192 arm_kernel_cmpxchg64_helper(env
);
198 /* Jump back to the caller. */
199 addr
= env
->regs
[14];
204 env
->regs
[15] = addr
;
209 static bool insn_is_linux_bkpt(uint32_t opcode
, bool is_thumb
)
212 * Return true if this insn is one of the three magic UDF insns
213 * which the kernel treats as breakpoint insns.
216 return (opcode
& 0x0fffffff) == 0x07f001f0;
219 * Note that we get the two halves of the 32-bit T32 insn
220 * in the opposite order to the value the kernel uses in
221 * its undef_hook struct.
223 return ((opcode
& 0xffff) == 0xde01) || (opcode
== 0xa000f7f0);
227 static bool emulate_arm_fpa11(CPUARMState
*env
, uint32_t opcode
)
229 TaskState
*ts
= env_cpu(env
)->opaque
;
230 int rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
233 /* Illegal instruction */
245 /* Translate softfloat flags to FPSR flags */
246 if (-rc
& float_flag_invalid
) {
249 if (-rc
& float_flag_divbyzero
) {
252 if (-rc
& float_flag_overflow
) {
255 if (-rc
& float_flag_underflow
) {
258 if (-rc
& float_flag_inexact
) {
262 /* Exception enabled? */
263 FPSR fpsr
= ts
->fpa
.fpsr
;
264 if (fpsr
& (arm_fpe
<< 16)) {
265 target_siginfo_t info
;
267 info
.si_signo
= TARGET_SIGFPE
;
270 /* ordered by priority, least first */
271 if (arm_fpe
& BIT_IXC
) {
272 info
.si_code
= TARGET_FPE_FLTRES
;
274 if (arm_fpe
& BIT_UFC
) {
275 info
.si_code
= TARGET_FPE_FLTUND
;
277 if (arm_fpe
& BIT_OFC
) {
278 info
.si_code
= TARGET_FPE_FLTOVF
;
280 if (arm_fpe
& BIT_DZC
) {
281 info
.si_code
= TARGET_FPE_FLTDIV
;
283 if (arm_fpe
& BIT_IOC
) {
284 info
.si_code
= TARGET_FPE_FLTINV
;
287 info
._sifields
._sigfault
._addr
= env
->regs
[15];
288 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
293 /* Accumulate unenabled exceptions */
294 if ((!(fpsr
& BIT_IXE
)) && (arm_fpe
& BIT_IXC
)) {
297 if ((!(fpsr
& BIT_UFE
)) && (arm_fpe
& BIT_UFC
)) {
300 if ((!(fpsr
& BIT_OFE
)) && (arm_fpe
& BIT_OFC
)) {
303 if ((!(fpsr
& BIT_DZE
)) && (arm_fpe
& BIT_DZC
)) {
306 if ((!(fpsr
& BIT_IOE
)) && (arm_fpe
& BIT_IOC
)) {
313 void cpu_loop(CPUARMState
*env
)
315 CPUState
*cs
= env_cpu(env
);
317 unsigned int n
, insn
;
318 target_siginfo_t info
;
324 trapnr
= cpu_exec(cs
);
326 process_queued_cpu_work(cs
);
335 /* we handle the FPU emulation here, as Linux */
336 /* we get the opcode */
337 /* FIXME - what to do if get_user() fails? */
338 get_user_code_u32(opcode
, env
->regs
[15], env
);
341 * The Linux kernel treats some UDF patterns specially
342 * to use as breakpoints (instead of the architectural
343 * bkpt insn). These should trigger a SIGTRAP rather
346 if (insn_is_linux_bkpt(opcode
, env
->thumb
)) {
350 if (emulate_arm_fpa11(env
, opcode
)) {
354 info
.si_signo
= TARGET_SIGILL
;
356 info
.si_code
= TARGET_ILL_ILLOPN
;
357 info
._sifields
._sigfault
._addr
= env
->regs
[15];
358 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
366 /* Thumb is always EABI style with syscall number in r7 */
370 * Equivalent of kernel CONFIG_OABI_COMPAT: read the
371 * Arm SVC insn to extract the immediate, which is the
372 * syscall number in OABI.
374 /* FIXME - what to do if get_user() fails? */
375 get_user_code_u32(insn
, env
->regs
[15] - 4, env
);
378 /* zero immediate: EABI, syscall number in r7 */
382 * This XOR matches the kernel code: an immediate
383 * in the valid range (0x900000 .. 0x9fffff) is
384 * converted into the correct EABI-style syscall
385 * number; invalid immediates end up as values
386 * > 0xfffff and are handled below as out-of-range.
388 n
^= ARM_SYSCALL_BASE
;
393 if (n
> ARM_NR_BASE
) {
395 case ARM_NR_cacheflush
:
399 cpu_set_tls(env
, env
->regs
[0]);
402 case ARM_NR_breakpoint
:
403 env
->regs
[15] -= env
->thumb
? 2 : 4;
406 env
->regs
[0] = cpu_get_tls(env
);
411 * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
412 * 0x9f07ff in OABI numbering) are defined
413 * to return -ENOSYS rather than raising
414 * SIGILL. Note that we have already
415 * removed the 0x900000 prefix.
417 qemu_log_mask(LOG_UNIMP
,
418 "qemu: Unsupported ARM syscall: 0x%x\n",
420 env
->regs
[0] = -TARGET_ENOSYS
;
423 * Otherwise SIGILL. This includes any SWI with
424 * immediate not originally 0x9fxxxx, because
425 * of the earlier XOR.
427 info
.si_signo
= TARGET_SIGILL
;
429 info
.si_code
= TARGET_ILL_ILLTRP
;
430 info
._sifields
._sigfault
._addr
= env
->regs
[15];
432 info
._sifields
._sigfault
._addr
-= 2;
434 info
._sifields
._sigfault
._addr
-= 4;
436 queue_signal(env
, info
.si_signo
,
437 QEMU_SI_FAULT
, &info
);
442 ret
= do_syscall(env
,
451 if (ret
== -TARGET_ERESTARTSYS
) {
452 env
->regs
[15] -= env
->thumb
? 2 : 4;
453 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
460 env
->regs
[0] = do_common_semihosting(cs
);
461 env
->regs
[15] += env
->thumb
? 2 : 4;
464 /* just indicate that signals should be handled asap */
466 case EXCP_PREFETCH_ABORT
:
467 case EXCP_DATA_ABORT
:
468 addr
= env
->exception
.vaddress
;
470 info
.si_signo
= TARGET_SIGSEGV
;
472 /* XXX: check env->error_code */
473 info
.si_code
= TARGET_SEGV_MAPERR
;
474 info
._sifields
._sigfault
._addr
= addr
;
475 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
481 info
.si_signo
= TARGET_SIGTRAP
;
483 info
.si_code
= TARGET_TRAP_BRKPT
;
484 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
486 case EXCP_KERNEL_TRAP
:
487 if (do_kernel_trap(env
))
491 /* nothing to do here for user-mode, just resume guest code */
494 cpu_exec_step_atomic(cs
);
498 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
501 process_pending_signals(env
);
505 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
507 CPUState
*cpu
= env_cpu(env
);
508 TaskState
*ts
= cpu
->opaque
;
509 struct image_info
*info
= ts
->info
;
512 cpsr_write(env
, regs
->uregs
[16], CPSR_USER
| CPSR_EXEC
,
514 for(i
= 0; i
< 16; i
++) {
515 env
->regs
[i
] = regs
->uregs
[i
];
517 #ifdef TARGET_WORDS_BIGENDIAN
519 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
520 && (info
->elf_flags
& EF_ARM_BE8
)) {
521 env
->uncached_cpsr
|= CPSR_E
;
522 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
524 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
526 arm_rebuild_hflags(env
);
529 ts
->stack_base
= info
->start_stack
;
530 ts
->heap_base
= info
->brk
;
531 /* This will be filled in on the first SYS_HEAPINFO call. */