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net/vmxnet3: rename VMXNET3_DEVICE_VERSION to VMXNET3_UPT_REVISION
[qemu/ar7.git] / hw / net / vmxnet3.c
blob63692c5d27cbb6113597a06ee7dafe9b988a4a17
1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "hw/hw.h"
19 #include "hw/pci/pci.h"
20 #include "net/net.h"
21 #include "net/tap.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
28
29 #include "vmxnet3.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
34
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
37 #define MIN_BUF_SIZE 60
38
39 #define VMXNET3_BAR0_IDX (0)
40 #define VMXNET3_BAR1_IDX (1)
41 #define VMXNET3_MSIX_BAR_IDX (2)
42
43 #define VMXNET3_OFF_MSIX_TABLE (0x000)
44 #define VMXNET3_OFF_MSIX_PBA (0x800)
45
46 /* Link speed in Mbps should be shifted by 16 */
47 #define VMXNET3_LINK_SPEED (1000 << 16)
48
49 /* Link status: 1 - up, 0 - down. */
50 #define VMXNET3_LINK_STATUS_UP 0x1
51
52 /* Least significant bit should be set for revision and version */
53 #define VMXNET3_UPT_REVISION 0x1
54 #define VMXNET3_DEVICE_REVISION 0x1
55
56 /* Number of interrupt vectors for non-MSIx modes */
57 #define VMXNET3_MAX_NMSIX_INTRS (1)
58
59 /* Macros for rings descriptors access */
60 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
61 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
62
63 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
64 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
65
66 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
67 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
68
69 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
70 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
71
72 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
73 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
74
75 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
76 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
77
78 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
79 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
80
81 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
82 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
83
84 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
85 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
86
87 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
88 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
89
90 /* Macros for guest driver shared area access */
91 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
92 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
93
94 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
95 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
96
97 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
98 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
99
100 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
101 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
102
103 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
104 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
105
106 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
107 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
108
109 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
110
111 #define TYPE_VMXNET3 "vmxnet3"
112 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
113
114 /* Cyclic ring abstraction */
115 typedef struct {
116 hwaddr pa;
117 size_t size;
118 size_t cell_size;
119 size_t next;
120 uint8_t gen;
121 } Vmxnet3Ring;
122
123 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
124 hwaddr pa,
125 size_t size,
126 size_t cell_size,
127 bool zero_region)
128 {
129 ring->pa = pa;
130 ring->size = size;
131 ring->cell_size = cell_size;
132 ring->gen = VMXNET3_INIT_GEN;
133 ring->next = 0;
134
135 if (zero_region) {
136 vmw_shmem_set(pa, 0, size * cell_size);
137 }
138 }
139
140 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
141 macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \
142 (ring_name), (ridx), \
143 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
144
145 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
146 {
147 if (++ring->next >= ring->size) {
148 ring->next = 0;
149 ring->gen ^= 1;
150 }
151 }
152
153 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
154 {
155 if (ring->next-- == 0) {
156 ring->next = ring->size - 1;
157 ring->gen ^= 1;
158 }
159 }
160
161 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
162 {
163 return ring->pa + ring->next * ring->cell_size;
164 }
165
166 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
167 {
168 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
169 }
170
171 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
172 {
173 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
174 }
175
176 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
177 {
178 return ring->next;
179 }
180
181 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
182 {
183 return ring->gen;
184 }
185
186 /* Debug trace-related functions */
187 static inline void
188 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
189 {
190 VMW_PKPRN("TX DESCR: "
191 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
192 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
193 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
194 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
195 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
196 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
197 }
198
199 static inline void
200 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
201 {
202 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
203 "csum_start: %d, csum_offset: %d",
204 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
205 vhdr->csum_start, vhdr->csum_offset);
206 }
207
208 static inline void
209 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
210 {
211 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
212 "dtype: %d, ext1: %d, btype: %d",
213 le64_to_cpu(descr->addr), descr->len, descr->gen,
214 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
215 }
216
217 /* Device state and helper functions */
218 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
219
220 typedef struct {
221 Vmxnet3Ring tx_ring;
222 Vmxnet3Ring comp_ring;
223
224 uint8_t intr_idx;
225 hwaddr tx_stats_pa;
226 struct UPT1_TxStats txq_stats;
227 } Vmxnet3TxqDescr;
228
229 typedef struct {
230 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
231 Vmxnet3Ring comp_ring;
232 uint8_t intr_idx;
233 hwaddr rx_stats_pa;
234 struct UPT1_RxStats rxq_stats;
235 } Vmxnet3RxqDescr;
236
237 typedef struct {
238 bool is_masked;
239 bool is_pending;
240 bool is_asserted;
241 } Vmxnet3IntState;
242
243 typedef struct {
244 PCIDevice parent_obj;
245 NICState *nic;
246 NICConf conf;
247 MemoryRegion bar0;
248 MemoryRegion bar1;
249 MemoryRegion msix_bar;
250
251 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
252 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
253
254 /* Whether MSI-X support was installed successfully */
255 bool msix_used;
256 /* Whether MSI support was installed successfully */
257 bool msi_used;
258 hwaddr drv_shmem;
259 hwaddr temp_shared_guest_driver_memory;
260
261 uint8_t txq_num;
262
263 /* This boolean tells whether RX packet being indicated has to */
264 /* be split into head and body chunks from different RX rings */
265 bool rx_packets_compound;
266
267 bool rx_vlan_stripping;
268 bool lro_supported;
269
270 uint8_t rxq_num;
271
272 /* Network MTU */
273 uint32_t mtu;
274
275 /* Maximum number of fragments for indicated TX packets */
276 uint32_t max_tx_frags;
277
278 /* Maximum number of fragments for indicated RX packets */
279 uint16_t max_rx_frags;
280
281 /* Index for events interrupt */
282 uint8_t event_int_idx;
283
284 /* Whether automatic interrupts masking enabled */
285 bool auto_int_masking;
286
287 bool peer_has_vhdr;
288
289 /* TX packets to QEMU interface */
290 struct VmxnetTxPkt *tx_pkt;
291 uint32_t offload_mode;
292 uint32_t cso_or_gso_size;
293 uint16_t tci;
294 bool needs_vlan;
295
296 struct VmxnetRxPkt *rx_pkt;
297
298 bool tx_sop;
299 bool skip_current_tx_pkt;
300
301 uint32_t device_active;
302 uint32_t last_command;
303
304 uint32_t link_status_and_speed;
305
306 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
307
308 uint32_t temp_mac; /* To store the low part first */
309
310 MACAddr perm_mac;
311 uint32_t vlan_table[VMXNET3_VFT_SIZE];
312 uint32_t rx_mode;
313 MACAddr *mcast_list;
314 uint32_t mcast_list_len;
315 uint32_t mcast_list_buff_size; /* needed for live migration. */
316 } VMXNET3State;
317
318 /* Interrupt management */
319
320 /*
321 *This function returns sign whether interrupt line is in asserted state
322 * This depends on the type of interrupt used. For INTX interrupt line will
323 * be asserted until explicit deassertion, for MSI(X) interrupt line will
324 * be deasserted automatically due to notification semantics of the MSI(X)
325 * interrupts
326 */
327 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
328 {
329 PCIDevice *d = PCI_DEVICE(s);
330
331 if (s->msix_used && msix_enabled(d)) {
332 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
333 msix_notify(d, int_idx);
334 return false;
335 }
336 if (s->msi_used && msi_enabled(d)) {
337 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
338 msi_notify(d, int_idx);
339 return false;
340 }
341
342 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
343 pci_irq_assert(d);
344 return true;
345 }
346
347 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
348 {
349 PCIDevice *d = PCI_DEVICE(s);
350
351 /*
352 * This function should never be called for MSI(X) interrupts
353 * because deassertion never required for message interrupts
354 */
355 assert(!s->msix_used || !msix_enabled(d));
356 /*
357 * This function should never be called for MSI(X) interrupts
358 * because deassertion never required for message interrupts
359 */
360 assert(!s->msi_used || !msi_enabled(d));
361
362 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
363 pci_irq_deassert(d);
364 }
365
366 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
367 {
368 if (!s->interrupt_states[lidx].is_pending &&
369 s->interrupt_states[lidx].is_asserted) {
370 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
371 _vmxnet3_deassert_interrupt_line(s, lidx);
372 s->interrupt_states[lidx].is_asserted = false;
373 return;
374 }
375
376 if (s->interrupt_states[lidx].is_pending &&
377 !s->interrupt_states[lidx].is_masked &&
378 !s->interrupt_states[lidx].is_asserted) {
379 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
380 s->interrupt_states[lidx].is_asserted =
381 _vmxnet3_assert_interrupt_line(s, lidx);
382 s->interrupt_states[lidx].is_pending = false;
383 return;
384 }
385 }
386
387 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
388 {
389 PCIDevice *d = PCI_DEVICE(s);
390 s->interrupt_states[lidx].is_pending = true;
391 vmxnet3_update_interrupt_line_state(s, lidx);
392
393 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
394 goto do_automask;
395 }
396
397 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
398 goto do_automask;
399 }
400
401 return;
402
403 do_automask:
404 s->interrupt_states[lidx].is_masked = true;
405 vmxnet3_update_interrupt_line_state(s, lidx);
406 }
407
408 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
409 {
410 return s->interrupt_states[lidx].is_asserted;
411 }
412
413 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
414 {
415 s->interrupt_states[int_idx].is_pending = false;
416 if (s->auto_int_masking) {
417 s->interrupt_states[int_idx].is_masked = true;
418 }
419 vmxnet3_update_interrupt_line_state(s, int_idx);
420 }
421
422 static void
423 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
424 {
425 s->interrupt_states[lidx].is_masked = is_masked;
426 vmxnet3_update_interrupt_line_state(s, lidx);
427 }
428
429 static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
430 {
431 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
432 }
433
434 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
435 #define VMXNET3_MAKE_BYTE(byte_num, val) \
436 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
437
438 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
439 {
440 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
441 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
442 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
443 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
444 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
445 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
446
447 VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
448
449 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
450 }
451
452 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
453 {
454 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
455 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
456 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
457 VMXNET3_MAKE_BYTE(3, addr->a[3]);
458 }
459
460 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
461 {
462 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
463 VMXNET3_MAKE_BYTE(1, addr->a[5]);
464 }
465
466 static void
467 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
468 {
469 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
470 }
471
472 static inline void
473 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
474 {
475 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
476 }
477
478 static inline void
479 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
480 {
481 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
482 }
483
484 static void
485 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
486 {
487 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
488 }
489
490 static void
491 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
492 {
493 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
494 }
495
496 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)
497 {
498 struct Vmxnet3_TxCompDesc txcq_descr;
499
500 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
501
502 txcq_descr.txdIdx = tx_ridx;
503 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
504
505 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
506
507 /* Flush changes in TX descriptor before changing the counter value */
508 smp_wmb();
509
510 vmxnet3_inc_tx_completion_counter(s, qidx);
511 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
512 }
513
514 static bool
515 vmxnet3_setup_tx_offloads(VMXNET3State *s)
516 {
517 switch (s->offload_mode) {
518 case VMXNET3_OM_NONE:
519 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
520 break;
521
522 case VMXNET3_OM_CSUM:
523 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
524 VMW_PKPRN("L4 CSO requested\n");
525 break;
526
527 case VMXNET3_OM_TSO:
528 vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
529 s->cso_or_gso_size);
530 vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
531 VMW_PKPRN("GSO offload requested.");
532 break;
533
534 default:
535 g_assert_not_reached();
536 return false;
537 }
538
539 return true;
540 }
541
542 static void
543 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
544 const struct Vmxnet3_TxDesc *txd)
545 {
546 s->offload_mode = txd->om;
547 s->cso_or_gso_size = txd->msscof;
548 s->tci = txd->tci;
549 s->needs_vlan = txd->ti;
550 }
551
552 typedef enum {
553 VMXNET3_PKT_STATUS_OK,
554 VMXNET3_PKT_STATUS_ERROR,
555 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
556 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
557 } Vmxnet3PktStatus;
558
559 static void
560 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
561 Vmxnet3PktStatus status)
562 {
563 size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
564 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
565
566 switch (status) {
567 case VMXNET3_PKT_STATUS_OK:
568 switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
569 case ETH_PKT_BCAST:
570 stats->bcastPktsTxOK++;
571 stats->bcastBytesTxOK += tot_len;
572 break;
573 case ETH_PKT_MCAST:
574 stats->mcastPktsTxOK++;
575 stats->mcastBytesTxOK += tot_len;
576 break;
577 case ETH_PKT_UCAST:
578 stats->ucastPktsTxOK++;
579 stats->ucastBytesTxOK += tot_len;
580 break;
581 default:
582 g_assert_not_reached();
583 }
584
585 if (s->offload_mode == VMXNET3_OM_TSO) {
586 /*
587 * According to VMWARE headers this statistic is a number
588 * of packets after segmentation but since we don't have
589 * this information in QEMU model, the best we can do is to
590 * provide number of non-segmented packets
591 */
592 stats->TSOPktsTxOK++;
593 stats->TSOBytesTxOK += tot_len;
594 }
595 break;
596
597 case VMXNET3_PKT_STATUS_DISCARD:
598 stats->pktsTxDiscard++;
599 break;
600
601 case VMXNET3_PKT_STATUS_ERROR:
602 stats->pktsTxError++;
603 break;
604
605 default:
606 g_assert_not_reached();
607 }
608 }
609
610 static void
611 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
612 int qidx,
613 Vmxnet3PktStatus status)
614 {
615 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
616 size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
617
618 switch (status) {
619 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
620 stats->pktsRxOutOfBuf++;
621 break;
622
623 case VMXNET3_PKT_STATUS_ERROR:
624 stats->pktsRxError++;
625 break;
626 case VMXNET3_PKT_STATUS_OK:
627 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
628 case ETH_PKT_BCAST:
629 stats->bcastPktsRxOK++;
630 stats->bcastBytesRxOK += tot_len;
631 break;
632 case ETH_PKT_MCAST:
633 stats->mcastPktsRxOK++;
634 stats->mcastBytesRxOK += tot_len;
635 break;
636 case ETH_PKT_UCAST:
637 stats->ucastPktsRxOK++;
638 stats->ucastBytesRxOK += tot_len;
639 break;
640 default:
641 g_assert_not_reached();
642 }
643
644 if (tot_len > s->mtu) {
645 stats->LROPktsRxOK++;
646 stats->LROBytesRxOK += tot_len;
647 }
648 break;
649 default:
650 g_assert_not_reached();
651 }
652 }
653
654 static inline bool
655 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
656 int qidx,
657 struct Vmxnet3_TxDesc *txd,
658 uint32_t *descr_idx)
659 {
660 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
661
662 vmxnet3_ring_read_curr_cell(ring, txd);
663 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
664 /* Only read after generation field verification */
665 smp_rmb();
666 /* Re-read to be sure we got the latest version */
667 vmxnet3_ring_read_curr_cell(ring, txd);
668 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
669 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
670 vmxnet3_inc_tx_consumption_counter(s, qidx);
671 return true;
672 }
673
674 return false;
675 }
676
677 static bool
678 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
679 {
680 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
681
682 if (!vmxnet3_setup_tx_offloads(s)) {
683 status = VMXNET3_PKT_STATUS_ERROR;
684 goto func_exit;
685 }
686
687 /* debug prints */
688 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
689 vmxnet_tx_pkt_dump(s->tx_pkt);
690
691 if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
692 status = VMXNET3_PKT_STATUS_DISCARD;
693 goto func_exit;
694 }
695
696 func_exit:
697 vmxnet3_on_tx_done_update_stats(s, qidx, status);
698 return (status == VMXNET3_PKT_STATUS_OK);
699 }
700
701 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
702 {
703 struct Vmxnet3_TxDesc txd;
704 uint32_t txd_idx;
705 uint32_t data_len;
706 hwaddr data_pa;
707
708 for (;;) {
709 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
710 break;
711 }
712
713 vmxnet3_dump_tx_descr(&txd);
714
715 if (!s->skip_current_tx_pkt) {
716 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
717 data_pa = le64_to_cpu(txd.addr);
718
719 if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
720 data_pa,
721 data_len)) {
722 s->skip_current_tx_pkt = true;
723 }
724 }
725
726 if (s->tx_sop) {
727 vmxnet3_tx_retrieve_metadata(s, &txd);
728 s->tx_sop = false;
729 }
730
731 if (txd.eop) {
732 if (!s->skip_current_tx_pkt && vmxnet_tx_pkt_parse(s->tx_pkt)) {
733 if (s->needs_vlan) {
734 vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
735 }
736
737 vmxnet3_send_packet(s, qidx);
738 } else {
739 vmxnet3_on_tx_done_update_stats(s, qidx,
740 VMXNET3_PKT_STATUS_ERROR);
741 }
742
743 vmxnet3_complete_packet(s, qidx, txd_idx);
744 s->tx_sop = true;
745 s->skip_current_tx_pkt = false;
746 vmxnet_tx_pkt_reset(s->tx_pkt);
747 }
748 }
749 }
750
751 static inline void
752 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
753 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
754 {
755 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
756 *didx = vmxnet3_ring_curr_cell_idx(ring);
757 vmxnet3_ring_read_curr_cell(ring, dbuf);
758 }
759
760 static inline uint8_t
761 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
762 {
763 return s->rxq_descr[qidx].rx_ring[ridx].gen;
764 }
765
766 static inline hwaddr
767 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
768 {
769 uint8_t ring_gen;
770 struct Vmxnet3_RxCompDesc rxcd;
771
772 hwaddr daddr =
773 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
774
775 cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
776 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
777
778 if (rxcd.gen != ring_gen) {
779 *descr_gen = ring_gen;
780 vmxnet3_inc_rx_completion_counter(s, qidx);
781 return daddr;
782 }
783
784 return 0;
785 }
786
787 static inline void
788 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
789 {
790 vmxnet3_dec_rx_completion_counter(s, qidx);
791 }
792
793 #define RXQ_IDX (0)
794 #define RX_HEAD_BODY_RING (0)
795 #define RX_BODY_ONLY_RING (1)
796
797 static bool
798 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
799 struct Vmxnet3_RxDesc *descr_buf,
800 uint32_t *descr_idx,
801 uint32_t *ridx)
802 {
803 for (;;) {
804 uint32_t ring_gen;
805 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
806 descr_buf, descr_idx);
807
808 /* If no more free descriptors - return */
809 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
810 if (descr_buf->gen != ring_gen) {
811 return false;
812 }
813
814 /* Only read after generation field verification */
815 smp_rmb();
816 /* Re-read to be sure we got the latest version */
817 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
818 descr_buf, descr_idx);
819
820 /* Mark current descriptor as used/skipped */
821 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
822
823 /* If this is what we are looking for - return */
824 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
825 *ridx = RX_HEAD_BODY_RING;
826 return true;
827 }
828 }
829 }
830
831 static bool
832 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
833 struct Vmxnet3_RxDesc *d,
834 uint32_t *didx,
835 uint32_t *ridx)
836 {
837 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
838
839 /* Try to find corresponding descriptor in head/body ring */
840 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
841 /* Only read after generation field verification */
842 smp_rmb();
843 /* Re-read to be sure we got the latest version */
844 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
845 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
846 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
847 *ridx = RX_HEAD_BODY_RING;
848 return true;
849 }
850 }
851
852 /*
853 * If there is no free descriptors on head/body ring or next free
854 * descriptor is a head descriptor switch to body only ring
855 */
856 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
857
858 /* If no more free descriptors - return */
859 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
860 /* Only read after generation field verification */
861 smp_rmb();
862 /* Re-read to be sure we got the latest version */
863 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
864 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
865 *ridx = RX_BODY_ONLY_RING;
866 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
867 return true;
868 }
869
870 return false;
871 }
872
873 static inline bool
874 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
875 struct Vmxnet3_RxDesc *descr_buf,
876 uint32_t *descr_idx,
877 uint32_t *ridx)
878 {
879 if (is_head || !s->rx_packets_compound) {
880 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
881 } else {
882 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
883 }
884 }
885
886 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
887 * the implementation always passes an RxCompDesc with a "Checksum
888 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
889 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
890 *
891 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
892 * and place a fully computed checksum into the tcp/udp header.
893 * Otherwise, the OS driver will receive a checksum-correct indication
894 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
895 * having just the pseudo header csum value.
896 *
897 * While this is not a problem if packet is destined for local delivery,
898 * in the case the host OS performs forwarding, it will forward an
899 * incorrectly checksummed packet.
900 */
901 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt *pkt,
902 const void *pkt_data,
903 size_t pkt_len)
904 {
905 struct virtio_net_hdr *vhdr;
906 bool isip4, isip6, istcp, isudp;
907 uint8_t *data;
908 int len;
909
910 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
911 return;
912 }
913
914 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
915 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
916 return;
917 }
918
919 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
920 if (!(isip4 || isip6) || !(istcp || isudp)) {
921 return;
922 }
923
924 vmxnet3_dump_virt_hdr(vhdr);
925
926 /* Validate packet len: csum_start + scum_offset + length of csum field */
927 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
928 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
929 "cannot calculate checksum",
930 pkt_len, vhdr->csum_start, vhdr->csum_offset);
931 return;
932 }
933
934 data = (uint8_t *)pkt_data + vhdr->csum_start;
935 len = pkt_len - vhdr->csum_start;
936 /* Put the checksum obtained into the packet */
937 stw_be_p(data + vhdr->csum_offset, net_raw_checksum(data, len));
938
939 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
940 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
941 }
942
943 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
944 struct Vmxnet3_RxCompDesc *rxcd)
945 {
946 int csum_ok, is_gso;
947 bool isip4, isip6, istcp, isudp;
948 struct virtio_net_hdr *vhdr;
949 uint8_t offload_type;
950
951 if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
952 rxcd->ts = 1;
953 rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
954 }
955
956 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
957 goto nocsum;
958 }
959
960 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
961 /*
962 * Checksum is valid when lower level tell so or when lower level
963 * requires checksum offload telling that packet produced/bridged
964 * locally and did travel over network after last checksum calculation
965 * or production
966 */
967 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
968 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
969
970 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
971 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
972
973 if (!csum_ok && !is_gso) {
974 goto nocsum;
975 }
976
977 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
978 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
979 goto nocsum;
980 }
981
982 rxcd->cnc = 0;
983 rxcd->v4 = isip4 ? 1 : 0;
984 rxcd->v6 = isip6 ? 1 : 0;
985 rxcd->tcp = istcp ? 1 : 0;
986 rxcd->udp = isudp ? 1 : 0;
987 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
988 return;
989
990 nocsum:
991 rxcd->cnc = 1;
992 return;
993 }
994
995 static void
996 vmxnet3_physical_memory_writev(const struct iovec *iov,
997 size_t start_iov_off,
998 hwaddr target_addr,
999 size_t bytes_to_copy)
1000 {
1001 size_t curr_off = 0;
1002 size_t copied = 0;
1003
1004 while (bytes_to_copy) {
1005 if (start_iov_off < (curr_off + iov->iov_len)) {
1006 size_t chunk_len =
1007 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
1008
1009 cpu_physical_memory_write(target_addr + copied,
1010 iov->iov_base + start_iov_off - curr_off,
1011 chunk_len);
1012
1013 copied += chunk_len;
1014 start_iov_off += chunk_len;
1015 curr_off = start_iov_off;
1016 bytes_to_copy -= chunk_len;
1017 } else {
1018 curr_off += iov->iov_len;
1019 }
1020 iov++;
1021 }
1022 }
1023
1024 static bool
1025 vmxnet3_indicate_packet(VMXNET3State *s)
1026 {
1027 struct Vmxnet3_RxDesc rxd;
1028 bool is_head = true;
1029 uint32_t rxd_idx;
1030 uint32_t rx_ridx = 0;
1031
1032 struct Vmxnet3_RxCompDesc rxcd;
1033 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
1034 hwaddr new_rxcd_pa = 0;
1035 hwaddr ready_rxcd_pa = 0;
1036 struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
1037 size_t bytes_copied = 0;
1038 size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
1039 uint16_t num_frags = 0;
1040 size_t chunk_size;
1041
1042 vmxnet_rx_pkt_dump(s->rx_pkt);
1043
1044 while (bytes_left > 0) {
1045
1046 /* cannot add more frags to packet */
1047 if (num_frags == s->max_rx_frags) {
1048 break;
1049 }
1050
1051 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1052 if (!new_rxcd_pa) {
1053 break;
1054 }
1055
1056 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1057 break;
1058 }
1059
1060 chunk_size = MIN(bytes_left, rxd.len);
1061 vmxnet3_physical_memory_writev(data, bytes_copied,
1062 le64_to_cpu(rxd.addr), chunk_size);
1063 bytes_copied += chunk_size;
1064 bytes_left -= chunk_size;
1065
1066 vmxnet3_dump_rx_descr(&rxd);
1067
1068 if (ready_rxcd_pa != 0) {
1069 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1070 }
1071
1072 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1073 rxcd.rxdIdx = rxd_idx;
1074 rxcd.len = chunk_size;
1075 rxcd.sop = is_head;
1076 rxcd.gen = new_rxcd_gen;
1077 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1078
1079 if (bytes_left == 0) {
1080 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1081 }
1082
1083 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1084 "sop %d csum_correct %lu",
1085 (unsigned long) rx_ridx,
1086 (unsigned long) rxcd.rxdIdx,
1087 (unsigned long) rxcd.len,
1088 (int) rxcd.sop,
1089 (unsigned long) rxcd.tuc);
1090
1091 is_head = false;
1092 ready_rxcd_pa = new_rxcd_pa;
1093 new_rxcd_pa = 0;
1094 num_frags++;
1095 }
1096
1097 if (ready_rxcd_pa != 0) {
1098 rxcd.eop = 1;
1099 rxcd.err = (bytes_left != 0);
1100 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1101
1102 /* Flush RX descriptor changes */
1103 smp_wmb();
1104 }
1105
1106 if (new_rxcd_pa != 0) {
1107 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1108 }
1109
1110 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1111
1112 if (bytes_left == 0) {
1113 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1114 return true;
1115 } else if (num_frags == s->max_rx_frags) {
1116 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1117 return false;
1118 } else {
1119 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1120 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1121 return false;
1122 }
1123 }
1124
1125 static void
1126 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1127 uint64_t val, unsigned size)
1128 {
1129 VMXNET3State *s = opaque;
1130
1131 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1132 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1133 int tx_queue_idx =
1134 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1135 VMXNET3_REG_ALIGN);
1136 assert(tx_queue_idx <= s->txq_num);
1137 vmxnet3_process_tx_queue(s, tx_queue_idx);
1138 return;
1139 }
1140
1141 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1142 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1143 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1144 VMXNET3_REG_ALIGN);
1145
1146 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1147
1148 vmxnet3_on_interrupt_mask_changed(s, l, val);
1149 return;
1150 }
1151
1152 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1153 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1154 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1155 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1156 return;
1157 }
1158
1159 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1160 (uint64_t) addr, val, size);
1161 }
1162
1163 static uint64_t
1164 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1165 {
1166 VMXNET3State *s = opaque;
1167
1168 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1169 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1170 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1171 VMXNET3_REG_ALIGN);
1172 return s->interrupt_states[l].is_masked;
1173 }
1174
1175 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1176 return 0;
1177 }
1178
1179 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1180 {
1181 int i;
1182 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1183 s->interrupt_states[i].is_asserted = false;
1184 s->interrupt_states[i].is_pending = false;
1185 s->interrupt_states[i].is_masked = true;
1186 }
1187 }
1188
1189 static void vmxnet3_reset_mac(VMXNET3State *s)
1190 {
1191 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1192 VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
1193 }
1194
1195 static void vmxnet3_deactivate_device(VMXNET3State *s)
1196 {
1197 if (s->device_active) {
1198 VMW_CBPRN("Deactivating vmxnet3...");
1199 vmxnet_tx_pkt_reset(s->tx_pkt);
1200 vmxnet_tx_pkt_uninit(s->tx_pkt);
1201 vmxnet_rx_pkt_uninit(s->rx_pkt);
1202 s->device_active = false;
1203 }
1204 }
1205
1206 static void vmxnet3_reset(VMXNET3State *s)
1207 {
1208 VMW_CBPRN("Resetting vmxnet3...");
1209
1210 vmxnet3_deactivate_device(s);
1211 vmxnet3_reset_interrupt_states(s);
1212 s->drv_shmem = 0;
1213 s->tx_sop = true;
1214 s->skip_current_tx_pkt = false;
1215 }
1216
1217 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1218 {
1219 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1220 devRead.rxFilterConf.rxMode);
1221 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1222 }
1223
1224 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1225 {
1226 int i;
1227
1228 /* Copy configuration from shared memory */
1229 VMXNET3_READ_DRV_SHARED(s->drv_shmem,
1230 devRead.rxFilterConf.vfTable,
1231 s->vlan_table,
1232 sizeof(s->vlan_table));
1233
1234 /* Invert byte order when needed */
1235 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1236 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1237 }
1238
1239 /* Dump configuration for debugging purposes */
1240 VMW_CFPRN("Configured VLANs:");
1241 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1242 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1243 VMW_CFPRN("\tVLAN %d is present", i);
1244 }
1245 }
1246 }
1247
1248 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1249 {
1250 uint16_t list_bytes =
1251 VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
1252 devRead.rxFilterConf.mfTableLen);
1253
1254 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1255
1256 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1257 if (!s->mcast_list) {
1258 if (s->mcast_list_len == 0) {
1259 VMW_CFPRN("Current multicast list is empty");
1260 } else {
1261 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1262 s->mcast_list_len);
1263 }
1264 s->mcast_list_len = 0;
1265 } else {
1266 int i;
1267 hwaddr mcast_list_pa =
1268 VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
1269 devRead.rxFilterConf.mfTablePA);
1270
1271 cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
1272 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1273 for (i = 0; i < s->mcast_list_len; i++) {
1274 VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
1275 }
1276 }
1277 }
1278
1279 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1280 {
1281 vmxnet3_update_rx_mode(s);
1282 vmxnet3_update_vlan_filters(s);
1283 vmxnet3_update_mcast_filters(s);
1284 }
1285
1286 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1287 {
1288 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1289 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1290 return interrupt_mode;
1291 }
1292
1293 static void vmxnet3_fill_stats(VMXNET3State *s)
1294 {
1295 int i;
1296
1297 if (!s->device_active)
1298 return;
1299
1300 for (i = 0; i < s->txq_num; i++) {
1301 cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
1302 &s->txq_descr[i].txq_stats,
1303 sizeof(s->txq_descr[i].txq_stats));
1304 }
1305
1306 for (i = 0; i < s->rxq_num; i++) {
1307 cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
1308 &s->rxq_descr[i].rxq_stats,
1309 sizeof(s->rxq_descr[i].rxq_stats));
1310 }
1311 }
1312
1313 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1314 {
1315 struct Vmxnet3_GOSInfo gos;
1316
1317 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
1318 &gos, sizeof(gos));
1319 s->rx_packets_compound =
1320 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1321
1322 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1323 }
1324
1325 static void
1326 vmxnet3_dump_conf_descr(const char *name,
1327 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1328 {
1329 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1330 name, pm_descr->confVer, pm_descr->confLen);
1331
1332 };
1333
1334 static void vmxnet3_update_pm_state(VMXNET3State *s)
1335 {
1336 struct Vmxnet3_VariableLenConfDesc pm_descr;
1337
1338 pm_descr.confLen =
1339 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
1340 pm_descr.confVer =
1341 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
1342 pm_descr.confPA =
1343 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
1344
1345 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1346 }
1347
1348 static void vmxnet3_update_features(VMXNET3State *s)
1349 {
1350 uint32_t guest_features;
1351 int rxcso_supported;
1352
1353 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1354 devRead.misc.uptFeatures);
1355
1356 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1357 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1358 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1359
1360 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1361 s->lro_supported, rxcso_supported,
1362 s->rx_vlan_stripping);
1363 if (s->peer_has_vhdr) {
1364 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1365 rxcso_supported,
1366 s->lro_supported,
1367 s->lro_supported,
1368 0,
1369 0);
1370 }
1371 }
1372
1373 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1374 {
1375 return s->msix_used || s->msi_used || (intx ==
1376 (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1));
1377 }
1378
1379 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1380 {
1381 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1382 if (idx >= max_ints) {
1383 hw_error("Bad interrupt index: %d\n", idx);
1384 }
1385 }
1386
1387 static void vmxnet3_validate_interrupts(VMXNET3State *s)
1388 {
1389 int i;
1390
1391 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1392 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1393
1394 for (i = 0; i < s->txq_num; i++) {
1395 int idx = s->txq_descr[i].intr_idx;
1396 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1397 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1398 }
1399
1400 for (i = 0; i < s->rxq_num; i++) {
1401 int idx = s->rxq_descr[i].intr_idx;
1402 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1403 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1404 }
1405 }
1406
1407 static void vmxnet3_validate_queues(VMXNET3State *s)
1408 {
1409 /*
1410 * txq_num and rxq_num are total number of queues
1411 * configured by guest. These numbers must not
1412 * exceed corresponding maximal values.
1413 */
1414
1415 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1416 hw_error("Bad TX queues number: %d\n", s->txq_num);
1417 }
1418
1419 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1420 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1421 }
1422 }
1423
1424 static void vmxnet3_activate_device(VMXNET3State *s)
1425 {
1426 int i;
1427 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1428 hwaddr qdescr_table_pa;
1429 uint64_t pa;
1430 uint32_t size;
1431
1432 /* Verify configuration consistency */
1433 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
1434 VMW_ERPRN("Device configuration received from driver is invalid");
1435 return;
1436 }
1437
1438 /* Verify if device is active */
1439 if (s->device_active) {
1440 VMW_CFPRN("Vmxnet3 device is active");
1441 return;
1442 }
1443
1444 vmxnet3_adjust_by_guest_type(s);
1445 vmxnet3_update_features(s);
1446 vmxnet3_update_pm_state(s);
1447 vmxnet3_setup_rx_filtering(s);
1448 /* Cache fields from shared memory */
1449 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
1450 VMW_CFPRN("MTU is %u", s->mtu);
1451
1452 s->max_rx_frags =
1453 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
1454
1455 if (s->max_rx_frags == 0) {
1456 s->max_rx_frags = 1;
1457 }
1458
1459 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1460
1461 s->event_int_idx =
1462 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
1463 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1464 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1465
1466 s->auto_int_masking =
1467 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
1468 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1469
1470 s->txq_num =
1471 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
1472 s->rxq_num =
1473 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
1474
1475 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1476 vmxnet3_validate_queues(s);
1477
1478 qdescr_table_pa =
1479 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
1480 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1481
1482 /*
1483 * Worst-case scenario is a packet that holds all TX rings space so
1484 * we calculate total size of all TX rings for max TX fragments number
1485 */
1486 s->max_tx_frags = 0;
1487
1488 /* TX queues */
1489 for (i = 0; i < s->txq_num; i++) {
1490 hwaddr qdescr_pa =
1491 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1492
1493 /* Read interrupt number for this TX queue */
1494 s->txq_descr[i].intr_idx =
1495 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
1496 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1497
1498 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1499
1500 /* Read rings memory locations for TX queues */
1501 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
1502 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
1503
1504 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
1505 sizeof(struct Vmxnet3_TxDesc), false);
1506 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1507
1508 s->max_tx_frags += size;
1509
1510 /* TXC ring */
1511 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
1512 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
1513 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
1514 sizeof(struct Vmxnet3_TxCompDesc), true);
1515 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1516
1517 s->txq_descr[i].tx_stats_pa =
1518 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1519
1520 memset(&s->txq_descr[i].txq_stats, 0,
1521 sizeof(s->txq_descr[i].txq_stats));
1522
1523 /* Fill device-managed parameters for queues */
1524 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
1525 ctrl.txThreshold,
1526 VMXNET3_DEF_TX_THRESHOLD);
1527 }
1528
1529 /* Preallocate TX packet wrapper */
1530 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1531 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
1532 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1533
1534 /* Read rings memory locations for RX queues */
1535 for (i = 0; i < s->rxq_num; i++) {
1536 int j;
1537 hwaddr qd_pa =
1538 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1539 i * sizeof(struct Vmxnet3_RxQueueDesc);
1540
1541 /* Read interrupt number for this RX queue */
1542 s->rxq_descr[i].intr_idx =
1543 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
1544 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1545
1546 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1547
1548 /* Read rings memory locations */
1549 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1550 /* RX rings */
1551 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
1552 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
1553 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
1554 sizeof(struct Vmxnet3_RxDesc), false);
1555 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1556 i, j, pa, size);
1557 }
1558
1559 /* RXC ring */
1560 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
1561 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
1562 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
1563 sizeof(struct Vmxnet3_RxCompDesc), true);
1564 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1565
1566 s->rxq_descr[i].rx_stats_pa =
1567 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1568 memset(&s->rxq_descr[i].rxq_stats, 0,
1569 sizeof(s->rxq_descr[i].rxq_stats));
1570 }
1571
1572 vmxnet3_validate_interrupts(s);
1573
1574 /* Make sure everything is in place before device activation */
1575 smp_wmb();
1576
1577 vmxnet3_reset_mac(s);
1578
1579 s->device_active = true;
1580 }
1581
1582 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1583 {
1584 s->last_command = cmd;
1585
1586 switch (cmd) {
1587 case VMXNET3_CMD_GET_PERM_MAC_HI:
1588 VMW_CBPRN("Set: Get upper part of permanent MAC");
1589 break;
1590
1591 case VMXNET3_CMD_GET_PERM_MAC_LO:
1592 VMW_CBPRN("Set: Get lower part of permanent MAC");
1593 break;
1594
1595 case VMXNET3_CMD_GET_STATS:
1596 VMW_CBPRN("Set: Get device statistics");
1597 vmxnet3_fill_stats(s);
1598 break;
1599
1600 case VMXNET3_CMD_ACTIVATE_DEV:
1601 VMW_CBPRN("Set: Activating vmxnet3 device");
1602 vmxnet3_activate_device(s);
1603 break;
1604
1605 case VMXNET3_CMD_UPDATE_RX_MODE:
1606 VMW_CBPRN("Set: Update rx mode");
1607 vmxnet3_update_rx_mode(s);
1608 break;
1609
1610 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1611 VMW_CBPRN("Set: Update VLAN filters");
1612 vmxnet3_update_vlan_filters(s);
1613 break;
1614
1615 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1616 VMW_CBPRN("Set: Update MAC filters");
1617 vmxnet3_update_mcast_filters(s);
1618 break;
1619
1620 case VMXNET3_CMD_UPDATE_FEATURE:
1621 VMW_CBPRN("Set: Update features");
1622 vmxnet3_update_features(s);
1623 break;
1624
1625 case VMXNET3_CMD_UPDATE_PMCFG:
1626 VMW_CBPRN("Set: Update power management config");
1627 vmxnet3_update_pm_state(s);
1628 break;
1629
1630 case VMXNET3_CMD_GET_LINK:
1631 VMW_CBPRN("Set: Get link");
1632 break;
1633
1634 case VMXNET3_CMD_RESET_DEV:
1635 VMW_CBPRN("Set: Reset device");
1636 vmxnet3_reset(s);
1637 break;
1638
1639 case VMXNET3_CMD_QUIESCE_DEV:
1640 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1641 vmxnet3_deactivate_device(s);
1642 break;
1643
1644 case VMXNET3_CMD_GET_CONF_INTR:
1645 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1646 break;
1647
1648 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1649 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1650 "adaptive ring info flags");
1651 break;
1652
1653 case VMXNET3_CMD_GET_DID_LO:
1654 VMW_CBPRN("Set: Get lower part of device ID");
1655 break;
1656
1657 case VMXNET3_CMD_GET_DID_HI:
1658 VMW_CBPRN("Set: Get upper part of device ID");
1659 break;
1660
1661 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1662 VMW_CBPRN("Set: Get device extra info");
1663 break;
1664
1665 default:
1666 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1667 break;
1668 }
1669 }
1670
1671 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1672 {
1673 uint64_t ret;
1674
1675 switch (s->last_command) {
1676 case VMXNET3_CMD_ACTIVATE_DEV:
1677 ret = (s->device_active) ? 0 : 1;
1678 VMW_CFPRN("Device active: %" PRIx64, ret);
1679 break;
1680
1681 case VMXNET3_CMD_RESET_DEV:
1682 case VMXNET3_CMD_QUIESCE_DEV:
1683 case VMXNET3_CMD_GET_QUEUE_STATUS:
1684 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1685 ret = 0;
1686 break;
1687
1688 case VMXNET3_CMD_GET_LINK:
1689 ret = s->link_status_and_speed;
1690 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1691 break;
1692
1693 case VMXNET3_CMD_GET_PERM_MAC_LO:
1694 ret = vmxnet3_get_mac_low(&s->perm_mac);
1695 break;
1696
1697 case VMXNET3_CMD_GET_PERM_MAC_HI:
1698 ret = vmxnet3_get_mac_high(&s->perm_mac);
1699 break;
1700
1701 case VMXNET3_CMD_GET_CONF_INTR:
1702 ret = vmxnet3_get_interrupt_config(s);
1703 break;
1704
1705 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1706 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1707 break;
1708
1709 case VMXNET3_CMD_GET_DID_LO:
1710 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1711 break;
1712
1713 case VMXNET3_CMD_GET_DID_HI:
1714 ret = VMXNET3_DEVICE_REVISION;
1715 break;
1716
1717 default:
1718 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1719 ret = 0;
1720 break;
1721 }
1722
1723 return ret;
1724 }
1725
1726 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1727 {
1728 uint32_t events;
1729
1730 VMW_CBPRN("Setting events: 0x%x", val);
1731 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
1732 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1733 }
1734
1735 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1736 {
1737 uint32_t events;
1738
1739 VMW_CBPRN("Clearing events: 0x%x", val);
1740 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
1741 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1742 }
1743
1744 static void
1745 vmxnet3_io_bar1_write(void *opaque,
1746 hwaddr addr,
1747 uint64_t val,
1748 unsigned size)
1749 {
1750 VMXNET3State *s = opaque;
1751
1752 switch (addr) {
1753 /* Vmxnet3 Revision Report Selection */
1754 case VMXNET3_REG_VRRS:
1755 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1756 val, size);
1757 break;
1758
1759 /* UPT Version Report Selection */
1760 case VMXNET3_REG_UVRS:
1761 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1762 val, size);
1763 break;
1764
1765 /* Driver Shared Address Low */
1766 case VMXNET3_REG_DSAL:
1767 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1768 val, size);
1769 /*
1770 * Guest driver will first write the low part of the shared
1771 * memory address. We save it to temp variable and set the
1772 * shared address only after we get the high part
1773 */
1774 if (val == 0) {
1775 vmxnet3_deactivate_device(s);
1776 }
1777 s->temp_shared_guest_driver_memory = val;
1778 s->drv_shmem = 0;
1779 break;
1780
1781 /* Driver Shared Address High */
1782 case VMXNET3_REG_DSAH:
1783 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1784 val, size);
1785 /*
1786 * Set the shared memory between guest driver and device.
1787 * We already should have low address part.
1788 */
1789 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1790 break;
1791
1792 /* Command */
1793 case VMXNET3_REG_CMD:
1794 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1795 val, size);
1796 vmxnet3_handle_command(s, val);
1797 break;
1798
1799 /* MAC Address Low */
1800 case VMXNET3_REG_MACL:
1801 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1802 val, size);
1803 s->temp_mac = val;
1804 break;
1805
1806 /* MAC Address High */
1807 case VMXNET3_REG_MACH:
1808 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1809 val, size);
1810 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1811 break;
1812
1813 /* Interrupt Cause Register */
1814 case VMXNET3_REG_ICR:
1815 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1816 val, size);
1817 g_assert_not_reached();
1818 break;
1819
1820 /* Event Cause Register */
1821 case VMXNET3_REG_ECR:
1822 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1823 val, size);
1824 vmxnet3_ack_events(s, val);
1825 break;
1826
1827 default:
1828 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1829 addr, val, size);
1830 break;
1831 }
1832 }
1833
1834 static uint64_t
1835 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1836 {
1837 VMXNET3State *s = opaque;
1838 uint64_t ret = 0;
1839
1840 switch (addr) {
1841 /* Vmxnet3 Revision Report Selection */
1842 case VMXNET3_REG_VRRS:
1843 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1844 ret = VMXNET3_DEVICE_REVISION;
1845 break;
1846
1847 /* UPT Version Report Selection */
1848 case VMXNET3_REG_UVRS:
1849 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1850 ret = VMXNET3_UPT_REVISION;
1851 break;
1852
1853 /* Command */
1854 case VMXNET3_REG_CMD:
1855 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1856 ret = vmxnet3_get_command_status(s);
1857 break;
1858
1859 /* MAC Address Low */
1860 case VMXNET3_REG_MACL:
1861 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1862 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1863 break;
1864
1865 /* MAC Address High */
1866 case VMXNET3_REG_MACH:
1867 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1868 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1869 break;
1870
1871 /*
1872 * Interrupt Cause Register
1873 * Used for legacy interrupts only so interrupt index always 0
1874 */
1875 case VMXNET3_REG_ICR:
1876 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1877 if (vmxnet3_interrupt_asserted(s, 0)) {
1878 vmxnet3_clear_interrupt(s, 0);
1879 ret = true;
1880 } else {
1881 ret = false;
1882 }
1883 break;
1884
1885 default:
1886 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1887 break;
1888 }
1889
1890 return ret;
1891 }
1892
1893 static int
1894 vmxnet3_can_receive(NetClientState *nc)
1895 {
1896 VMXNET3State *s = qemu_get_nic_opaque(nc);
1897 return s->device_active &&
1898 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1899 }
1900
1901 static inline bool
1902 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1903 {
1904 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1905 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1906 return true;
1907 }
1908
1909 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1910 }
1911
1912 static bool
1913 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1914 {
1915 int i;
1916 for (i = 0; i < s->mcast_list_len; i++) {
1917 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1918 return true;
1919 }
1920 }
1921 return false;
1922 }
1923
1924 static bool
1925 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1926 size_t size)
1927 {
1928 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1929
1930 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1931 return true;
1932 }
1933
1934 if (!vmxnet3_is_registered_vlan(s, data)) {
1935 return false;
1936 }
1937
1938 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
1939 case ETH_PKT_UCAST:
1940 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1941 return false;
1942 }
1943 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1944 return false;
1945 }
1946 break;
1947
1948 case ETH_PKT_BCAST:
1949 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1950 return false;
1951 }
1952 break;
1953
1954 case ETH_PKT_MCAST:
1955 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1956 return true;
1957 }
1958 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1959 return false;
1960 }
1961 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1962 return false;
1963 }
1964 break;
1965
1966 default:
1967 g_assert_not_reached();
1968 }
1969
1970 return true;
1971 }
1972
1973 static ssize_t
1974 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1975 {
1976 VMXNET3State *s = qemu_get_nic_opaque(nc);
1977 size_t bytes_indicated;
1978 uint8_t min_buf[MIN_BUF_SIZE];
1979
1980 if (!vmxnet3_can_receive(nc)) {
1981 VMW_PKPRN("Cannot receive now");
1982 return -1;
1983 }
1984
1985 if (s->peer_has_vhdr) {
1986 vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1987 buf += sizeof(struct virtio_net_hdr);
1988 size -= sizeof(struct virtio_net_hdr);
1989 }
1990
1991 /* Pad to minimum Ethernet frame length */
1992 if (size < sizeof(min_buf)) {
1993 memcpy(min_buf, buf, size);
1994 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1995 buf = min_buf;
1996 size = sizeof(min_buf);
1997 }
1998
1999 vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
2000 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
2001
2002 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
2003 vmxnet_rx_pkt_set_protocols(s->rx_pkt, buf, size);
2004 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
2005 vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
2006 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2007 if (bytes_indicated < size) {
2008 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
2009 }
2010 } else {
2011 VMW_PKPRN("Packet dropped by RX filter");
2012 bytes_indicated = size;
2013 }
2014
2015 assert(size > 0);
2016 assert(bytes_indicated != 0);
2017 return bytes_indicated;
2018 }
2019
2020 static void vmxnet3_set_link_status(NetClientState *nc)
2021 {
2022 VMXNET3State *s = qemu_get_nic_opaque(nc);
2023
2024 if (nc->link_down) {
2025 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2026 } else {
2027 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2028 }
2029
2030 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2031 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2032 }
2033
2034 static NetClientInfo net_vmxnet3_info = {
2035 .type = NET_CLIENT_OPTIONS_KIND_NIC,
2036 .size = sizeof(NICState),
2037 .receive = vmxnet3_receive,
2038 .link_status_changed = vmxnet3_set_link_status,
2039 };
2040
2041 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2042 {
2043 NetClientState *nc = qemu_get_queue(s->nic);
2044
2045 if (qemu_has_vnet_hdr(nc->peer)) {
2046 return true;
2047 }
2048
2049 return false;
2050 }
2051
2052 static void vmxnet3_net_uninit(VMXNET3State *s)
2053 {
2054 g_free(s->mcast_list);
2055 vmxnet3_deactivate_device(s);
2056 qemu_del_nic(s->nic);
2057 }
2058
2059 static void vmxnet3_net_init(VMXNET3State *s)
2060 {
2061 DeviceState *d = DEVICE(s);
2062
2063 VMW_CBPRN("vmxnet3_net_init called...");
2064
2065 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2066
2067 /* Windows guest will query the address that was set on init */
2068 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2069
2070 s->mcast_list = NULL;
2071 s->mcast_list_len = 0;
2072
2073 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2074
2075 VMW_CFPRN("Permanent MAC: " VMXNET_MF, VMXNET_MA(s->perm_mac.a));
2076
2077 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2078 object_get_typename(OBJECT(s)),
2079 d->id, s);
2080
2081 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2082 s->tx_sop = true;
2083 s->skip_current_tx_pkt = false;
2084 s->tx_pkt = NULL;
2085 s->rx_pkt = NULL;
2086 s->rx_vlan_stripping = false;
2087 s->lro_supported = false;
2088
2089 if (s->peer_has_vhdr) {
2090 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2091 sizeof(struct virtio_net_hdr));
2092
2093 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
2094 }
2095
2096 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2097 }
2098
2099 static void
2100 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2101 {
2102 PCIDevice *d = PCI_DEVICE(s);
2103 int i;
2104 for (i = 0; i < num_vectors; i++) {
2105 msix_vector_unuse(d, i);
2106 }
2107 }
2108
2109 static bool
2110 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2111 {
2112 PCIDevice *d = PCI_DEVICE(s);
2113 int i;
2114 for (i = 0; i < num_vectors; i++) {
2115 int res = msix_vector_use(d, i);
2116 if (0 > res) {
2117 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2118 vmxnet3_unuse_msix_vectors(s, i);
2119 return false;
2120 }
2121 }
2122 return true;
2123 }
2124
2125 static bool
2126 vmxnet3_init_msix(VMXNET3State *s)
2127 {
2128 PCIDevice *d = PCI_DEVICE(s);
2129 int res = msix_init(d, VMXNET3_MAX_INTRS,
2130 &s->msix_bar,
2131 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2132 &s->msix_bar,
2133 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
2134 0);
2135
2136 if (0 > res) {
2137 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2138 s->msix_used = false;
2139 } else {
2140 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2141 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2142 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2143 s->msix_used = false;
2144 } else {
2145 s->msix_used = true;
2146 }
2147 }
2148 return s->msix_used;
2149 }
2150
2151 static void
2152 vmxnet3_cleanup_msix(VMXNET3State *s)
2153 {
2154 PCIDevice *d = PCI_DEVICE(s);
2155
2156 if (s->msix_used) {
2157 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2158 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2159 }
2160 }
2161
2162 #define VMXNET3_MSI_OFFSET (0x50)
2163 #define VMXNET3_USE_64BIT (true)
2164 #define VMXNET3_PER_VECTOR_MASK (false)
2165
2166 static bool
2167 vmxnet3_init_msi(VMXNET3State *s)
2168 {
2169 PCIDevice *d = PCI_DEVICE(s);
2170 int res;
2171
2172 res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
2173 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
2174 if (0 > res) {
2175 VMW_WRPRN("Failed to initialize MSI, error %d", res);
2176 s->msi_used = false;
2177 } else {
2178 s->msi_used = true;
2179 }
2180
2181 return s->msi_used;
2182 }
2183
2184 static void
2185 vmxnet3_cleanup_msi(VMXNET3State *s)
2186 {
2187 PCIDevice *d = PCI_DEVICE(s);
2188
2189 if (s->msi_used) {
2190 msi_uninit(d);
2191 }
2192 }
2193
2194 static void
2195 vmxnet3_msix_save(QEMUFile *f, void *opaque)
2196 {
2197 PCIDevice *d = PCI_DEVICE(opaque);
2198 msix_save(d, f);
2199 }
2200
2201 static int
2202 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2203 {
2204 PCIDevice *d = PCI_DEVICE(opaque);
2205 msix_load(d, f);
2206 return 0;
2207 }
2208
2209 static const MemoryRegionOps b0_ops = {
2210 .read = vmxnet3_io_bar0_read,
2211 .write = vmxnet3_io_bar0_write,
2212 .endianness = DEVICE_LITTLE_ENDIAN,
2213 .impl = {
2214 .min_access_size = 4,
2215 .max_access_size = 4,
2216 },
2217 };
2218
2219 static const MemoryRegionOps b1_ops = {
2220 .read = vmxnet3_io_bar1_read,
2221 .write = vmxnet3_io_bar1_write,
2222 .endianness = DEVICE_LITTLE_ENDIAN,
2223 .impl = {
2224 .min_access_size = 4,
2225 .max_access_size = 4,
2226 },
2227 };
2228
2229 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2230 {
2231 DeviceState *dev = DEVICE(pci_dev);
2232 VMXNET3State *s = VMXNET3(pci_dev);
2233
2234 VMW_CBPRN("Starting init...");
2235
2236 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2237 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2238 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2239 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2240
2241 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2242 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2243 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2244 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2245
2246 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2247 VMXNET3_MSIX_BAR_SIZE);
2248 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2249 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2250
2251 vmxnet3_reset_interrupt_states(s);
2252
2253 /* Interrupt pin A */
2254 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2255
2256 if (!vmxnet3_init_msix(s)) {
2257 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2258 }
2259
2260 if (!vmxnet3_init_msi(s)) {
2261 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2262 }
2263
2264 vmxnet3_net_init(s);
2265
2266 register_savevm(dev, "vmxnet3-msix", -1, 1,
2267 vmxnet3_msix_save, vmxnet3_msix_load, s);
2268 }
2269
2270 static void vmxnet3_instance_init(Object *obj)
2271 {
2272 VMXNET3State *s = VMXNET3(obj);
2273 device_add_bootindex_property(obj, &s->conf.bootindex,
2274 "bootindex", "/ethernet-phy@0",
2275 DEVICE(obj), NULL);
2276 }
2277
2278 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2279 {
2280 DeviceState *dev = DEVICE(pci_dev);
2281 VMXNET3State *s = VMXNET3(pci_dev);
2282
2283 VMW_CBPRN("Starting uninit...");
2284
2285 unregister_savevm(dev, "vmxnet3-msix", s);
2286
2287 vmxnet3_net_uninit(s);
2288
2289 vmxnet3_cleanup_msix(s);
2290
2291 vmxnet3_cleanup_msi(s);
2292 }
2293
2294 static void vmxnet3_qdev_reset(DeviceState *dev)
2295 {
2296 PCIDevice *d = PCI_DEVICE(dev);
2297 VMXNET3State *s = VMXNET3(d);
2298
2299 VMW_CBPRN("Starting QDEV reset...");
2300 vmxnet3_reset(s);
2301 }
2302
2303 static bool vmxnet3_mc_list_needed(void *opaque)
2304 {
2305 return true;
2306 }
2307
2308 static int vmxnet3_mcast_list_pre_load(void *opaque)
2309 {
2310 VMXNET3State *s = opaque;
2311
2312 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2313
2314 return 0;
2315 }
2316
2317
2318 static void vmxnet3_pre_save(void *opaque)
2319 {
2320 VMXNET3State *s = opaque;
2321
2322 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2323 }
2324
2325 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2326 .name = "vmxnet3/mcast_list",
2327 .version_id = 1,
2328 .minimum_version_id = 1,
2329 .pre_load = vmxnet3_mcast_list_pre_load,
2330 .needed = vmxnet3_mc_list_needed,
2331 .fields = (VMStateField[]) {
2332 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
2333 mcast_list_buff_size),
2334 VMSTATE_END_OF_LIST()
2335 }
2336 };
2337
2338 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
2339 {
2340 r->pa = qemu_get_be64(f);
2341 r->size = qemu_get_be32(f);
2342 r->cell_size = qemu_get_be32(f);
2343 r->next = qemu_get_be32(f);
2344 r->gen = qemu_get_byte(f);
2345 }
2346
2347 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
2348 {
2349 qemu_put_be64(f, r->pa);
2350 qemu_put_be32(f, r->size);
2351 qemu_put_be32(f, r->cell_size);
2352 qemu_put_be32(f, r->next);
2353 qemu_put_byte(f, r->gen);
2354 }
2355
2356 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
2357 struct UPT1_TxStats *tx_stat)
2358 {
2359 tx_stat->TSOPktsTxOK = qemu_get_be64(f);
2360 tx_stat->TSOBytesTxOK = qemu_get_be64(f);
2361 tx_stat->ucastPktsTxOK = qemu_get_be64(f);
2362 tx_stat->ucastBytesTxOK = qemu_get_be64(f);
2363 tx_stat->mcastPktsTxOK = qemu_get_be64(f);
2364 tx_stat->mcastBytesTxOK = qemu_get_be64(f);
2365 tx_stat->bcastPktsTxOK = qemu_get_be64(f);
2366 tx_stat->bcastBytesTxOK = qemu_get_be64(f);
2367 tx_stat->pktsTxError = qemu_get_be64(f);
2368 tx_stat->pktsTxDiscard = qemu_get_be64(f);
2369 }
2370
2371 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
2372 struct UPT1_TxStats *tx_stat)
2373 {
2374 qemu_put_be64(f, tx_stat->TSOPktsTxOK);
2375 qemu_put_be64(f, tx_stat->TSOBytesTxOK);
2376 qemu_put_be64(f, tx_stat->ucastPktsTxOK);
2377 qemu_put_be64(f, tx_stat->ucastBytesTxOK);
2378 qemu_put_be64(f, tx_stat->mcastPktsTxOK);
2379 qemu_put_be64(f, tx_stat->mcastBytesTxOK);
2380 qemu_put_be64(f, tx_stat->bcastPktsTxOK);
2381 qemu_put_be64(f, tx_stat->bcastBytesTxOK);
2382 qemu_put_be64(f, tx_stat->pktsTxError);
2383 qemu_put_be64(f, tx_stat->pktsTxDiscard);
2384 }
2385
2386 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
2387 {
2388 Vmxnet3TxqDescr *r = pv;
2389
2390 vmxnet3_get_ring_from_file(f, &r->tx_ring);
2391 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2392 r->intr_idx = qemu_get_byte(f);
2393 r->tx_stats_pa = qemu_get_be64(f);
2394
2395 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
2396
2397 return 0;
2398 }
2399
2400 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
2401 {
2402 Vmxnet3TxqDescr *r = pv;
2403
2404 vmxnet3_put_ring_to_file(f, &r->tx_ring);
2405 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2406 qemu_put_byte(f, r->intr_idx);
2407 qemu_put_be64(f, r->tx_stats_pa);
2408 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
2409 }
2410
2411 static const VMStateInfo txq_descr_info = {
2412 .name = "txq_descr",
2413 .get = vmxnet3_get_txq_descr,
2414 .put = vmxnet3_put_txq_descr
2415 };
2416
2417 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
2418 struct UPT1_RxStats *rx_stat)
2419 {
2420 rx_stat->LROPktsRxOK = qemu_get_be64(f);
2421 rx_stat->LROBytesRxOK = qemu_get_be64(f);
2422 rx_stat->ucastPktsRxOK = qemu_get_be64(f);
2423 rx_stat->ucastBytesRxOK = qemu_get_be64(f);
2424 rx_stat->mcastPktsRxOK = qemu_get_be64(f);
2425 rx_stat->mcastBytesRxOK = qemu_get_be64(f);
2426 rx_stat->bcastPktsRxOK = qemu_get_be64(f);
2427 rx_stat->bcastBytesRxOK = qemu_get_be64(f);
2428 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
2429 rx_stat->pktsRxError = qemu_get_be64(f);
2430 }
2431
2432 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
2433 struct UPT1_RxStats *rx_stat)
2434 {
2435 qemu_put_be64(f, rx_stat->LROPktsRxOK);
2436 qemu_put_be64(f, rx_stat->LROBytesRxOK);
2437 qemu_put_be64(f, rx_stat->ucastPktsRxOK);
2438 qemu_put_be64(f, rx_stat->ucastBytesRxOK);
2439 qemu_put_be64(f, rx_stat->mcastPktsRxOK);
2440 qemu_put_be64(f, rx_stat->mcastBytesRxOK);
2441 qemu_put_be64(f, rx_stat->bcastPktsRxOK);
2442 qemu_put_be64(f, rx_stat->bcastBytesRxOK);
2443 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
2444 qemu_put_be64(f, rx_stat->pktsRxError);
2445 }
2446
2447 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
2448 {
2449 Vmxnet3RxqDescr *r = pv;
2450 int i;
2451
2452 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2453 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
2454 }
2455
2456 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2457 r->intr_idx = qemu_get_byte(f);
2458 r->rx_stats_pa = qemu_get_be64(f);
2459
2460 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
2461
2462 return 0;
2463 }
2464
2465 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
2466 {
2467 Vmxnet3RxqDescr *r = pv;
2468 int i;
2469
2470 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2471 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
2472 }
2473
2474 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2475 qemu_put_byte(f, r->intr_idx);
2476 qemu_put_be64(f, r->rx_stats_pa);
2477 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
2478 }
2479
2480 static int vmxnet3_post_load(void *opaque, int version_id)
2481 {
2482 VMXNET3State *s = opaque;
2483 PCIDevice *d = PCI_DEVICE(s);
2484
2485 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
2486 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2487
2488 if (s->msix_used) {
2489 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2490 VMW_WRPRN("Failed to re-use MSI-X vectors");
2491 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2492 s->msix_used = false;
2493 return -1;
2494 }
2495 }
2496
2497 vmxnet3_validate_queues(s);
2498 vmxnet3_validate_interrupts(s);
2499
2500 return 0;
2501 }
2502
2503 static const VMStateInfo rxq_descr_info = {
2504 .name = "rxq_descr",
2505 .get = vmxnet3_get_rxq_descr,
2506 .put = vmxnet3_put_rxq_descr
2507 };
2508
2509 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
2510 {
2511 Vmxnet3IntState *r = pv;
2512
2513 r->is_masked = qemu_get_byte(f);
2514 r->is_pending = qemu_get_byte(f);
2515 r->is_asserted = qemu_get_byte(f);
2516
2517 return 0;
2518 }
2519
2520 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
2521 {
2522 Vmxnet3IntState *r = pv;
2523
2524 qemu_put_byte(f, r->is_masked);
2525 qemu_put_byte(f, r->is_pending);
2526 qemu_put_byte(f, r->is_asserted);
2527 }
2528
2529 static const VMStateInfo int_state_info = {
2530 .name = "int_state",
2531 .get = vmxnet3_get_int_state,
2532 .put = vmxnet3_put_int_state
2533 };
2534
2535 static const VMStateDescription vmstate_vmxnet3 = {
2536 .name = "vmxnet3",
2537 .version_id = 1,
2538 .minimum_version_id = 1,
2539 .pre_save = vmxnet3_pre_save,
2540 .post_load = vmxnet3_post_load,
2541 .fields = (VMStateField[]) {
2542 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2543 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2544 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2545 VMSTATE_BOOL(lro_supported, VMXNET3State),
2546 VMSTATE_UINT32(rx_mode, VMXNET3State),
2547 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2548 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2549 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2550 VMSTATE_UINT32(mtu, VMXNET3State),
2551 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2552 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2553 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2554 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2555 VMSTATE_UINT8(txq_num, VMXNET3State),
2556 VMSTATE_UINT8(rxq_num, VMXNET3State),
2557 VMSTATE_UINT32(device_active, VMXNET3State),
2558 VMSTATE_UINT32(last_command, VMXNET3State),
2559 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2560 VMSTATE_UINT32(temp_mac, VMXNET3State),
2561 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2562 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2563
2564 VMSTATE_ARRAY(txq_descr, VMXNET3State,
2565 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
2566 Vmxnet3TxqDescr),
2567 VMSTATE_ARRAY(rxq_descr, VMXNET3State,
2568 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
2569 Vmxnet3RxqDescr),
2570 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
2571 0, int_state_info, Vmxnet3IntState),
2572
2573 VMSTATE_END_OF_LIST()
2574 },
2575 .subsections = (const VMStateDescription*[]) {
2576 &vmxstate_vmxnet3_mcast_list,
2577 NULL
2578 }
2579 };
2580
2581 static Property vmxnet3_properties[] = {
2582 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2583 DEFINE_PROP_END_OF_LIST(),
2584 };
2585
2586 static void vmxnet3_class_init(ObjectClass *class, void *data)
2587 {
2588 DeviceClass *dc = DEVICE_CLASS(class);
2589 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2590
2591 c->realize = vmxnet3_pci_realize;
2592 c->exit = vmxnet3_pci_uninit;
2593 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2594 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2595 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2596 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2597 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2598 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2599 dc->desc = "VMWare Paravirtualized Ethernet v3";
2600 dc->reset = vmxnet3_qdev_reset;
2601 dc->vmsd = &vmstate_vmxnet3;
2602 dc->props = vmxnet3_properties;
2603 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2604 }
2605
2606 static const TypeInfo vmxnet3_info = {
2607 .name = TYPE_VMXNET3,
2608 .parent = TYPE_PCI_DEVICE,
2609 .instance_size = sizeof(VMXNET3State),
2610 .class_init = vmxnet3_class_init,
2611 .instance_init = vmxnet3_instance_init,
2612 };
2613
2614 static void vmxnet3_register_types(void)
2615 {
2616 VMW_CBPRN("vmxnet3_register_types called...");
2617 type_register_static(&vmxnet3_info);
2618 }
2619
2620 type_init(vmxnet3_register_types)
AR7 emulation for QEMU