target/i386: Use X86Seg enum for segment registers
[qemu/ar7.git] / tests / tcg / alpha / test-cond.c
blob3e11c4c10516c1b5e424e1eb4dfe8bb703533bb8
1 #include <unistd.h>
3 #ifdef TEST_CMOV
5 #define TEST_COND(N) \
6 int test_##N (long a) \
7 { \
8 int res = 1; \
10 asm ("cmov"#N" %1,$31,%0" \
11 : "+r" (res) : "r" (a)); \
12 return !res; \
15 #else
17 #define TEST_COND(N) \
18 int test_##N (long a) \
19 { \
20 int res = 1; \
22 asm ("b"#N" %1,1f\n\t" \
23 "addq $31,$31,%0\n\t" \
24 "1: unop\n" \
25 : "+r" (res) : "r" (a)); \
26 return res; \
29 #endif
31 TEST_COND(eq)
32 TEST_COND(ne)
33 TEST_COND(ge)
34 TEST_COND(gt)
35 TEST_COND(lbc)
36 TEST_COND(lbs)
37 TEST_COND(le)
38 TEST_COND(lt)
40 static struct {
41 int (*func)(long);
42 long v;
43 int r;
44 } vectors[] =
46 {test_eq, 0, 1},
47 {test_eq, 1, 0},
49 {test_ne, 0, 0},
50 {test_ne, 1, 1},
52 {test_ge, 0, 1},
53 {test_ge, 1, 1},
54 {test_ge, -1, 0},
56 {test_gt, 0, 0},
57 {test_gt, 1, 1},
58 {test_gt, -1, 0},
60 {test_lbc, 0, 1},
61 {test_lbc, 1, 0},
62 {test_lbc, -1, 0},
64 {test_lbs, 0, 0},
65 {test_lbs, 1, 1},
66 {test_lbs, -1, 1},
68 {test_le, 0, 1},
69 {test_le, 1, 0},
70 {test_le, -1, 1},
72 {test_lt, 0, 0},
73 {test_lt, 1, 0},
74 {test_lt, -1, 1},
77 int main (void)
79 int i;
81 for (i = 0; i < sizeof (vectors)/sizeof(vectors[0]); i++)
82 if ((*vectors[i].func)(vectors[i].v) != vectors[i].r) {
83 write(1, "Failed\n", 7);
84 return 1;
86 write(1, "OK\n", 3);
87 return 0;