include/hw/pci-host/designware.h

   1 /*
   2  * Copyright (c) 2017, Impinj, Inc.
   3  *
   4  * Designware PCIe IP block emulation
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef DESIGNWARE_H
  22 #define DESIGNWARE_H
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/pci/pci_bus.h"
  27 #include "hw/pci/pcie_host.h"
  28 #include "hw/pci/pci_bridge.h"
  29 #include "qom/object.h"
  30
  31 #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
  32 OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
  33
  34 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
  35 OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
  36
  37 struct DesignwarePCIERoot;
  38
  39 typedef struct DesignwarePCIEViewport {
  40     DesignwarePCIERoot *root;
  41
  42     MemoryRegion cfg;
  43     MemoryRegion mem;
  44
  45     uint64_t base;
  46     uint64_t target;
  47     uint32_t limit;
  48     uint32_t cr[2];
  49
  50     bool inbound;
  51 } DesignwarePCIEViewport;
  52
  53 typedef struct DesignwarePCIEMSIBank {
  54     uint32_t enable;
  55     uint32_t mask;
  56     uint32_t status;
  57 } DesignwarePCIEMSIBank;
  58
  59 typedef struct DesignwarePCIEMSI {
  60     uint64_t     base;
  61     MemoryRegion iomem;
  62
  63 #define DESIGNWARE_PCIE_NUM_MSI_BANKS        1
  64
  65     DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
  66 } DesignwarePCIEMSI;
  67
  68 struct DesignwarePCIERoot {
  69     PCIBridge parent_obj;
  70
  71     uint32_t atu_viewport;
  72
  73 #define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
  74 #define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
  75 #define DESIGNWARE_PCIE_NUM_VIEWPORTS        4
  76
  77     DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
  78     DesignwarePCIEMSI msi;
  79 };
  80
  81 struct DesignwarePCIEHost {
  82     PCIHostState parent_obj;
  83
  84     DesignwarePCIERoot root;
  85
  86     struct {
  87         AddressSpace address_space;
  88         MemoryRegion address_space_root;
  89
  90         MemoryRegion memory;
  91         MemoryRegion io;
  92
  93         qemu_irq     irqs[4];
  94     } pci;
  95
  96     MemoryRegion mmio;
  97 };
  98
  99 #endif /* DESIGNWARE_H */