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dma: rc4030: limit interval timer reload value
[qemu/ar7.git] / tcg / ppc / tcg-target.inc.c
blob64f67d2c7723b28bff9d5cdf3719e976d48b69ff
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 #if defined _CALL_DARWIN || defined __APPLE__
28 #define TCG_TARGET_CALL_DARWIN
29 #endif
30 #ifdef _CALL_SYSV
31 # define TCG_TARGET_CALL_ALIGN_ARGS 1
32 #endif
33
34 /* For some memory operations, we need a scratch that isn't R0. For the AIX
35 calling convention, we can re-use the TOC register since we'll be reloading
36 it at every call. Otherwise R12 will do nicely as neither a call-saved
37 register nor a parameter register. */
38 #ifdef _CALL_AIX
39 # define TCG_REG_TMP1 TCG_REG_R2
40 #else
41 # define TCG_REG_TMP1 TCG_REG_R12
42 #endif
43
44 /* For the 64-bit target, we don't like the 5 insn sequence needed to build
45 full 64-bit addresses. Better to have a base register to which we can
46 apply a 32-bit displacement.
47
48 There are generally three items of interest:
49 (1) helper functions in the main executable,
50 (2) TranslationBlock data structures,
51 (3) the return address in the epilogue.
52
53 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
54 will be inside the main executable, and thus near enough to make a
55 pointer to the epilogue be within 2GB of all helper functions.
56
57 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
58 and odds are it'll be somewhere close to the main malloc arena, and so
59 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
60
61 For --enable-pie, everything will be kinda near everything else,
62 somewhere in high memory.
63
64 Thus we choose to keep the return address in a call-saved register. */
65 #define TCG_REG_RA TCG_REG_R31
66 #define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
67
68 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
69 #define SZP ((int)sizeof(void *))
70
71 /* Shorthand for size of a register. */
72 #define SZR (TCG_TARGET_REG_BITS / 8)
73
74 #define TCG_CT_CONST_S16 0x100
75 #define TCG_CT_CONST_U16 0x200
76 #define TCG_CT_CONST_S32 0x400
77 #define TCG_CT_CONST_U32 0x800
78 #define TCG_CT_CONST_ZERO 0x1000
79 #define TCG_CT_CONST_MONE 0x2000
80 #define TCG_CT_CONST_WSZ 0x4000
81
82 static tcg_insn_unit *tb_ret_addr;
83
84 #include "elf.h"
85
86 bool have_isa_2_06;
87 bool have_isa_3_00;
88
89 #define HAVE_ISA_2_06 have_isa_2_06
90 #define HAVE_ISEL have_isa_2_06
91
92 #ifndef CONFIG_SOFTMMU
93 #define TCG_GUEST_BASE_REG 30
94 #endif
95
96 #ifdef CONFIG_DEBUG_TCG
97 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
98 "r0",
99 "r1",
100 "r2",
101 "r3",
102 "r4",
103 "r5",
104 "r6",
105 "r7",
106 "r8",
107 "r9",
108 "r10",
109 "r11",
110 "r12",
111 "r13",
112 "r14",
113 "r15",
114 "r16",
115 "r17",
116 "r18",
117 "r19",
118 "r20",
119 "r21",
120 "r22",
121 "r23",
122 "r24",
123 "r25",
124 "r26",
125 "r27",
126 "r28",
127 "r29",
128 "r30",
129 "r31"
130 };
131 #endif
132
133 static const int tcg_target_reg_alloc_order[] = {
134 TCG_REG_R14, /* call saved registers */
135 TCG_REG_R15,
136 TCG_REG_R16,
137 TCG_REG_R17,
138 TCG_REG_R18,
139 TCG_REG_R19,
140 TCG_REG_R20,
141 TCG_REG_R21,
142 TCG_REG_R22,
143 TCG_REG_R23,
144 TCG_REG_R24,
145 TCG_REG_R25,
146 TCG_REG_R26,
147 TCG_REG_R27,
148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31,
152 TCG_REG_R12, /* call clobbered, non-arguments */
153 TCG_REG_R11,
154 TCG_REG_R2,
155 TCG_REG_R13,
156 TCG_REG_R10, /* call clobbered, arguments */
157 TCG_REG_R9,
158 TCG_REG_R8,
159 TCG_REG_R7,
160 TCG_REG_R6,
161 TCG_REG_R5,
162 TCG_REG_R4,
163 TCG_REG_R3,
164 };
165
166 static const int tcg_target_call_iarg_regs[] = {
167 TCG_REG_R3,
168 TCG_REG_R4,
169 TCG_REG_R5,
170 TCG_REG_R6,
171 TCG_REG_R7,
172 TCG_REG_R8,
173 TCG_REG_R9,
174 TCG_REG_R10
175 };
176
177 static const int tcg_target_call_oarg_regs[] = {
178 TCG_REG_R3,
179 TCG_REG_R4
180 };
181
182 static const int tcg_target_callee_save_regs[] = {
183 #ifdef TCG_TARGET_CALL_DARWIN
184 TCG_REG_R11,
185 #endif
186 TCG_REG_R14,
187 TCG_REG_R15,
188 TCG_REG_R16,
189 TCG_REG_R17,
190 TCG_REG_R18,
191 TCG_REG_R19,
192 TCG_REG_R20,
193 TCG_REG_R21,
194 TCG_REG_R22,
195 TCG_REG_R23,
196 TCG_REG_R24,
197 TCG_REG_R25,
198 TCG_REG_R26,
199 TCG_REG_R27, /* currently used for the global env */
200 TCG_REG_R28,
201 TCG_REG_R29,
202 TCG_REG_R30,
203 TCG_REG_R31
204 };
205
206 static inline bool in_range_b(tcg_target_long target)
207 {
208 return target == sextract64(target, 0, 26);
209 }
210
211 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
212 {
213 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
214 tcg_debug_assert(in_range_b(disp));
215 return disp & 0x3fffffc;
216 }
217
218 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
219 {
220 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
221 }
222
223 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
224 {
225 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
226 tcg_debug_assert(disp == (int16_t) disp);
227 return disp & 0xfffc;
228 }
229
230 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
231 {
232 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
233 }
234
235 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
236 {
237 unsigned retrans = *s->code_ptr & 0x3fffffc;
238 tcg_out32(s, insn | retrans);
239 }
240
241 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
242 {
243 unsigned retrans = *s->code_ptr & 0xfffc;
244 tcg_out32(s, insn | retrans);
245 }
246
247 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
248 intptr_t value, intptr_t addend)
249 {
250 tcg_insn_unit *target = (tcg_insn_unit *)value;
251
252 tcg_debug_assert(addend == 0);
253 switch (type) {
254 case R_PPC_REL14:
255 reloc_pc14(code_ptr, target);
256 break;
257 case R_PPC_REL24:
258 reloc_pc24(code_ptr, target);
259 break;
260 default:
261 tcg_abort();
262 }
263 }
264
265 /* parse target specific constraints */
266 static const char *target_parse_constraint(TCGArgConstraint *ct,
267 const char *ct_str, TCGType type)
268 {
269 switch (*ct_str++) {
270 case 'A': case 'B': case 'C': case 'D':
271 ct->ct |= TCG_CT_REG;
272 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
273 break;
274 case 'r':
275 ct->ct |= TCG_CT_REG;
276 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
277 break;
278 case 'L': /* qemu_ld constraint */
279 ct->ct |= TCG_CT_REG;
280 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
281 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
282 #ifdef CONFIG_SOFTMMU
283 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
284 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
285 #endif
286 break;
287 case 'S': /* qemu_st constraint */
288 ct->ct |= TCG_CT_REG;
289 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
290 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
291 #ifdef CONFIG_SOFTMMU
292 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
293 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
294 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
295 #endif
296 break;
297 case 'I':
298 ct->ct |= TCG_CT_CONST_S16;
299 break;
300 case 'J':
301 ct->ct |= TCG_CT_CONST_U16;
302 break;
303 case 'M':
304 ct->ct |= TCG_CT_CONST_MONE;
305 break;
306 case 'T':
307 ct->ct |= TCG_CT_CONST_S32;
308 break;
309 case 'U':
310 ct->ct |= TCG_CT_CONST_U32;
311 break;
312 case 'W':
313 ct->ct |= TCG_CT_CONST_WSZ;
314 break;
315 case 'Z':
316 ct->ct |= TCG_CT_CONST_ZERO;
317 break;
318 default:
319 return NULL;
320 }
321 return ct_str;
322 }
323
324 /* test if a constant matches the constraint */
325 static int tcg_target_const_match(tcg_target_long val, TCGType type,
326 const TCGArgConstraint *arg_ct)
327 {
328 int ct = arg_ct->ct;
329 if (ct & TCG_CT_CONST) {
330 return 1;
331 }
332
333 /* The only 32-bit constraint we use aside from
334 TCG_CT_CONST is TCG_CT_CONST_S16. */
335 if (type == TCG_TYPE_I32) {
336 val = (int32_t)val;
337 }
338
339 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
340 return 1;
341 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
342 return 1;
343 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
344 return 1;
345 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
346 return 1;
347 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
348 return 1;
349 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
350 return 1;
351 } else if ((ct & TCG_CT_CONST_WSZ)
352 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
353 return 1;
354 }
355 return 0;
356 }
357
358 #define OPCD(opc) ((opc)<<26)
359 #define XO19(opc) (OPCD(19)|((opc)<<1))
360 #define MD30(opc) (OPCD(30)|((opc)<<2))
361 #define MDS30(opc) (OPCD(30)|((opc)<<1))
362 #define XO31(opc) (OPCD(31)|((opc)<<1))
363 #define XO58(opc) (OPCD(58)|(opc))
364 #define XO62(opc) (OPCD(62)|(opc))
365
366 #define B OPCD( 18)
367 #define BC OPCD( 16)
368 #define LBZ OPCD( 34)
369 #define LHZ OPCD( 40)
370 #define LHA OPCD( 42)
371 #define LWZ OPCD( 32)
372 #define STB OPCD( 38)
373 #define STH OPCD( 44)
374 #define STW OPCD( 36)
375
376 #define STD XO62( 0)
377 #define STDU XO62( 1)
378 #define STDX XO31(149)
379
380 #define LD XO58( 0)
381 #define LDX XO31( 21)
382 #define LDU XO58( 1)
383 #define LWA XO58( 2)
384 #define LWAX XO31(341)
385
386 #define ADDIC OPCD( 12)
387 #define ADDI OPCD( 14)
388 #define ADDIS OPCD( 15)
389 #define ORI OPCD( 24)
390 #define ORIS OPCD( 25)
391 #define XORI OPCD( 26)
392 #define XORIS OPCD( 27)
393 #define ANDI OPCD( 28)
394 #define ANDIS OPCD( 29)
395 #define MULLI OPCD( 7)
396 #define CMPLI OPCD( 10)
397 #define CMPI OPCD( 11)
398 #define SUBFIC OPCD( 8)
399
400 #define LWZU OPCD( 33)
401 #define STWU OPCD( 37)
402
403 #define RLWIMI OPCD( 20)
404 #define RLWINM OPCD( 21)
405 #define RLWNM OPCD( 23)
406
407 #define RLDICL MD30( 0)
408 #define RLDICR MD30( 1)
409 #define RLDIMI MD30( 3)
410 #define RLDCL MDS30( 8)
411
412 #define BCLR XO19( 16)
413 #define BCCTR XO19(528)
414 #define CRAND XO19(257)
415 #define CRANDC XO19(129)
416 #define CRNAND XO19(225)
417 #define CROR XO19(449)
418 #define CRNOR XO19( 33)
419
420 #define EXTSB XO31(954)
421 #define EXTSH XO31(922)
422 #define EXTSW XO31(986)
423 #define ADD XO31(266)
424 #define ADDE XO31(138)
425 #define ADDME XO31(234)
426 #define ADDZE XO31(202)
427 #define ADDC XO31( 10)
428 #define AND XO31( 28)
429 #define SUBF XO31( 40)
430 #define SUBFC XO31( 8)
431 #define SUBFE XO31(136)
432 #define SUBFME XO31(232)
433 #define SUBFZE XO31(200)
434 #define OR XO31(444)
435 #define XOR XO31(316)
436 #define MULLW XO31(235)
437 #define MULHW XO31( 75)
438 #define MULHWU XO31( 11)
439 #define DIVW XO31(491)
440 #define DIVWU XO31(459)
441 #define CMP XO31( 0)
442 #define CMPL XO31( 32)
443 #define LHBRX XO31(790)
444 #define LWBRX XO31(534)
445 #define LDBRX XO31(532)
446 #define STHBRX XO31(918)
447 #define STWBRX XO31(662)
448 #define STDBRX XO31(660)
449 #define MFSPR XO31(339)
450 #define MTSPR XO31(467)
451 #define SRAWI XO31(824)
452 #define NEG XO31(104)
453 #define MFCR XO31( 19)
454 #define MFOCRF (MFCR | (1u << 20))
455 #define NOR XO31(124)
456 #define CNTLZW XO31( 26)
457 #define CNTLZD XO31( 58)
458 #define CNTTZW XO31(538)
459 #define CNTTZD XO31(570)
460 #define CNTPOPW XO31(378)
461 #define CNTPOPD XO31(506)
462 #define ANDC XO31( 60)
463 #define ORC XO31(412)
464 #define EQV XO31(284)
465 #define NAND XO31(476)
466 #define ISEL XO31( 15)
467
468 #define MULLD XO31(233)
469 #define MULHD XO31( 73)
470 #define MULHDU XO31( 9)
471 #define DIVD XO31(489)
472 #define DIVDU XO31(457)
473
474 #define LBZX XO31( 87)
475 #define LHZX XO31(279)
476 #define LHAX XO31(343)
477 #define LWZX XO31( 23)
478 #define STBX XO31(215)
479 #define STHX XO31(407)
480 #define STWX XO31(151)
481
482 #define EIEIO XO31(854)
483 #define HWSYNC XO31(598)
484 #define LWSYNC (HWSYNC | (1u << 21))
485
486 #define SPR(a, b) ((((a)<<5)|(b))<<11)
487 #define LR SPR(8, 0)
488 #define CTR SPR(9, 0)
489
490 #define SLW XO31( 24)
491 #define SRW XO31(536)
492 #define SRAW XO31(792)
493
494 #define SLD XO31( 27)
495 #define SRD XO31(539)
496 #define SRAD XO31(794)
497 #define SRADI XO31(413<<1)
498
499 #define TW XO31( 4)
500 #define TRAP (TW | TO(31))
501
502 #define NOP ORI /* ori 0,0,0 */
503
504 #define RT(r) ((r)<<21)
505 #define RS(r) ((r)<<21)
506 #define RA(r) ((r)<<16)
507 #define RB(r) ((r)<<11)
508 #define TO(t) ((t)<<21)
509 #define SH(s) ((s)<<11)
510 #define MB(b) ((b)<<6)
511 #define ME(e) ((e)<<1)
512 #define BO(o) ((o)<<21)
513 #define MB64(b) ((b)<<5)
514 #define FXM(b) (1 << (19 - (b)))
515
516 #define LK 1
517
518 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
519 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
520 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
521 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
522
523 #define BF(n) ((n)<<23)
524 #define BI(n, c) (((c)+((n)*4))<<16)
525 #define BT(n, c) (((c)+((n)*4))<<21)
526 #define BA(n, c) (((c)+((n)*4))<<16)
527 #define BB(n, c) (((c)+((n)*4))<<11)
528 #define BC_(n, c) (((c)+((n)*4))<<6)
529
530 #define BO_COND_TRUE BO(12)
531 #define BO_COND_FALSE BO( 4)
532 #define BO_ALWAYS BO(20)
533
534 enum {
535 CR_LT,
536 CR_GT,
537 CR_EQ,
538 CR_SO
539 };
540
541 static const uint32_t tcg_to_bc[] = {
542 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
543 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
544 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
545 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
546 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
547 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
548 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
549 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
550 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
551 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
552 };
553
554 /* The low bit here is set if the RA and RB fields must be inverted. */
555 static const uint32_t tcg_to_isel[] = {
556 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
557 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
558 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
559 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
560 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
561 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
562 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
563 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
564 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
565 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
566 };
567
568 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
569 TCGReg base, tcg_target_long offset);
570
571 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
572 {
573 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
574 if (ret != arg) {
575 tcg_out32(s, OR | SAB(arg, ret, arg));
576 }
577 }
578
579 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
580 int sh, int mb)
581 {
582 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
583 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
584 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
585 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
586 }
587
588 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
589 int sh, int mb, int me)
590 {
591 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
592 }
593
594 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
595 {
596 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
597 }
598
599 static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
600 {
601 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
602 }
603
604 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
605 {
606 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
607 }
608
609 static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
610 {
611 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
612 }
613
614 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
615 {
616 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
617 }
618
619 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
620 {
621 if (arg == (int16_t) arg) {
622 tcg_out32(s, ADDI | TAI(ret, 0, arg));
623 } else {
624 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
625 if (arg & 0xffff) {
626 tcg_out32(s, ORI | SAI(ret, ret, arg));
627 }
628 }
629 }
630
631 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
632 tcg_target_long arg)
633 {
634 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
635 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
636 tcg_out_movi32(s, ret, arg);
637 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
638 tcg_out32(s, ADDI | TAI(ret, 0, arg));
639 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
640 } else {
641 int32_t high;
642
643 if (USE_REG_RA) {
644 intptr_t diff = arg - (intptr_t)tb_ret_addr;
645 if (diff == (int32_t)diff) {
646 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
647 return;
648 }
649 }
650
651 high = arg >> 31 >> 1;
652 tcg_out_movi32(s, ret, high);
653 if (high) {
654 tcg_out_shli64(s, ret, ret, 32);
655 }
656 if (arg & 0xffff0000) {
657 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
658 }
659 if (arg & 0xffff) {
660 tcg_out32(s, ORI | SAI(ret, ret, arg));
661 }
662 }
663 }
664
665 static bool mask_operand(uint32_t c, int *mb, int *me)
666 {
667 uint32_t lsb, test;
668
669 /* Accept a bit pattern like:
670 0....01....1
671 1....10....0
672 0..01..10..0
673 Keep track of the transitions. */
674 if (c == 0 || c == -1) {
675 return false;
676 }
677 test = c;
678 lsb = test & -test;
679 test += lsb;
680 if (test & (test - 1)) {
681 return false;
682 }
683
684 *me = clz32(lsb);
685 *mb = test ? clz32(test & -test) + 1 : 0;
686 return true;
687 }
688
689 static bool mask64_operand(uint64_t c, int *mb, int *me)
690 {
691 uint64_t lsb;
692
693 if (c == 0) {
694 return false;
695 }
696
697 lsb = c & -c;
698 /* Accept 1..10..0. */
699 if (c == -lsb) {
700 *mb = 0;
701 *me = clz64(lsb);
702 return true;
703 }
704 /* Accept 0..01..1. */
705 if (lsb == 1 && (c & (c + 1)) == 0) {
706 *mb = clz64(c + 1) + 1;
707 *me = 63;
708 return true;
709 }
710 return false;
711 }
712
713 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
714 {
715 int mb, me;
716
717 if (mask_operand(c, &mb, &me)) {
718 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
719 } else if ((c & 0xffff) == c) {
720 tcg_out32(s, ANDI | SAI(src, dst, c));
721 return;
722 } else if ((c & 0xffff0000) == c) {
723 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
724 return;
725 } else {
726 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
727 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
728 }
729 }
730
731 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
732 {
733 int mb, me;
734
735 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
736 if (mask64_operand(c, &mb, &me)) {
737 if (mb == 0) {
738 tcg_out_rld(s, RLDICR, dst, src, 0, me);
739 } else {
740 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
741 }
742 } else if ((c & 0xffff) == c) {
743 tcg_out32(s, ANDI | SAI(src, dst, c));
744 return;
745 } else if ((c & 0xffff0000) == c) {
746 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
747 return;
748 } else {
749 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
750 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
751 }
752 }
753
754 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
755 int op_lo, int op_hi)
756 {
757 if (c >> 16) {
758 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
759 src = dst;
760 }
761 if (c & 0xffff) {
762 tcg_out32(s, op_lo | SAI(src, dst, c));
763 src = dst;
764 }
765 }
766
767 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
768 {
769 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
770 }
771
772 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
773 {
774 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
775 }
776
777 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
778 {
779 ptrdiff_t disp = tcg_pcrel_diff(s, target);
780 if (in_range_b(disp)) {
781 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
782 } else {
783 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
784 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
785 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
786 }
787 }
788
789 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
790 TCGReg base, tcg_target_long offset)
791 {
792 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
793 bool is_store = false;
794 TCGReg rs = TCG_REG_TMP1;
795
796 switch (opi) {
797 case LD: case LWA:
798 align = 3;
799 /* FALLTHRU */
800 default:
801 if (rt != TCG_REG_R0) {
802 rs = rt;
803 break;
804 }
805 break;
806 case STD:
807 align = 3;
808 /* FALLTHRU */
809 case STB: case STH: case STW:
810 is_store = true;
811 break;
812 }
813
814 /* For unaligned, or very large offsets, use the indexed form. */
815 if (offset & align || offset != (int32_t)offset) {
816 if (rs == base) {
817 rs = TCG_REG_R0;
818 }
819 tcg_debug_assert(!is_store || rs != rt);
820 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
821 tcg_out32(s, opx | TAB(rt, base, rs));
822 return;
823 }
824
825 l0 = (int16_t)offset;
826 offset = (offset - l0) >> 16;
827 l1 = (int16_t)offset;
828
829 if (l1 < 0 && orig >= 0) {
830 extra = 0x4000;
831 l1 = (int16_t)(offset - 0x4000);
832 }
833 if (l1) {
834 tcg_out32(s, ADDIS | TAI(rs, base, l1));
835 base = rs;
836 }
837 if (extra) {
838 tcg_out32(s, ADDIS | TAI(rs, base, extra));
839 base = rs;
840 }
841 if (opi != ADDI || base != rt || l0 != 0) {
842 tcg_out32(s, opi | TAI(rt, base, l0));
843 }
844 }
845
846 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
847 TCGReg arg1, intptr_t arg2)
848 {
849 int opi, opx;
850
851 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
852 if (type == TCG_TYPE_I32) {
853 opi = LWZ, opx = LWZX;
854 } else {
855 opi = LD, opx = LDX;
856 }
857 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
858 }
859
860 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
861 TCGReg arg1, intptr_t arg2)
862 {
863 int opi, opx;
864
865 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
866 if (type == TCG_TYPE_I32) {
867 opi = STW, opx = STWX;
868 } else {
869 opi = STD, opx = STDX;
870 }
871 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
872 }
873
874 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
875 TCGReg base, intptr_t ofs)
876 {
877 return false;
878 }
879
880 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
881 int const_arg2, int cr, TCGType type)
882 {
883 int imm;
884 uint32_t op;
885
886 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
887
888 /* Simplify the comparisons below wrt CMPI. */
889 if (type == TCG_TYPE_I32) {
890 arg2 = (int32_t)arg2;
891 }
892
893 switch (cond) {
894 case TCG_COND_EQ:
895 case TCG_COND_NE:
896 if (const_arg2) {
897 if ((int16_t) arg2 == arg2) {
898 op = CMPI;
899 imm = 1;
900 break;
901 } else if ((uint16_t) arg2 == arg2) {
902 op = CMPLI;
903 imm = 1;
904 break;
905 }
906 }
907 op = CMPL;
908 imm = 0;
909 break;
910
911 case TCG_COND_LT:
912 case TCG_COND_GE:
913 case TCG_COND_LE:
914 case TCG_COND_GT:
915 if (const_arg2) {
916 if ((int16_t) arg2 == arg2) {
917 op = CMPI;
918 imm = 1;
919 break;
920 }
921 }
922 op = CMP;
923 imm = 0;
924 break;
925
926 case TCG_COND_LTU:
927 case TCG_COND_GEU:
928 case TCG_COND_LEU:
929 case TCG_COND_GTU:
930 if (const_arg2) {
931 if ((uint16_t) arg2 == arg2) {
932 op = CMPLI;
933 imm = 1;
934 break;
935 }
936 }
937 op = CMPL;
938 imm = 0;
939 break;
940
941 default:
942 tcg_abort();
943 }
944 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
945
946 if (imm) {
947 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
948 } else {
949 if (const_arg2) {
950 tcg_out_movi(s, type, TCG_REG_R0, arg2);
951 arg2 = TCG_REG_R0;
952 }
953 tcg_out32(s, op | RA(arg1) | RB(arg2));
954 }
955 }
956
957 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
958 TCGReg dst, TCGReg src)
959 {
960 if (type == TCG_TYPE_I32) {
961 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
962 tcg_out_shri32(s, dst, dst, 5);
963 } else {
964 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
965 tcg_out_shri64(s, dst, dst, 6);
966 }
967 }
968
969 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
970 {
971 /* X != 0 implies X + -1 generates a carry. Extra addition
972 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
973 if (dst != src) {
974 tcg_out32(s, ADDIC | TAI(dst, src, -1));
975 tcg_out32(s, SUBFE | TAB(dst, dst, src));
976 } else {
977 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
978 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
979 }
980 }
981
982 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
983 bool const_arg2)
984 {
985 if (const_arg2) {
986 if ((uint32_t)arg2 == arg2) {
987 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
988 } else {
989 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
990 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
991 }
992 } else {
993 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
994 }
995 return TCG_REG_R0;
996 }
997
998 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
999 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1000 int const_arg2)
1001 {
1002 int crop, sh;
1003
1004 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1005
1006 /* Ignore high bits of a potential constant arg2. */
1007 if (type == TCG_TYPE_I32) {
1008 arg2 = (uint32_t)arg2;
1009 }
1010
1011 /* Handle common and trivial cases before handling anything else. */
1012 if (arg2 == 0) {
1013 switch (cond) {
1014 case TCG_COND_EQ:
1015 tcg_out_setcond_eq0(s, type, arg0, arg1);
1016 return;
1017 case TCG_COND_NE:
1018 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1019 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1020 arg1 = TCG_REG_R0;
1021 }
1022 tcg_out_setcond_ne0(s, arg0, arg1);
1023 return;
1024 case TCG_COND_GE:
1025 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1026 arg1 = arg0;
1027 /* FALLTHRU */
1028 case TCG_COND_LT:
1029 /* Extract the sign bit. */
1030 if (type == TCG_TYPE_I32) {
1031 tcg_out_shri32(s, arg0, arg1, 31);
1032 } else {
1033 tcg_out_shri64(s, arg0, arg1, 63);
1034 }
1035 return;
1036 default:
1037 break;
1038 }
1039 }
1040
1041 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1042 All other cases below are also at least 3 insns, so speed up the
1043 code generator by not considering them and always using ISEL. */
1044 if (HAVE_ISEL) {
1045 int isel, tab;
1046
1047 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1048
1049 isel = tcg_to_isel[cond];
1050
1051 tcg_out_movi(s, type, arg0, 1);
1052 if (isel & 1) {
1053 /* arg0 = (bc ? 0 : 1) */
1054 tab = TAB(arg0, 0, arg0);
1055 isel &= ~1;
1056 } else {
1057 /* arg0 = (bc ? 1 : 0) */
1058 tcg_out_movi(s, type, TCG_REG_R0, 0);
1059 tab = TAB(arg0, arg0, TCG_REG_R0);
1060 }
1061 tcg_out32(s, isel | tab);
1062 return;
1063 }
1064
1065 switch (cond) {
1066 case TCG_COND_EQ:
1067 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1068 tcg_out_setcond_eq0(s, type, arg0, arg1);
1069 return;
1070
1071 case TCG_COND_NE:
1072 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1073 /* Discard the high bits only once, rather than both inputs. */
1074 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1075 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1076 arg1 = TCG_REG_R0;
1077 }
1078 tcg_out_setcond_ne0(s, arg0, arg1);
1079 return;
1080
1081 case TCG_COND_GT:
1082 case TCG_COND_GTU:
1083 sh = 30;
1084 crop = 0;
1085 goto crtest;
1086
1087 case TCG_COND_LT:
1088 case TCG_COND_LTU:
1089 sh = 29;
1090 crop = 0;
1091 goto crtest;
1092
1093 case TCG_COND_GE:
1094 case TCG_COND_GEU:
1095 sh = 31;
1096 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1097 goto crtest;
1098
1099 case TCG_COND_LE:
1100 case TCG_COND_LEU:
1101 sh = 31;
1102 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1103 crtest:
1104 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1105 if (crop) {
1106 tcg_out32(s, crop);
1107 }
1108 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1109 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1110 break;
1111
1112 default:
1113 tcg_abort();
1114 }
1115 }
1116
1117 static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
1118 {
1119 if (l->has_value) {
1120 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1121 } else {
1122 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
1123 tcg_out_bc_noaddr(s, bc);
1124 }
1125 }
1126
1127 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1128 TCGArg arg1, TCGArg arg2, int const_arg2,
1129 TCGLabel *l, TCGType type)
1130 {
1131 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1132 tcg_out_bc(s, tcg_to_bc[cond], l);
1133 }
1134
1135 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1136 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1137 TCGArg v2, bool const_c2)
1138 {
1139 /* If for some reason both inputs are zero, don't produce bad code. */
1140 if (v1 == 0 && v2 == 0) {
1141 tcg_out_movi(s, type, dest, 0);
1142 return;
1143 }
1144
1145 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1146
1147 if (HAVE_ISEL) {
1148 int isel = tcg_to_isel[cond];
1149
1150 /* Swap the V operands if the operation indicates inversion. */
1151 if (isel & 1) {
1152 int t = v1;
1153 v1 = v2;
1154 v2 = t;
1155 isel &= ~1;
1156 }
1157 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1158 if (v2 == 0) {
1159 tcg_out_movi(s, type, TCG_REG_R0, 0);
1160 }
1161 tcg_out32(s, isel | TAB(dest, v1, v2));
1162 } else {
1163 if (dest == v2) {
1164 cond = tcg_invert_cond(cond);
1165 v2 = v1;
1166 } else if (dest != v1) {
1167 if (v1 == 0) {
1168 tcg_out_movi(s, type, dest, 0);
1169 } else {
1170 tcg_out_mov(s, type, dest, v1);
1171 }
1172 }
1173 /* Branch forward over one insn */
1174 tcg_out32(s, tcg_to_bc[cond] | 8);
1175 if (v2 == 0) {
1176 tcg_out_movi(s, type, dest, 0);
1177 } else {
1178 tcg_out_mov(s, type, dest, v2);
1179 }
1180 }
1181 }
1182
1183 static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1184 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1185 {
1186 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1187 tcg_out32(s, opc | RA(a0) | RS(a1));
1188 } else {
1189 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1190 /* Note that the only other valid constant for a2 is 0. */
1191 if (HAVE_ISEL) {
1192 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1193 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1194 } else if (!const_a2 && a0 == a2) {
1195 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1196 tcg_out32(s, opc | RA(a0) | RS(a1));
1197 } else {
1198 tcg_out32(s, opc | RA(a0) | RS(a1));
1199 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1200 if (const_a2) {
1201 tcg_out_movi(s, type, a0, 0);
1202 } else {
1203 tcg_out_mov(s, type, a0, a2);
1204 }
1205 }
1206 }
1207 }
1208
1209 static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1210 const int *const_args)
1211 {
1212 static const struct { uint8_t bit1, bit2; } bits[] = {
1213 [TCG_COND_LT ] = { CR_LT, CR_LT },
1214 [TCG_COND_LE ] = { CR_LT, CR_GT },
1215 [TCG_COND_GT ] = { CR_GT, CR_GT },
1216 [TCG_COND_GE ] = { CR_GT, CR_LT },
1217 [TCG_COND_LTU] = { CR_LT, CR_LT },
1218 [TCG_COND_LEU] = { CR_LT, CR_GT },
1219 [TCG_COND_GTU] = { CR_GT, CR_GT },
1220 [TCG_COND_GEU] = { CR_GT, CR_LT },
1221 };
1222
1223 TCGCond cond = args[4], cond2;
1224 TCGArg al, ah, bl, bh;
1225 int blconst, bhconst;
1226 int op, bit1, bit2;
1227
1228 al = args[0];
1229 ah = args[1];
1230 bl = args[2];
1231 bh = args[3];
1232 blconst = const_args[2];
1233 bhconst = const_args[3];
1234
1235 switch (cond) {
1236 case TCG_COND_EQ:
1237 op = CRAND;
1238 goto do_equality;
1239 case TCG_COND_NE:
1240 op = CRNAND;
1241 do_equality:
1242 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1243 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1244 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1245 break;
1246
1247 case TCG_COND_LT:
1248 case TCG_COND_LE:
1249 case TCG_COND_GT:
1250 case TCG_COND_GE:
1251 case TCG_COND_LTU:
1252 case TCG_COND_LEU:
1253 case TCG_COND_GTU:
1254 case TCG_COND_GEU:
1255 bit1 = bits[cond].bit1;
1256 bit2 = bits[cond].bit2;
1257 op = (bit1 != bit2 ? CRANDC : CRAND);
1258 cond2 = tcg_unsigned_cond(cond);
1259
1260 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1261 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1262 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1263 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1264 break;
1265
1266 default:
1267 tcg_abort();
1268 }
1269 }
1270
1271 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1272 const int *const_args)
1273 {
1274 tcg_out_cmp2(s, args + 1, const_args + 1);
1275 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1276 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1277 }
1278
1279 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1280 const int *const_args)
1281 {
1282 tcg_out_cmp2(s, args, const_args);
1283 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
1284 }
1285
1286 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1287 {
1288 uint32_t insn = HWSYNC;
1289 a0 &= TCG_MO_ALL;
1290 if (a0 == TCG_MO_LD_LD) {
1291 insn = LWSYNC;
1292 } else if (a0 == TCG_MO_ST_ST) {
1293 insn = EIEIO;
1294 }
1295 tcg_out32(s, insn);
1296 }
1297
1298 #ifdef __powerpc64__
1299 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1300 {
1301 tcg_insn_unit i1, i2;
1302 uint64_t pair;
1303 intptr_t diff = addr - jmp_addr;
1304
1305 if (in_range_b(diff)) {
1306 i1 = B | (diff & 0x3fffffc);
1307 i2 = NOP;
1308 } else if (USE_REG_RA) {
1309 intptr_t lo, hi;
1310 diff = addr - (uintptr_t)tb_ret_addr;
1311 lo = (int16_t)diff;
1312 hi = (int32_t)(diff - lo);
1313 tcg_debug_assert(diff == hi + lo);
1314 i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);
1315 i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);
1316 } else {
1317 tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);
1318 i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);
1319 i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);
1320 }
1321 #ifdef HOST_WORDS_BIGENDIAN
1322 pair = (uint64_t)i1 << 32 | i2;
1323 #else
1324 pair = (uint64_t)i2 << 32 | i1;
1325 #endif
1326
1327 atomic_set((uint64_t *)jmp_addr, pair);
1328 flush_icache_range(jmp_addr, jmp_addr + 8);
1329 }
1330 #else
1331 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1332 {
1333 intptr_t diff = addr - jmp_addr;
1334 tcg_debug_assert(in_range_b(diff));
1335 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1336 flush_icache_range(jmp_addr, jmp_addr + 4);
1337 }
1338 #endif
1339
1340 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1341 {
1342 #ifdef _CALL_AIX
1343 /* Look through the descriptor. If the branch is in range, and we
1344 don't have to spend too much effort on building the toc. */
1345 void *tgt = ((void **)target)[0];
1346 uintptr_t toc = ((uintptr_t *)target)[1];
1347 intptr_t diff = tcg_pcrel_diff(s, tgt);
1348
1349 if (in_range_b(diff) && toc == (uint32_t)toc) {
1350 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
1351 tcg_out_b(s, LK, tgt);
1352 } else {
1353 /* Fold the low bits of the constant into the addresses below. */
1354 intptr_t arg = (intptr_t)target;
1355 int ofs = (int16_t)arg;
1356
1357 if (ofs + 8 < 0x8000) {
1358 arg -= ofs;
1359 } else {
1360 ofs = 0;
1361 }
1362 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1363 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
1364 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1365 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
1366 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1367 }
1368 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1369 intptr_t diff;
1370
1371 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1372 address, which the callee uses to compute its TOC address. */
1373 /* FIXME: when the branch is in range, we could avoid r12 load if we
1374 knew that the destination uses the same TOC, and what its local
1375 entry point offset is. */
1376 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1377
1378 diff = tcg_pcrel_diff(s, target);
1379 if (in_range_b(diff)) {
1380 tcg_out_b(s, LK, target);
1381 } else {
1382 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1383 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1384 }
1385 #else
1386 tcg_out_b(s, LK, target);
1387 #endif
1388 }
1389
1390 static const uint32_t qemu_ldx_opc[16] = {
1391 [MO_UB] = LBZX,
1392 [MO_UW] = LHZX,
1393 [MO_UL] = LWZX,
1394 [MO_Q] = LDX,
1395 [MO_SW] = LHAX,
1396 [MO_SL] = LWAX,
1397 [MO_BSWAP | MO_UB] = LBZX,
1398 [MO_BSWAP | MO_UW] = LHBRX,
1399 [MO_BSWAP | MO_UL] = LWBRX,
1400 [MO_BSWAP | MO_Q] = LDBRX,
1401 };
1402
1403 static const uint32_t qemu_stx_opc[16] = {
1404 [MO_UB] = STBX,
1405 [MO_UW] = STHX,
1406 [MO_UL] = STWX,
1407 [MO_Q] = STDX,
1408 [MO_BSWAP | MO_UB] = STBX,
1409 [MO_BSWAP | MO_UW] = STHBRX,
1410 [MO_BSWAP | MO_UL] = STWBRX,
1411 [MO_BSWAP | MO_Q] = STDBRX,
1412 };
1413
1414 static const uint32_t qemu_exts_opc[4] = {
1415 EXTSB, EXTSH, EXTSW, 0
1416 };
1417
1418 #if defined (CONFIG_SOFTMMU)
1419 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1420 * int mmu_idx, uintptr_t ra)
1421 */
1422 static void * const qemu_ld_helpers[16] = {
1423 [MO_UB] = helper_ret_ldub_mmu,
1424 [MO_LEUW] = helper_le_lduw_mmu,
1425 [MO_LEUL] = helper_le_ldul_mmu,
1426 [MO_LEQ] = helper_le_ldq_mmu,
1427 [MO_BEUW] = helper_be_lduw_mmu,
1428 [MO_BEUL] = helper_be_ldul_mmu,
1429 [MO_BEQ] = helper_be_ldq_mmu,
1430 };
1431
1432 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1433 * uintxx_t val, int mmu_idx, uintptr_t ra)
1434 */
1435 static void * const qemu_st_helpers[16] = {
1436 [MO_UB] = helper_ret_stb_mmu,
1437 [MO_LEUW] = helper_le_stw_mmu,
1438 [MO_LEUL] = helper_le_stl_mmu,
1439 [MO_LEQ] = helper_le_stq_mmu,
1440 [MO_BEUW] = helper_be_stw_mmu,
1441 [MO_BEUL] = helper_be_stl_mmu,
1442 [MO_BEQ] = helper_be_stq_mmu,
1443 };
1444
1445 /* Perform the TLB load and compare. Places the result of the comparison
1446 in CR7, loads the addend of the TLB into R3, and returns the register
1447 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1448
1449 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
1450 TCGReg addrlo, TCGReg addrhi,
1451 int mem_index, bool is_read)
1452 {
1453 int cmp_off
1454 = (is_read
1455 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1456 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1457 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1458 TCGReg base = TCG_AREG0;
1459 unsigned s_bits = opc & MO_SIZE;
1460 unsigned a_bits = get_alignment_bits(opc);
1461
1462 /* Extract the page index, shifted into place for tlb index. */
1463 if (TCG_TARGET_REG_BITS == 64) {
1464 if (TARGET_LONG_BITS == 32) {
1465 /* Zero-extend the address into a place helpful for further use. */
1466 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1467 addrlo = TCG_REG_R4;
1468 } else {
1469 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1470 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1471 }
1472 }
1473
1474 /* Compensate for very large offsets. */
1475 if (add_off >= 0x8000) {
1476 /* Most target env are smaller than 32k; none are larger than 64k.
1477 Simplify the logic here merely to offset by 0x7ff0, giving us a
1478 range just shy of 64k. Check this assumption. */
1479 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1480 tlb_table[NB_MMU_MODES - 1][1])
1481 > 0x7ff0 + 0x7fff);
1482 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1483 base = TCG_REG_TMP1;
1484 cmp_off -= 0x7ff0;
1485 add_off -= 0x7ff0;
1486 }
1487
1488 /* Extraction and shifting, part 2. */
1489 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1490 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
1491 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1492 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1493 31 - CPU_TLB_ENTRY_BITS);
1494 } else {
1495 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1496 }
1497
1498 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1499
1500 /* Load the tlb comparator. */
1501 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1502 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1503 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1504 } else {
1505 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1506 }
1507
1508 /* Load the TLB addend for use on the fast path. Do this asap
1509 to minimize any load use delay. */
1510 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
1511
1512 /* Clear the non-page, non-alignment bits from the address */
1513 if (TCG_TARGET_REG_BITS == 32) {
1514 /* We don't support unaligned accesses on 32-bits.
1515 * Preserve the bottom bits and thus trigger a comparison
1516 * failure on unaligned accesses.
1517 */
1518 if (a_bits < s_bits) {
1519 a_bits = s_bits;
1520 }
1521 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1522 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1523 } else {
1524 TCGReg t = addrlo;
1525
1526 /* If the access is unaligned, we need to make sure we fail if we
1527 * cross a page boundary. The trick is to add the access size-1
1528 * to the address before masking the low bits. That will make the
1529 * address overflow to the next page if we cross a page boundary,
1530 * which will then force a mismatch of the TLB compare.
1531 */
1532 if (a_bits < s_bits) {
1533 unsigned a_mask = (1 << a_bits) - 1;
1534 unsigned s_mask = (1 << s_bits) - 1;
1535 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1536 t = TCG_REG_R0;
1537 }
1538
1539 /* Mask the address for the requested alignment. */
1540 if (TARGET_LONG_BITS == 32) {
1541 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1542 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1543 } else if (a_bits == 0) {
1544 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1545 } else {
1546 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1547 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
1548 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1549 }
1550 }
1551
1552 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1553 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1554 0, 7, TCG_TYPE_I32);
1555 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1556 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1557 } else {
1558 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1559 0, 7, TCG_TYPE_TL);
1560 }
1561
1562 return addrlo;
1563 }
1564
1565 /* Record the context of a call to the out of line helper code for the slow
1566 path for a load or store, so that we can later generate the correct
1567 helper code. */
1568 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1569 TCGReg datalo_reg, TCGReg datahi_reg,
1570 TCGReg addrlo_reg, TCGReg addrhi_reg,
1571 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
1572 {
1573 TCGLabelQemuLdst *label = new_ldst_label(s);
1574
1575 label->is_ld = is_ld;
1576 label->oi = oi;
1577 label->datalo_reg = datalo_reg;
1578 label->datahi_reg = datahi_reg;
1579 label->addrlo_reg = addrlo_reg;
1580 label->addrhi_reg = addrhi_reg;
1581 label->raddr = raddr;
1582 label->label_ptr[0] = lptr;
1583 }
1584
1585 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1586 {
1587 TCGMemOpIdx oi = lb->oi;
1588 TCGMemOp opc = get_memop(oi);
1589 TCGReg hi, lo, arg = TCG_REG_R3;
1590
1591 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1592
1593 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1594
1595 lo = lb->addrlo_reg;
1596 hi = lb->addrhi_reg;
1597 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1598 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1599 arg |= 1;
1600 #endif
1601 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1602 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1603 } else {
1604 /* If the address needed to be zero-extended, we'll have already
1605 placed it in R4. The only remaining case is 64-bit guest. */
1606 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1607 }
1608
1609 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1610 tcg_out32(s, MFSPR | RT(arg) | LR);
1611
1612 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1613
1614 lo = lb->datalo_reg;
1615 hi = lb->datahi_reg;
1616 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1617 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1618 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1619 } else if (opc & MO_SIGN) {
1620 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1621 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
1622 } else {
1623 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
1624 }
1625
1626 tcg_out_b(s, 0, lb->raddr);
1627 }
1628
1629 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1630 {
1631 TCGMemOpIdx oi = lb->oi;
1632 TCGMemOp opc = get_memop(oi);
1633 TCGMemOp s_bits = opc & MO_SIZE;
1634 TCGReg hi, lo, arg = TCG_REG_R3;
1635
1636 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1637
1638 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1639
1640 lo = lb->addrlo_reg;
1641 hi = lb->addrhi_reg;
1642 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1643 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1644 arg |= 1;
1645 #endif
1646 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1647 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1648 } else {
1649 /* If the address needed to be zero-extended, we'll have already
1650 placed it in R4. The only remaining case is 64-bit guest. */
1651 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1652 }
1653
1654 lo = lb->datalo_reg;
1655 hi = lb->datahi_reg;
1656 if (TCG_TARGET_REG_BITS == 32) {
1657 switch (s_bits) {
1658 case MO_64:
1659 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1660 arg |= 1;
1661 #endif
1662 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1663 /* FALLTHRU */
1664 case MO_32:
1665 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1666 break;
1667 default:
1668 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1669 break;
1670 }
1671 } else {
1672 if (s_bits == MO_64) {
1673 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1674 } else {
1675 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1676 }
1677 }
1678
1679 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1680 tcg_out32(s, MFSPR | RT(arg) | LR);
1681
1682 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1683
1684 tcg_out_b(s, 0, lb->raddr);
1685 }
1686 #endif /* SOFTMMU */
1687
1688 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1689 {
1690 TCGReg datalo, datahi, addrlo, rbase;
1691 TCGReg addrhi __attribute__((unused));
1692 TCGMemOpIdx oi;
1693 TCGMemOp opc, s_bits;
1694 #ifdef CONFIG_SOFTMMU
1695 int mem_index;
1696 tcg_insn_unit *label_ptr;
1697 #endif
1698
1699 datalo = *args++;
1700 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1701 addrlo = *args++;
1702 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1703 oi = *args++;
1704 opc = get_memop(oi);
1705 s_bits = opc & MO_SIZE;
1706
1707 #ifdef CONFIG_SOFTMMU
1708 mem_index = get_mmuidx(oi);
1709 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
1710
1711 /* Load a pointer into the current opcode w/conditional branch-link. */
1712 label_ptr = s->code_ptr;
1713 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1714
1715 rbase = TCG_REG_R3;
1716 #else /* !CONFIG_SOFTMMU */
1717 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1718 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1719 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1720 addrlo = TCG_REG_TMP1;
1721 }
1722 #endif
1723
1724 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1725 if (opc & MO_BSWAP) {
1726 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1727 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1728 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1729 } else if (rbase != 0) {
1730 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1731 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1732 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1733 } else if (addrlo == datahi) {
1734 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1735 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1736 } else {
1737 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1738 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1739 }
1740 } else {
1741 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
1742 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1743 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1744 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1745 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1746 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1747 } else if (insn) {
1748 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1749 } else {
1750 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1751 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1752 insn = qemu_exts_opc[s_bits];
1753 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1754 }
1755 }
1756
1757 #ifdef CONFIG_SOFTMMU
1758 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1759 s->code_ptr, label_ptr);
1760 #endif
1761 }
1762
1763 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1764 {
1765 TCGReg datalo, datahi, addrlo, rbase;
1766 TCGReg addrhi __attribute__((unused));
1767 TCGMemOpIdx oi;
1768 TCGMemOp opc, s_bits;
1769 #ifdef CONFIG_SOFTMMU
1770 int mem_index;
1771 tcg_insn_unit *label_ptr;
1772 #endif
1773
1774 datalo = *args++;
1775 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1776 addrlo = *args++;
1777 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1778 oi = *args++;
1779 opc = get_memop(oi);
1780 s_bits = opc & MO_SIZE;
1781
1782 #ifdef CONFIG_SOFTMMU
1783 mem_index = get_mmuidx(oi);
1784 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
1785
1786 /* Load a pointer into the current opcode w/conditional branch-link. */
1787 label_ptr = s->code_ptr;
1788 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1789
1790 rbase = TCG_REG_R3;
1791 #else /* !CONFIG_SOFTMMU */
1792 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1793 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1794 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1795 addrlo = TCG_REG_TMP1;
1796 }
1797 #endif
1798
1799 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1800 if (opc & MO_BSWAP) {
1801 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1802 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1803 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1804 } else if (rbase != 0) {
1805 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1806 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1807 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1808 } else {
1809 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1810 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1811 }
1812 } else {
1813 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
1814 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1815 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1816 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
1817 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
1818 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
1819 } else {
1820 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1821 }
1822 }
1823
1824 #ifdef CONFIG_SOFTMMU
1825 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1826 s->code_ptr, label_ptr);
1827 #endif
1828 }
1829
1830 /* Parameters for function call generation, used in tcg.c. */
1831 #define TCG_TARGET_STACK_ALIGN 16
1832 #define TCG_TARGET_EXTEND_ARGS 1
1833
1834 #ifdef _CALL_AIX
1835 # define LINK_AREA_SIZE (6 * SZR)
1836 # define LR_OFFSET (1 * SZR)
1837 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1838 #elif defined(TCG_TARGET_CALL_DARWIN)
1839 # define LINK_AREA_SIZE (6 * SZR)
1840 # define LR_OFFSET (2 * SZR)
1841 #elif TCG_TARGET_REG_BITS == 64
1842 # if defined(_CALL_ELF) && _CALL_ELF == 2
1843 # define LINK_AREA_SIZE (4 * SZR)
1844 # define LR_OFFSET (1 * SZR)
1845 # endif
1846 #else /* TCG_TARGET_REG_BITS == 32 */
1847 # if defined(_CALL_SYSV)
1848 # define LINK_AREA_SIZE (2 * SZR)
1849 # define LR_OFFSET (1 * SZR)
1850 # endif
1851 #endif
1852 #ifndef LR_OFFSET
1853 # error "Unhandled abi"
1854 #endif
1855 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1856 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1857 #endif
1858
1859 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1860 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1861
1862 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1863 + TCG_STATIC_CALL_ARGS_SIZE \
1864 + CPU_TEMP_BUF_SIZE \
1865 + REG_SAVE_SIZE \
1866 + TCG_TARGET_STACK_ALIGN - 1) \
1867 & -TCG_TARGET_STACK_ALIGN)
1868
1869 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1870
1871 static void tcg_target_qemu_prologue(TCGContext *s)
1872 {
1873 int i;
1874
1875 #ifdef _CALL_AIX
1876 void **desc = (void **)s->code_ptr;
1877 desc[0] = desc + 2; /* entry point */
1878 desc[1] = 0; /* environment pointer */
1879 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1880 #endif
1881
1882 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1883 CPU_TEMP_BUF_SIZE);
1884
1885 /* Prologue */
1886 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1887 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1888 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1889
1890 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1891 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1892 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1893 }
1894 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1895
1896 #ifndef CONFIG_SOFTMMU
1897 if (guest_base) {
1898 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1899 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1900 }
1901 #endif
1902
1903 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1904 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1905
1906 if (USE_REG_RA) {
1907 #ifdef _CALL_AIX
1908 /* Make the caller load the value as the TOC into R2. */
1909 tb_ret_addr = s->code_ptr + 2;
1910 desc[1] = tb_ret_addr;
1911 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1912 tcg_out32(s, BCCTR | BO_ALWAYS);
1913 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1914 /* Compute from the incoming R12 value. */
1915 tb_ret_addr = s->code_ptr + 2;
1916 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1917 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1918 tcg_out32(s, BCCTR | BO_ALWAYS);
1919 #else
1920 /* Reserve max 5 insns for the constant load. */
1921 tb_ret_addr = s->code_ptr + 6;
1922 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1923 tcg_out32(s, BCCTR | BO_ALWAYS);
1924 while (s->code_ptr < tb_ret_addr) {
1925 tcg_out32(s, NOP);
1926 }
1927 #endif
1928 } else {
1929 tcg_out32(s, BCCTR | BO_ALWAYS);
1930 tb_ret_addr = s->code_ptr;
1931 }
1932
1933 /* Epilogue */
1934 tcg_debug_assert(tb_ret_addr == s->code_ptr);
1935
1936 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1937 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1938 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1939 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1940 }
1941 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1942 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1943 tcg_out32(s, BCLR | BO_ALWAYS);
1944 }
1945
1946 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1947 const int *const_args)
1948 {
1949 TCGArg a0, a1, a2;
1950 int c;
1951
1952 switch (opc) {
1953 case INDEX_op_exit_tb:
1954 if (USE_REG_RA) {
1955 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1956
1957 /* Use a direct branch if we can, otherwise use the value in RA.
1958 Note that the direct branch is always backward, thus we need
1959 to account for the possibility of 5 insns from the movi. */
1960 if (!in_range_b(disp - 20)) {
1961 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1962 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1963 tcg_out32(s, BCCTR | BO_ALWAYS);
1964 break;
1965 }
1966 }
1967 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1968 tcg_out_b(s, 0, tb_ret_addr);
1969 break;
1970 case INDEX_op_goto_tb:
1971 tcg_debug_assert(s->tb_jmp_insn_offset);
1972 /* Direct jump. */
1973 #ifdef __powerpc64__
1974 /* Ensure the next insns are 8-byte aligned. */
1975 if ((uintptr_t)s->code_ptr & 7) {
1976 tcg_out32(s, NOP);
1977 }
1978 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
1979 /* To be replaced by either a branch+nop or a load into TMP1. */
1980 s->code_ptr += 2;
1981 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
1982 tcg_out32(s, BCCTR | BO_ALWAYS);
1983 #else
1984 /* To be replaced by a branch. */
1985 s->code_ptr++;
1986 #endif
1987 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
1988 break;
1989 case INDEX_op_br:
1990 {
1991 TCGLabel *l = arg_label(args[0]);
1992
1993 if (l->has_value) {
1994 tcg_out_b(s, 0, l->u.value_ptr);
1995 } else {
1996 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
1997 tcg_out_b_noaddr(s, B);
1998 }
1999 }
2000 break;
2001 case INDEX_op_ld8u_i32:
2002 case INDEX_op_ld8u_i64:
2003 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2004 break;
2005 case INDEX_op_ld8s_i32:
2006 case INDEX_op_ld8s_i64:
2007 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2008 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
2009 break;
2010 case INDEX_op_ld16u_i32:
2011 case INDEX_op_ld16u_i64:
2012 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
2013 break;
2014 case INDEX_op_ld16s_i32:
2015 case INDEX_op_ld16s_i64:
2016 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
2017 break;
2018 case INDEX_op_ld_i32:
2019 case INDEX_op_ld32u_i64:
2020 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
2021 break;
2022 case INDEX_op_ld32s_i64:
2023 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
2024 break;
2025 case INDEX_op_ld_i64:
2026 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
2027 break;
2028 case INDEX_op_st8_i32:
2029 case INDEX_op_st8_i64:
2030 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
2031 break;
2032 case INDEX_op_st16_i32:
2033 case INDEX_op_st16_i64:
2034 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
2035 break;
2036 case INDEX_op_st_i32:
2037 case INDEX_op_st32_i64:
2038 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
2039 break;
2040 case INDEX_op_st_i64:
2041 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
2042 break;
2043
2044 case INDEX_op_add_i32:
2045 a0 = args[0], a1 = args[1], a2 = args[2];
2046 if (const_args[2]) {
2047 do_addi_32:
2048 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
2049 } else {
2050 tcg_out32(s, ADD | TAB(a0, a1, a2));
2051 }
2052 break;
2053 case INDEX_op_sub_i32:
2054 a0 = args[0], a1 = args[1], a2 = args[2];
2055 if (const_args[1]) {
2056 if (const_args[2]) {
2057 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2058 } else {
2059 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2060 }
2061 } else if (const_args[2]) {
2062 a2 = -a2;
2063 goto do_addi_32;
2064 } else {
2065 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2066 }
2067 break;
2068
2069 case INDEX_op_and_i32:
2070 a0 = args[0], a1 = args[1], a2 = args[2];
2071 if (const_args[2]) {
2072 tcg_out_andi32(s, a0, a1, a2);
2073 } else {
2074 tcg_out32(s, AND | SAB(a1, a0, a2));
2075 }
2076 break;
2077 case INDEX_op_and_i64:
2078 a0 = args[0], a1 = args[1], a2 = args[2];
2079 if (const_args[2]) {
2080 tcg_out_andi64(s, a0, a1, a2);
2081 } else {
2082 tcg_out32(s, AND | SAB(a1, a0, a2));
2083 }
2084 break;
2085 case INDEX_op_or_i64:
2086 case INDEX_op_or_i32:
2087 a0 = args[0], a1 = args[1], a2 = args[2];
2088 if (const_args[2]) {
2089 tcg_out_ori32(s, a0, a1, a2);
2090 } else {
2091 tcg_out32(s, OR | SAB(a1, a0, a2));
2092 }
2093 break;
2094 case INDEX_op_xor_i64:
2095 case INDEX_op_xor_i32:
2096 a0 = args[0], a1 = args[1], a2 = args[2];
2097 if (const_args[2]) {
2098 tcg_out_xori32(s, a0, a1, a2);
2099 } else {
2100 tcg_out32(s, XOR | SAB(a1, a0, a2));
2101 }
2102 break;
2103 case INDEX_op_andc_i32:
2104 a0 = args[0], a1 = args[1], a2 = args[2];
2105 if (const_args[2]) {
2106 tcg_out_andi32(s, a0, a1, ~a2);
2107 } else {
2108 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2109 }
2110 break;
2111 case INDEX_op_andc_i64:
2112 a0 = args[0], a1 = args[1], a2 = args[2];
2113 if (const_args[2]) {
2114 tcg_out_andi64(s, a0, a1, ~a2);
2115 } else {
2116 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2117 }
2118 break;
2119 case INDEX_op_orc_i32:
2120 if (const_args[2]) {
2121 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2122 break;
2123 }
2124 /* FALLTHRU */
2125 case INDEX_op_orc_i64:
2126 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2127 break;
2128 case INDEX_op_eqv_i32:
2129 if (const_args[2]) {
2130 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2131 break;
2132 }
2133 /* FALLTHRU */
2134 case INDEX_op_eqv_i64:
2135 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2136 break;
2137 case INDEX_op_nand_i32:
2138 case INDEX_op_nand_i64:
2139 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2140 break;
2141 case INDEX_op_nor_i32:
2142 case INDEX_op_nor_i64:
2143 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2144 break;
2145
2146 case INDEX_op_clz_i32:
2147 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2148 args[2], const_args[2]);
2149 break;
2150 case INDEX_op_ctz_i32:
2151 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2152 args[2], const_args[2]);
2153 break;
2154 case INDEX_op_ctpop_i32:
2155 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2156 break;
2157
2158 case INDEX_op_clz_i64:
2159 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2160 args[2], const_args[2]);
2161 break;
2162 case INDEX_op_ctz_i64:
2163 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2164 args[2], const_args[2]);
2165 break;
2166 case INDEX_op_ctpop_i64:
2167 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2168 break;
2169
2170 case INDEX_op_mul_i32:
2171 a0 = args[0], a1 = args[1], a2 = args[2];
2172 if (const_args[2]) {
2173 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2174 } else {
2175 tcg_out32(s, MULLW | TAB(a0, a1, a2));
2176 }
2177 break;
2178
2179 case INDEX_op_div_i32:
2180 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
2181 break;
2182
2183 case INDEX_op_divu_i32:
2184 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
2185 break;
2186
2187 case INDEX_op_shl_i32:
2188 if (const_args[2]) {
2189 tcg_out_shli32(s, args[0], args[1], args[2]);
2190 } else {
2191 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
2192 }
2193 break;
2194 case INDEX_op_shr_i32:
2195 if (const_args[2]) {
2196 tcg_out_shri32(s, args[0], args[1], args[2]);
2197 } else {
2198 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
2199 }
2200 break;
2201 case INDEX_op_sar_i32:
2202 if (const_args[2]) {
2203 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2204 } else {
2205 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2206 }
2207 break;
2208 case INDEX_op_rotl_i32:
2209 if (const_args[2]) {
2210 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2211 } else {
2212 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2213 | MB(0) | ME(31));
2214 }
2215 break;
2216 case INDEX_op_rotr_i32:
2217 if (const_args[2]) {
2218 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2219 } else {
2220 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2221 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
2222 | MB(0) | ME(31));
2223 }
2224 break;
2225
2226 case INDEX_op_brcond_i32:
2227 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2228 arg_label(args[3]), TCG_TYPE_I32);
2229 break;
2230 case INDEX_op_brcond_i64:
2231 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2232 arg_label(args[3]), TCG_TYPE_I64);
2233 break;
2234 case INDEX_op_brcond2_i32:
2235 tcg_out_brcond2(s, args, const_args);
2236 break;
2237
2238 case INDEX_op_neg_i32:
2239 case INDEX_op_neg_i64:
2240 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
2241 break;
2242
2243 case INDEX_op_not_i32:
2244 case INDEX_op_not_i64:
2245 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
2246 break;
2247
2248 case INDEX_op_add_i64:
2249 a0 = args[0], a1 = args[1], a2 = args[2];
2250 if (const_args[2]) {
2251 do_addi_64:
2252 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
2253 } else {
2254 tcg_out32(s, ADD | TAB(a0, a1, a2));
2255 }
2256 break;
2257 case INDEX_op_sub_i64:
2258 a0 = args[0], a1 = args[1], a2 = args[2];
2259 if (const_args[1]) {
2260 if (const_args[2]) {
2261 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2262 } else {
2263 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2264 }
2265 } else if (const_args[2]) {
2266 a2 = -a2;
2267 goto do_addi_64;
2268 } else {
2269 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2270 }
2271 break;
2272
2273 case INDEX_op_shl_i64:
2274 if (const_args[2]) {
2275 tcg_out_shli64(s, args[0], args[1], args[2]);
2276 } else {
2277 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2278 }
2279 break;
2280 case INDEX_op_shr_i64:
2281 if (const_args[2]) {
2282 tcg_out_shri64(s, args[0], args[1], args[2]);
2283 } else {
2284 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2285 }
2286 break;
2287 case INDEX_op_sar_i64:
2288 if (const_args[2]) {
2289 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2290 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2291 } else {
2292 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
2293 }
2294 break;
2295 case INDEX_op_rotl_i64:
2296 if (const_args[2]) {
2297 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2298 } else {
2299 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2300 }
2301 break;
2302 case INDEX_op_rotr_i64:
2303 if (const_args[2]) {
2304 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2305 } else {
2306 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2307 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
2308 }
2309 break;
2310
2311 case INDEX_op_mul_i64:
2312 a0 = args[0], a1 = args[1], a2 = args[2];
2313 if (const_args[2]) {
2314 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2315 } else {
2316 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2317 }
2318 break;
2319 case INDEX_op_div_i64:
2320 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
2321 break;
2322 case INDEX_op_divu_i64:
2323 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
2324 break;
2325
2326 case INDEX_op_qemu_ld_i32:
2327 tcg_out_qemu_ld(s, args, false);
2328 break;
2329 case INDEX_op_qemu_ld_i64:
2330 tcg_out_qemu_ld(s, args, true);
2331 break;
2332 case INDEX_op_qemu_st_i32:
2333 tcg_out_qemu_st(s, args, false);
2334 break;
2335 case INDEX_op_qemu_st_i64:
2336 tcg_out_qemu_st(s, args, true);
2337 break;
2338
2339 case INDEX_op_ext8s_i32:
2340 case INDEX_op_ext8s_i64:
2341 c = EXTSB;
2342 goto gen_ext;
2343 case INDEX_op_ext16s_i32:
2344 case INDEX_op_ext16s_i64:
2345 c = EXTSH;
2346 goto gen_ext;
2347 case INDEX_op_ext_i32_i64:
2348 case INDEX_op_ext32s_i64:
2349 c = EXTSW;
2350 goto gen_ext;
2351 gen_ext:
2352 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
2353 break;
2354 case INDEX_op_extu_i32_i64:
2355 tcg_out_ext32u(s, args[0], args[1]);
2356 break;
2357
2358 case INDEX_op_setcond_i32:
2359 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2360 const_args[2]);
2361 break;
2362 case INDEX_op_setcond_i64:
2363 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2364 const_args[2]);
2365 break;
2366 case INDEX_op_setcond2_i32:
2367 tcg_out_setcond2(s, args, const_args);
2368 break;
2369
2370 case INDEX_op_bswap16_i32:
2371 case INDEX_op_bswap16_i64:
2372 a0 = args[0], a1 = args[1];
2373 /* a1 = abcd */
2374 if (a0 != a1) {
2375 /* a0 = (a1 r<< 24) & 0xff # 000c */
2376 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2377 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2378 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2379 } else {
2380 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2381 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2382 /* a0 = (a1 r<< 24) & 0xff # 000c */
2383 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2384 /* a0 = a0 | r0 # 00dc */
2385 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2386 }
2387 break;
2388
2389 case INDEX_op_bswap32_i32:
2390 case INDEX_op_bswap32_i64:
2391 /* Stolen from gcc's builtin_bswap32 */
2392 a1 = args[1];
2393 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2394
2395 /* a1 = args[1] # abcd */
2396 /* a0 = rotate_left (a1, 8) # bcda */
2397 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2398 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2399 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2400 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2401 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2402
2403 if (a0 == TCG_REG_R0) {
2404 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2405 }
2406 break;
2407
2408 case INDEX_op_bswap64_i64:
2409 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
2410 if (a0 == a1) {
2411 a0 = TCG_REG_R0;
2412 a2 = a1;
2413 }
2414
2415 /* a1 = # abcd efgh */
2416 /* a0 = rl32(a1, 8) # 0000 fghe */
2417 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2418 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2419 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2420 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2421 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2422
2423 /* a0 = rl64(a0, 32) # hgfe 0000 */
2424 /* a2 = rl64(a1, 32) # efgh abcd */
2425 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2426 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2427
2428 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2429 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2430 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2431 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2432 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2433 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2434
2435 if (a0 == 0) {
2436 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2437 }
2438 break;
2439
2440 case INDEX_op_deposit_i32:
2441 if (const_args[2]) {
2442 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2443 tcg_out_andi32(s, args[0], args[0], ~mask);
2444 } else {
2445 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2446 32 - args[3] - args[4], 31 - args[3]);
2447 }
2448 break;
2449 case INDEX_op_deposit_i64:
2450 if (const_args[2]) {
2451 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2452 tcg_out_andi64(s, args[0], args[0], ~mask);
2453 } else {
2454 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2455 64 - args[3] - args[4]);
2456 }
2457 break;
2458
2459 case INDEX_op_extract_i32:
2460 tcg_out_rlw(s, RLWINM, args[0], args[1],
2461 32 - args[2], 32 - args[3], 31);
2462 break;
2463 case INDEX_op_extract_i64:
2464 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2465 break;
2466
2467 case INDEX_op_movcond_i32:
2468 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2469 args[3], args[4], const_args[2]);
2470 break;
2471 case INDEX_op_movcond_i64:
2472 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2473 args[3], args[4], const_args[2]);
2474 break;
2475
2476 #if TCG_TARGET_REG_BITS == 64
2477 case INDEX_op_add2_i64:
2478 #else
2479 case INDEX_op_add2_i32:
2480 #endif
2481 /* Note that the CA bit is defined based on the word size of the
2482 environment. So in 64-bit mode it's always carry-out of bit 63.
2483 The fallback code using deposit works just as well for 32-bit. */
2484 a0 = args[0], a1 = args[1];
2485 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
2486 a0 = TCG_REG_R0;
2487 }
2488 if (const_args[4]) {
2489 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
2490 } else {
2491 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
2492 }
2493 if (const_args[5]) {
2494 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
2495 } else {
2496 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
2497 }
2498 if (a0 != args[0]) {
2499 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2500 }
2501 break;
2502
2503 #if TCG_TARGET_REG_BITS == 64
2504 case INDEX_op_sub2_i64:
2505 #else
2506 case INDEX_op_sub2_i32:
2507 #endif
2508 a0 = args[0], a1 = args[1];
2509 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
2510 a0 = TCG_REG_R0;
2511 }
2512 if (const_args[2]) {
2513 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
2514 } else {
2515 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
2516 }
2517 if (const_args[3]) {
2518 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2519 } else {
2520 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
2521 }
2522 if (a0 != args[0]) {
2523 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2524 }
2525 break;
2526
2527 case INDEX_op_muluh_i32:
2528 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2529 break;
2530 case INDEX_op_mulsh_i32:
2531 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2532 break;
2533 case INDEX_op_muluh_i64:
2534 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2535 break;
2536 case INDEX_op_mulsh_i64:
2537 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2538 break;
2539
2540 case INDEX_op_mb:
2541 tcg_out_mb(s, args[0]);
2542 break;
2543
2544 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2545 case INDEX_op_mov_i64:
2546 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2547 case INDEX_op_movi_i64:
2548 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2549 default:
2550 tcg_abort();
2551 }
2552 }
2553
2554 static const TCGTargetOpDef ppc_op_defs[] = {
2555 { INDEX_op_exit_tb, { } },
2556 { INDEX_op_goto_tb, { } },
2557 { INDEX_op_br, { } },
2558
2559 { INDEX_op_ld8u_i32, { "r", "r" } },
2560 { INDEX_op_ld8s_i32, { "r", "r" } },
2561 { INDEX_op_ld16u_i32, { "r", "r" } },
2562 { INDEX_op_ld16s_i32, { "r", "r" } },
2563 { INDEX_op_ld_i32, { "r", "r" } },
2564
2565 { INDEX_op_st8_i32, { "r", "r" } },
2566 { INDEX_op_st16_i32, { "r", "r" } },
2567 { INDEX_op_st_i32, { "r", "r" } },
2568
2569 { INDEX_op_add_i32, { "r", "r", "ri" } },
2570 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2571 { INDEX_op_div_i32, { "r", "r", "r" } },
2572 { INDEX_op_divu_i32, { "r", "r", "r" } },
2573 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2574 { INDEX_op_and_i32, { "r", "r", "ri" } },
2575 { INDEX_op_or_i32, { "r", "r", "ri" } },
2576 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2577 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2578 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2579 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2580 { INDEX_op_nand_i32, { "r", "r", "r" } },
2581 { INDEX_op_nor_i32, { "r", "r", "r" } },
2582 { INDEX_op_clz_i32, { "r", "r", "rZW" } },
2583 { INDEX_op_ctz_i32, { "r", "r", "rZW" } },
2584 { INDEX_op_ctpop_i32, { "r", "r" } },
2585
2586 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2587 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2588 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2589 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2590 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2591
2592 { INDEX_op_neg_i32, { "r", "r" } },
2593 { INDEX_op_not_i32, { "r", "r" } },
2594 { INDEX_op_ext8s_i32, { "r", "r" } },
2595 { INDEX_op_ext16s_i32, { "r", "r" } },
2596 { INDEX_op_bswap16_i32, { "r", "r" } },
2597 { INDEX_op_bswap32_i32, { "r", "r" } },
2598
2599 { INDEX_op_brcond_i32, { "r", "ri" } },
2600 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2601 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2602
2603 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2604 { INDEX_op_extract_i32, { "r", "r" } },
2605
2606 { INDEX_op_muluh_i32, { "r", "r", "r" } },
2607 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
2608
2609 #if TCG_TARGET_REG_BITS == 64
2610 { INDEX_op_ld8u_i64, { "r", "r" } },
2611 { INDEX_op_ld8s_i64, { "r", "r" } },
2612 { INDEX_op_ld16u_i64, { "r", "r" } },
2613 { INDEX_op_ld16s_i64, { "r", "r" } },
2614 { INDEX_op_ld32u_i64, { "r", "r" } },
2615 { INDEX_op_ld32s_i64, { "r", "r" } },
2616 { INDEX_op_ld_i64, { "r", "r" } },
2617
2618 { INDEX_op_st8_i64, { "r", "r" } },
2619 { INDEX_op_st16_i64, { "r", "r" } },
2620 { INDEX_op_st32_i64, { "r", "r" } },
2621 { INDEX_op_st_i64, { "r", "r" } },
2622
2623 { INDEX_op_add_i64, { "r", "r", "rT" } },
2624 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2625 { INDEX_op_and_i64, { "r", "r", "ri" } },
2626 { INDEX_op_or_i64, { "r", "r", "rU" } },
2627 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2628 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2629 { INDEX_op_orc_i64, { "r", "r", "r" } },
2630 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2631 { INDEX_op_nand_i64, { "r", "r", "r" } },
2632 { INDEX_op_nor_i64, { "r", "r", "r" } },
2633 { INDEX_op_clz_i64, { "r", "r", "rZW" } },
2634 { INDEX_op_ctz_i64, { "r", "r", "rZW" } },
2635 { INDEX_op_ctpop_i64, { "r", "r" } },
2636
2637 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2638 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2639 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2640 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2641 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2642
2643 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2644 { INDEX_op_div_i64, { "r", "r", "r" } },
2645 { INDEX_op_divu_i64, { "r", "r", "r" } },
2646
2647 { INDEX_op_neg_i64, { "r", "r" } },
2648 { INDEX_op_not_i64, { "r", "r" } },
2649 { INDEX_op_ext8s_i64, { "r", "r" } },
2650 { INDEX_op_ext16s_i64, { "r", "r" } },
2651 { INDEX_op_ext32s_i64, { "r", "r" } },
2652 { INDEX_op_ext_i32_i64, { "r", "r" } },
2653 { INDEX_op_extu_i32_i64, { "r", "r" } },
2654 { INDEX_op_bswap16_i64, { "r", "r" } },
2655 { INDEX_op_bswap32_i64, { "r", "r" } },
2656 { INDEX_op_bswap64_i64, { "r", "r" } },
2657
2658 { INDEX_op_brcond_i64, { "r", "ri" } },
2659 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2660 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2661
2662 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2663 { INDEX_op_extract_i64, { "r", "r" } },
2664
2665 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2666 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2667 #endif
2668
2669 #if TCG_TARGET_REG_BITS == 32
2670 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2671 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2672 #endif
2673
2674 #if TCG_TARGET_REG_BITS == 64
2675 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2676 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2677 #else
2678 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2679 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2680 #endif
2681
2682 #if TCG_TARGET_REG_BITS == 64
2683 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2684 { INDEX_op_qemu_st_i32, { "S", "S" } },
2685 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2686 { INDEX_op_qemu_st_i64, { "S", "S" } },
2687 #elif TARGET_LONG_BITS == 32
2688 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2689 { INDEX_op_qemu_st_i32, { "S", "S" } },
2690 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
2691 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2692 #else
2693 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2694 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
2695 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
2696 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2697 #endif
2698
2699 { INDEX_op_mb, { } },
2700 { -1 },
2701 };
2702
2703 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2704 {
2705 int i, n = ARRAY_SIZE(ppc_op_defs);
2706
2707 for (i = 0; i < n; ++i) {
2708 if (ppc_op_defs[i].op == op) {
2709 return &ppc_op_defs[i];
2710 }
2711 }
2712 return NULL;
2713 }
2714
2715 static void tcg_target_init(TCGContext *s)
2716 {
2717 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2718 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
2719
2720 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2721 have_isa_2_06 = true;
2722 }
2723 #ifdef PPC_FEATURE2_ARCH_3_00
2724 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
2725 have_isa_3_00 = true;
2726 }
2727 #endif
2728
2729 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2730 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2731 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2732 (1 << TCG_REG_R0) |
2733 (1 << TCG_REG_R2) |
2734 (1 << TCG_REG_R3) |
2735 (1 << TCG_REG_R4) |
2736 (1 << TCG_REG_R5) |
2737 (1 << TCG_REG_R6) |
2738 (1 << TCG_REG_R7) |
2739 (1 << TCG_REG_R8) |
2740 (1 << TCG_REG_R9) |
2741 (1 << TCG_REG_R10) |
2742 (1 << TCG_REG_R11) |
2743 (1 << TCG_REG_R12));
2744
2745 tcg_regset_clear(s->reserved_regs);
2746 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2747 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2748 #if defined(_CALL_SYSV)
2749 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
2750 #endif
2751 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2752 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2753 #endif
2754 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
2755 if (USE_REG_RA) {
2756 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2757 }
2758 }
2759
2760 #ifdef __ELF__
2761 typedef struct {
2762 DebugFrameCIE cie;
2763 DebugFrameFDEHeader fde;
2764 uint8_t fde_def_cfa[4];
2765 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2766 } DebugFrame;
2767
2768 /* We're expecting a 2 byte uleb128 encoded value. */
2769 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2770
2771 #if TCG_TARGET_REG_BITS == 64
2772 # define ELF_HOST_MACHINE EM_PPC64
2773 #else
2774 # define ELF_HOST_MACHINE EM_PPC
2775 #endif
2776
2777 static DebugFrame debug_frame = {
2778 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2779 .cie.id = -1,
2780 .cie.version = 1,
2781 .cie.code_align = 1,
2782 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2783 .cie.return_column = 65,
2784
2785 /* Total FDE size does not include the "len" member. */
2786 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2787
2788 .fde_def_cfa = {
2789 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2790 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2791 (FRAME_SIZE >> 7)
2792 },
2793 .fde_reg_ofs = {
2794 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2795 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2796 }
2797 };
2798
2799 void tcg_register_jit(void *buf, size_t buf_size)
2800 {
2801 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2802 int i;
2803
2804 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2805 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2806 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2807 }
2808
2809 debug_frame.fde.func_start = (uintptr_t)buf;
2810 debug_frame.fde.func_len = buf_size;
2811
2812 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2813 }
2814 #endif /* __ELF__ */
2815
2816 static size_t dcache_bsize = 16;
2817 static size_t icache_bsize = 16;
2818
2819 void flush_icache_range(uintptr_t start, uintptr_t stop)
2820 {
2821 uintptr_t p, start1, stop1;
2822 size_t dsize = dcache_bsize;
2823 size_t isize = icache_bsize;
2824
2825 start1 = start & ~(dsize - 1);
2826 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2827 for (p = start1; p < stop1; p += dsize) {
2828 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2829 }
2830 asm volatile ("sync" : : : "memory");
2831
2832 start &= start & ~(isize - 1);
2833 stop1 = (stop + isize - 1) & ~(isize - 1);
2834 for (p = start1; p < stop1; p += isize) {
2835 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2836 }
2837 asm volatile ("sync" : : : "memory");
2838 asm volatile ("isync" : : : "memory");
2839 }
2840
2841 #if defined _AIX
2842 #include <sys/systemcfg.h>
2843
2844 static void __attribute__((constructor)) tcg_cache_init(void)
2845 {
2846 icache_bsize = _system_configuration.icache_line;
2847 dcache_bsize = _system_configuration.dcache_line;
2848 }
2849
2850 #elif defined __linux__
2851 static void __attribute__((constructor)) tcg_cache_init(void)
2852 {
2853 unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE);
2854 unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE);
2855
2856 if (dsize == 0 || isize == 0) {
2857 if (dsize == 0) {
2858 fprintf(stderr, "getauxval AT_DCACHEBSIZE failed\n");
2859 }
2860 if (isize == 0) {
2861 fprintf(stderr, "getauxval AT_ICACHEBSIZE failed\n");
2862 }
2863 exit(1);
2864 }
2865 dcache_bsize = dsize;
2866 icache_bsize = isize;
2867 }
2868
2869 #elif defined __APPLE__
2870 #include <sys/sysctl.h>
2871
2872 static void __attribute__((constructor)) tcg_cache_init(void)
2873 {
2874 size_t len;
2875 unsigned cacheline;
2876 int name[2] = { CTL_HW, HW_CACHELINE };
2877
2878 len = sizeof(cacheline);
2879 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
2880 perror("sysctl CTL_HW HW_CACHELINE failed");
2881 exit(1);
2882 }
2883 dcache_bsize = cacheline;
2884 icache_bsize = cacheline;
2885 }
2886
2887 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2888 #include <sys/sysctl.h>
2889
2890 static void __attribute__((constructor)) tcg_cache_init(void)
2891 {
2892 size_t len = 4;
2893 unsigned cacheline;
2894
2895 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
2896 fprintf(stderr, "sysctlbyname machdep.cacheline_size failed: %s\n",
2897 strerror(errno));
2898 exit(1);
2899 }
2900 dcache_bsize = cacheline;
2901 icache_bsize = cacheline;
2902 }
2903 #endif
AR7 emulation for QEMU