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tests/tcg: target/mips: Amend tests for MSA int dot product instructions
[qemu/ar7.git] / memory.c
blob0a089a73ae1a409d314cb84384490951d83a5e32
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "cpu.h"
19 #include "exec/memory.h"
20 #include "exec/address-spaces.h"
21 #include "qapi/visitor.h"
22 #include "qemu/bitops.h"
23 #include "qemu/error-report.h"
24 #include "qemu/qemu-print.h"
25 #include "qom/object.h"
26 #include "trace-root.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/tcg.h"
33 #include "hw/qdev-properties.h"
34 #include "migration/vmstate.h"
35
36 //#define DEBUG_UNASSIGNED
37
38 static unsigned memory_region_transaction_depth;
39 static bool memory_region_update_pending;
40 static bool ioeventfd_update_pending;
41 static bool global_dirty_log = false;
42
43 static QTAILQ_HEAD(, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
45
46 static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
49 static GHashTable *flat_views;
50
51 typedef struct AddrRange AddrRange;
52
53 /*
54 * Note that signed integers are needed for negative offsetting in aliases
55 * (large MemoryRegion::alias_offset).
56 */
57 struct AddrRange {
58 Int128 start;
59 Int128 size;
60 };
61
62 static AddrRange addrrange_make(Int128 start, Int128 size)
63 {
64 return (AddrRange) { start, size };
65 }
66
67 static bool addrrange_equal(AddrRange r1, AddrRange r2)
68 {
69 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
70 }
71
72 static Int128 addrrange_end(AddrRange r)
73 {
74 return int128_add(r.start, r.size);
75 }
76
77 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
78 {
79 int128_addto(&range.start, delta);
80 return range;
81 }
82
83 static bool addrrange_contains(AddrRange range, Int128 addr)
84 {
85 return int128_ge(addr, range.start)
86 && int128_lt(addr, addrrange_end(range));
87 }
88
89 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
90 {
91 return addrrange_contains(r1, r2.start)
92 || addrrange_contains(r2, r1.start);
93 }
94
95 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
96 {
97 Int128 start = int128_max(r1.start, r2.start);
98 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
99 return addrrange_make(start, int128_sub(end, start));
100 }
101
102 enum ListenerDirection { Forward, Reverse };
103
104 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
105 do { \
106 MemoryListener *_listener; \
107 \
108 switch (_direction) { \
109 case Forward: \
110 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
114 } \
115 break; \
116 case Reverse: \
117 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
128 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
129 do { \
130 MemoryListener *_listener; \
131 \
132 switch (_direction) { \
133 case Forward: \
134 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
135 if (_listener->_callback) { \
136 _listener->_callback(_listener, _section, ##_args); \
137 } \
138 } \
139 break; \
140 case Reverse: \
141 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
142 if (_listener->_callback) { \
143 _listener->_callback(_listener, _section, ##_args); \
144 } \
145 } \
146 break; \
147 default: \
148 abort(); \
149 } \
150 } while (0)
151
152 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
153 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
154 do { \
155 MemoryRegionSection mrs = section_from_flat_range(fr, \
156 address_space_to_flatview(as)); \
157 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
158 } while(0)
159
160 struct CoalescedMemoryRange {
161 AddrRange addr;
162 QTAILQ_ENTRY(CoalescedMemoryRange) link;
163 };
164
165 struct MemoryRegionIoeventfd {
166 AddrRange addr;
167 bool match_data;
168 uint64_t data;
169 EventNotifier *e;
170 };
171
172 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
173 MemoryRegionIoeventfd *b)
174 {
175 if (int128_lt(a->addr.start, b->addr.start)) {
176 return true;
177 } else if (int128_gt(a->addr.start, b->addr.start)) {
178 return false;
179 } else if (int128_lt(a->addr.size, b->addr.size)) {
180 return true;
181 } else if (int128_gt(a->addr.size, b->addr.size)) {
182 return false;
183 } else if (a->match_data < b->match_data) {
184 return true;
185 } else if (a->match_data > b->match_data) {
186 return false;
187 } else if (a->match_data) {
188 if (a->data < b->data) {
189 return true;
190 } else if (a->data > b->data) {
191 return false;
192 }
193 }
194 if (a->e < b->e) {
195 return true;
196 } else if (a->e > b->e) {
197 return false;
198 }
199 return false;
200 }
201
202 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
203 MemoryRegionIoeventfd *b)
204 {
205 return !memory_region_ioeventfd_before(a, b)
206 && !memory_region_ioeventfd_before(b, a);
207 }
208
209 /* Range of memory in the global map. Addresses are absolute. */
210 struct FlatRange {
211 MemoryRegion *mr;
212 hwaddr offset_in_region;
213 AddrRange addr;
214 uint8_t dirty_log_mask;
215 bool romd_mode;
216 bool readonly;
217 bool nonvolatile;
218 int has_coalesced_range;
219 };
220
221 #define FOR_EACH_FLAT_RANGE(var, view) \
222 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
223
224 static inline MemoryRegionSection
225 section_from_flat_range(FlatRange *fr, FlatView *fv)
226 {
227 return (MemoryRegionSection) {
228 .mr = fr->mr,
229 .fv = fv,
230 .offset_within_region = fr->offset_in_region,
231 .size = fr->addr.size,
232 .offset_within_address_space = int128_get64(fr->addr.start),
233 .readonly = fr->readonly,
234 .nonvolatile = fr->nonvolatile,
235 };
236 }
237
238 static bool flatrange_equal(FlatRange *a, FlatRange *b)
239 {
240 return a->mr == b->mr
241 && addrrange_equal(a->addr, b->addr)
242 && a->offset_in_region == b->offset_in_region
243 && a->romd_mode == b->romd_mode
244 && a->readonly == b->readonly
245 && a->nonvolatile == b->nonvolatile;
246 }
247
248 static FlatView *flatview_new(MemoryRegion *mr_root)
249 {
250 FlatView *view;
251
252 view = g_new0(FlatView, 1);
253 view->ref = 1;
254 view->root = mr_root;
255 memory_region_ref(mr_root);
256 trace_flatview_new(view, mr_root);
257
258 return view;
259 }
260
261 /* Insert a range into a given position. Caller is responsible for maintaining
262 * sorting order.
263 */
264 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
265 {
266 if (view->nr == view->nr_allocated) {
267 view->nr_allocated = MAX(2 * view->nr, 10);
268 view->ranges = g_realloc(view->ranges,
269 view->nr_allocated * sizeof(*view->ranges));
270 }
271 memmove(view->ranges + pos + 1, view->ranges + pos,
272 (view->nr - pos) * sizeof(FlatRange));
273 view->ranges[pos] = *range;
274 memory_region_ref(range->mr);
275 ++view->nr;
276 }
277
278 static void flatview_destroy(FlatView *view)
279 {
280 int i;
281
282 trace_flatview_destroy(view, view->root);
283 if (view->dispatch) {
284 address_space_dispatch_free(view->dispatch);
285 }
286 for (i = 0; i < view->nr; i++) {
287 memory_region_unref(view->ranges[i].mr);
288 }
289 g_free(view->ranges);
290 memory_region_unref(view->root);
291 g_free(view);
292 }
293
294 static bool flatview_ref(FlatView *view)
295 {
296 return atomic_fetch_inc_nonzero(&view->ref) > 0;
297 }
298
299 void flatview_unref(FlatView *view)
300 {
301 if (atomic_fetch_dec(&view->ref) == 1) {
302 trace_flatview_destroy_rcu(view, view->root);
303 assert(view->root);
304 call_rcu(view, flatview_destroy, rcu);
305 }
306 }
307
308 static bool can_merge(FlatRange *r1, FlatRange *r2)
309 {
310 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
311 && r1->mr == r2->mr
312 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
313 r1->addr.size),
314 int128_make64(r2->offset_in_region))
315 && r1->dirty_log_mask == r2->dirty_log_mask
316 && r1->romd_mode == r2->romd_mode
317 && r1->readonly == r2->readonly
318 && r1->nonvolatile == r2->nonvolatile;
319 }
320
321 /* Attempt to simplify a view by merging adjacent ranges */
322 static void flatview_simplify(FlatView *view)
323 {
324 unsigned i, j;
325
326 i = 0;
327 while (i < view->nr) {
328 j = i + 1;
329 while (j < view->nr
330 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
331 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
332 ++j;
333 }
334 ++i;
335 memmove(&view->ranges[i], &view->ranges[j],
336 (view->nr - j) * sizeof(view->ranges[j]));
337 view->nr -= j - i;
338 }
339 }
340
341 static bool memory_region_big_endian(MemoryRegion *mr)
342 {
343 #ifdef TARGET_WORDS_BIGENDIAN
344 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
345 #else
346 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
347 #endif
348 }
349
350 static bool memory_region_wrong_endianness(MemoryRegion *mr)
351 {
352 #ifdef TARGET_WORDS_BIGENDIAN
353 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
354 #else
355 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
356 #endif
357 }
358
359 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
360 {
361 if (memory_region_wrong_endianness(mr)) {
362 switch (size) {
363 case 1:
364 break;
365 case 2:
366 *data = bswap16(*data);
367 break;
368 case 4:
369 *data = bswap32(*data);
370 break;
371 case 8:
372 *data = bswap64(*data);
373 break;
374 default:
375 abort();
376 }
377 }
378 }
379
380 static inline void memory_region_shift_read_access(uint64_t *value,
381 signed shift,
382 uint64_t mask,
383 uint64_t tmp)
384 {
385 if (shift >= 0) {
386 *value |= (tmp & mask) << shift;
387 } else {
388 *value |= (tmp & mask) >> -shift;
389 }
390 }
391
392 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
393 signed shift,
394 uint64_t mask)
395 {
396 uint64_t tmp;
397
398 if (shift >= 0) {
399 tmp = (*value >> shift) & mask;
400 } else {
401 tmp = (*value << -shift) & mask;
402 }
403
404 return tmp;
405 }
406
407 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
408 {
409 MemoryRegion *root;
410 hwaddr abs_addr = offset;
411
412 abs_addr += mr->addr;
413 for (root = mr; root->container; ) {
414 root = root->container;
415 abs_addr += root->addr;
416 }
417
418 return abs_addr;
419 }
420
421 static int get_cpu_index(void)
422 {
423 if (current_cpu) {
424 return current_cpu->cpu_index;
425 }
426 return -1;
427 }
428
429 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
430 hwaddr addr,
431 uint64_t *value,
432 unsigned size,
433 signed shift,
434 uint64_t mask,
435 MemTxAttrs attrs)
436 {
437 uint64_t tmp;
438
439 tmp = mr->ops->read(mr->opaque, addr, size);
440 if (mr->subpage) {
441 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
442 } else if (mr == &io_mem_notdirty) {
443 /* Accesses to code which has previously been translated into a TB show
444 * up in the MMIO path, as accesses to the io_mem_notdirty
445 * MemoryRegion. */
446 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
447 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
448 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
449 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
450 }
451 memory_region_shift_read_access(value, shift, mask, tmp);
452 return MEMTX_OK;
453 }
454
455 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
456 hwaddr addr,
457 uint64_t *value,
458 unsigned size,
459 signed shift,
460 uint64_t mask,
461 MemTxAttrs attrs)
462 {
463 uint64_t tmp = 0;
464 MemTxResult r;
465
466 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
467 if (mr->subpage) {
468 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
469 } else if (mr == &io_mem_notdirty) {
470 /* Accesses to code which has previously been translated into a TB show
471 * up in the MMIO path, as accesses to the io_mem_notdirty
472 * MemoryRegion. */
473 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
474 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
475 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
476 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
477 }
478 memory_region_shift_read_access(value, shift, mask, tmp);
479 return r;
480 }
481
482 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
483 hwaddr addr,
484 uint64_t *value,
485 unsigned size,
486 signed shift,
487 uint64_t mask,
488 MemTxAttrs attrs)
489 {
490 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
491
492 if (mr->subpage) {
493 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
494 } else if (mr == &io_mem_notdirty) {
495 /* Accesses to code which has previously been translated into a TB show
496 * up in the MMIO path, as accesses to the io_mem_notdirty
497 * MemoryRegion. */
498 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
499 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
502 }
503 mr->ops->write(mr->opaque, addr, tmp, size);
504 return MEMTX_OK;
505 }
506
507 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
508 hwaddr addr,
509 uint64_t *value,
510 unsigned size,
511 signed shift,
512 uint64_t mask,
513 MemTxAttrs attrs)
514 {
515 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
516
517 if (mr->subpage) {
518 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
519 } else if (mr == &io_mem_notdirty) {
520 /* Accesses to code which has previously been translated into a TB show
521 * up in the MMIO path, as accesses to the io_mem_notdirty
522 * MemoryRegion. */
523 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
524 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
525 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
526 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
527 }
528 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
529 }
530
531 static MemTxResult access_with_adjusted_size(hwaddr addr,
532 uint64_t *value,
533 unsigned size,
534 unsigned access_size_min,
535 unsigned access_size_max,
536 MemTxResult (*access_fn)
537 (MemoryRegion *mr,
538 hwaddr addr,
539 uint64_t *value,
540 unsigned size,
541 signed shift,
542 uint64_t mask,
543 MemTxAttrs attrs),
544 MemoryRegion *mr,
545 MemTxAttrs attrs)
546 {
547 uint64_t access_mask;
548 unsigned access_size;
549 unsigned i;
550 MemTxResult r = MEMTX_OK;
551
552 if (!access_size_min) {
553 access_size_min = 1;
554 }
555 if (!access_size_max) {
556 access_size_max = 4;
557 }
558
559 /* FIXME: support unaligned access? */
560 access_size = MAX(MIN(size, access_size_max), access_size_min);
561 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
562 if (memory_region_big_endian(mr)) {
563 for (i = 0; i < size; i += access_size) {
564 r |= access_fn(mr, addr + i, value, access_size,
565 (size - access_size - i) * 8, access_mask, attrs);
566 }
567 } else {
568 for (i = 0; i < size; i += access_size) {
569 r |= access_fn(mr, addr + i, value, access_size, i * 8,
570 access_mask, attrs);
571 }
572 }
573 return r;
574 }
575
576 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
577 {
578 AddressSpace *as;
579
580 while (mr->container) {
581 mr = mr->container;
582 }
583 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
584 if (mr == as->root) {
585 return as;
586 }
587 }
588 return NULL;
589 }
590
591 /* Render a memory region into the global view. Ranges in @view obscure
592 * ranges in @mr.
593 */
594 static void render_memory_region(FlatView *view,
595 MemoryRegion *mr,
596 Int128 base,
597 AddrRange clip,
598 bool readonly,
599 bool nonvolatile)
600 {
601 MemoryRegion *subregion;
602 unsigned i;
603 hwaddr offset_in_region;
604 Int128 remain;
605 Int128 now;
606 FlatRange fr;
607 AddrRange tmp;
608
609 if (!mr->enabled) {
610 return;
611 }
612
613 int128_addto(&base, int128_make64(mr->addr));
614 readonly |= mr->readonly;
615 nonvolatile |= mr->nonvolatile;
616
617 tmp = addrrange_make(base, mr->size);
618
619 if (!addrrange_intersects(tmp, clip)) {
620 return;
621 }
622
623 clip = addrrange_intersection(tmp, clip);
624
625 if (mr->alias) {
626 int128_subfrom(&base, int128_make64(mr->alias->addr));
627 int128_subfrom(&base, int128_make64(mr->alias_offset));
628 render_memory_region(view, mr->alias, base, clip,
629 readonly, nonvolatile);
630 return;
631 }
632
633 /* Render subregions in priority order. */
634 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
635 render_memory_region(view, subregion, base, clip,
636 readonly, nonvolatile);
637 }
638
639 if (!mr->terminates) {
640 return;
641 }
642
643 offset_in_region = int128_get64(int128_sub(clip.start, base));
644 base = clip.start;
645 remain = clip.size;
646
647 fr.mr = mr;
648 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
649 fr.romd_mode = mr->romd_mode;
650 fr.readonly = readonly;
651 fr.nonvolatile = nonvolatile;
652 fr.has_coalesced_range = 0;
653
654 /* Render the region itself into any gaps left by the current view. */
655 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
656 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
657 continue;
658 }
659 if (int128_lt(base, view->ranges[i].addr.start)) {
660 now = int128_min(remain,
661 int128_sub(view->ranges[i].addr.start, base));
662 fr.offset_in_region = offset_in_region;
663 fr.addr = addrrange_make(base, now);
664 flatview_insert(view, i, &fr);
665 ++i;
666 int128_addto(&base, now);
667 offset_in_region += int128_get64(now);
668 int128_subfrom(&remain, now);
669 }
670 now = int128_sub(int128_min(int128_add(base, remain),
671 addrrange_end(view->ranges[i].addr)),
672 base);
673 int128_addto(&base, now);
674 offset_in_region += int128_get64(now);
675 int128_subfrom(&remain, now);
676 }
677 if (int128_nz(remain)) {
678 fr.offset_in_region = offset_in_region;
679 fr.addr = addrrange_make(base, remain);
680 flatview_insert(view, i, &fr);
681 }
682 }
683
684 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
685 {
686 while (mr->enabled) {
687 if (mr->alias) {
688 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
689 /* The alias is included in its entirety. Use it as
690 * the "real" root, so that we can share more FlatViews.
691 */
692 mr = mr->alias;
693 continue;
694 }
695 } else if (!mr->terminates) {
696 unsigned int found = 0;
697 MemoryRegion *child, *next = NULL;
698 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
699 if (child->enabled) {
700 if (++found > 1) {
701 next = NULL;
702 break;
703 }
704 if (!child->addr && int128_ge(mr->size, child->size)) {
705 /* A child is included in its entirety. If it's the only
706 * enabled one, use it in the hope of finding an alias down the
707 * way. This will also let us share FlatViews.
708 */
709 next = child;
710 }
711 }
712 }
713 if (found == 0) {
714 return NULL;
715 }
716 if (next) {
717 mr = next;
718 continue;
719 }
720 }
721
722 return mr;
723 }
724
725 return NULL;
726 }
727
728 /* Render a memory topology into a list of disjoint absolute ranges. */
729 static FlatView *generate_memory_topology(MemoryRegion *mr)
730 {
731 int i;
732 FlatView *view;
733
734 view = flatview_new(mr);
735
736 if (mr) {
737 render_memory_region(view, mr, int128_zero(),
738 addrrange_make(int128_zero(), int128_2_64()),
739 false, false);
740 }
741 flatview_simplify(view);
742
743 view->dispatch = address_space_dispatch_new(view);
744 for (i = 0; i < view->nr; i++) {
745 MemoryRegionSection mrs =
746 section_from_flat_range(&view->ranges[i], view);
747 flatview_add_to_dispatch(view, &mrs);
748 }
749 address_space_dispatch_compact(view->dispatch);
750 g_hash_table_replace(flat_views, mr, view);
751
752 return view;
753 }
754
755 static void address_space_add_del_ioeventfds(AddressSpace *as,
756 MemoryRegionIoeventfd *fds_new,
757 unsigned fds_new_nb,
758 MemoryRegionIoeventfd *fds_old,
759 unsigned fds_old_nb)
760 {
761 unsigned iold, inew;
762 MemoryRegionIoeventfd *fd;
763 MemoryRegionSection section;
764
765 /* Generate a symmetric difference of the old and new fd sets, adding
766 * and deleting as necessary.
767 */
768
769 iold = inew = 0;
770 while (iold < fds_old_nb || inew < fds_new_nb) {
771 if (iold < fds_old_nb
772 && (inew == fds_new_nb
773 || memory_region_ioeventfd_before(&fds_old[iold],
774 &fds_new[inew]))) {
775 fd = &fds_old[iold];
776 section = (MemoryRegionSection) {
777 .fv = address_space_to_flatview(as),
778 .offset_within_address_space = int128_get64(fd->addr.start),
779 .size = fd->addr.size,
780 };
781 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
782 fd->match_data, fd->data, fd->e);
783 ++iold;
784 } else if (inew < fds_new_nb
785 && (iold == fds_old_nb
786 || memory_region_ioeventfd_before(&fds_new[inew],
787 &fds_old[iold]))) {
788 fd = &fds_new[inew];
789 section = (MemoryRegionSection) {
790 .fv = address_space_to_flatview(as),
791 .offset_within_address_space = int128_get64(fd->addr.start),
792 .size = fd->addr.size,
793 };
794 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
795 fd->match_data, fd->data, fd->e);
796 ++inew;
797 } else {
798 ++iold;
799 ++inew;
800 }
801 }
802 }
803
804 FlatView *address_space_get_flatview(AddressSpace *as)
805 {
806 FlatView *view;
807
808 rcu_read_lock();
809 do {
810 view = address_space_to_flatview(as);
811 /* If somebody has replaced as->current_map concurrently,
812 * flatview_ref returns false.
813 */
814 } while (!flatview_ref(view));
815 rcu_read_unlock();
816 return view;
817 }
818
819 static void address_space_update_ioeventfds(AddressSpace *as)
820 {
821 FlatView *view;
822 FlatRange *fr;
823 unsigned ioeventfd_nb = 0;
824 MemoryRegionIoeventfd *ioeventfds = NULL;
825 AddrRange tmp;
826 unsigned i;
827
828 view = address_space_get_flatview(as);
829 FOR_EACH_FLAT_RANGE(fr, view) {
830 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
831 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
832 int128_sub(fr->addr.start,
833 int128_make64(fr->offset_in_region)));
834 if (addrrange_intersects(fr->addr, tmp)) {
835 ++ioeventfd_nb;
836 ioeventfds = g_realloc(ioeventfds,
837 ioeventfd_nb * sizeof(*ioeventfds));
838 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
839 ioeventfds[ioeventfd_nb-1].addr = tmp;
840 }
841 }
842 }
843
844 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
845 as->ioeventfds, as->ioeventfd_nb);
846
847 g_free(as->ioeventfds);
848 as->ioeventfds = ioeventfds;
849 as->ioeventfd_nb = ioeventfd_nb;
850 flatview_unref(view);
851 }
852
853 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
854 {
855 if (!fr->has_coalesced_range) {
856 return;
857 }
858
859 if (--fr->has_coalesced_range > 0) {
860 return;
861 }
862
863 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
864 int128_get64(fr->addr.start),
865 int128_get64(fr->addr.size));
866 }
867
868 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
869 {
870 MemoryRegion *mr = fr->mr;
871 CoalescedMemoryRange *cmr;
872 AddrRange tmp;
873
874 if (QTAILQ_EMPTY(&mr->coalesced)) {
875 return;
876 }
877
878 if (fr->has_coalesced_range++) {
879 return;
880 }
881
882 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
883 tmp = addrrange_shift(cmr->addr,
884 int128_sub(fr->addr.start,
885 int128_make64(fr->offset_in_region)));
886 if (!addrrange_intersects(tmp, fr->addr)) {
887 continue;
888 }
889 tmp = addrrange_intersection(tmp, fr->addr);
890 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
891 int128_get64(tmp.start),
892 int128_get64(tmp.size));
893 }
894 }
895
896 static void address_space_update_topology_pass(AddressSpace *as,
897 const FlatView *old_view,
898 const FlatView *new_view,
899 bool adding)
900 {
901 unsigned iold, inew;
902 FlatRange *frold, *frnew;
903
904 /* Generate a symmetric difference of the old and new memory maps.
905 * Kill ranges in the old map, and instantiate ranges in the new map.
906 */
907 iold = inew = 0;
908 while (iold < old_view->nr || inew < new_view->nr) {
909 if (iold < old_view->nr) {
910 frold = &old_view->ranges[iold];
911 } else {
912 frold = NULL;
913 }
914 if (inew < new_view->nr) {
915 frnew = &new_view->ranges[inew];
916 } else {
917 frnew = NULL;
918 }
919
920 if (frold
921 && (!frnew
922 || int128_lt(frold->addr.start, frnew->addr.start)
923 || (int128_eq(frold->addr.start, frnew->addr.start)
924 && !flatrange_equal(frold, frnew)))) {
925 /* In old but not in new, or in both but attributes changed. */
926
927 if (!adding) {
928 flat_range_coalesced_io_del(frold, as);
929 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
930 }
931
932 ++iold;
933 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
934 /* In both and unchanged (except logging may have changed) */
935
936 if (adding) {
937 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
938 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
939 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
940 frold->dirty_log_mask,
941 frnew->dirty_log_mask);
942 }
943 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
944 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
945 frold->dirty_log_mask,
946 frnew->dirty_log_mask);
947 }
948 }
949
950 ++iold;
951 ++inew;
952 } else {
953 /* In new */
954
955 if (adding) {
956 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
957 flat_range_coalesced_io_add(frnew, as);
958 }
959
960 ++inew;
961 }
962 }
963 }
964
965 static void flatviews_init(void)
966 {
967 static FlatView *empty_view;
968
969 if (flat_views) {
970 return;
971 }
972
973 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
974 (GDestroyNotify) flatview_unref);
975 if (!empty_view) {
976 empty_view = generate_memory_topology(NULL);
977 /* We keep it alive forever in the global variable. */
978 flatview_ref(empty_view);
979 } else {
980 g_hash_table_replace(flat_views, NULL, empty_view);
981 flatview_ref(empty_view);
982 }
983 }
984
985 static void flatviews_reset(void)
986 {
987 AddressSpace *as;
988
989 if (flat_views) {
990 g_hash_table_unref(flat_views);
991 flat_views = NULL;
992 }
993 flatviews_init();
994
995 /* Render unique FVs */
996 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
997 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
998
999 if (g_hash_table_lookup(flat_views, physmr)) {
1000 continue;
1001 }
1002
1003 generate_memory_topology(physmr);
1004 }
1005 }
1006
1007 static void address_space_set_flatview(AddressSpace *as)
1008 {
1009 FlatView *old_view = address_space_to_flatview(as);
1010 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1011 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1012
1013 assert(new_view);
1014
1015 if (old_view == new_view) {
1016 return;
1017 }
1018
1019 if (old_view) {
1020 flatview_ref(old_view);
1021 }
1022
1023 flatview_ref(new_view);
1024
1025 if (!QTAILQ_EMPTY(&as->listeners)) {
1026 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1027
1028 if (!old_view2) {
1029 old_view2 = &tmpview;
1030 }
1031 address_space_update_topology_pass(as, old_view2, new_view, false);
1032 address_space_update_topology_pass(as, old_view2, new_view, true);
1033 }
1034
1035 /* Writes are protected by the BQL. */
1036 atomic_rcu_set(&as->current_map, new_view);
1037 if (old_view) {
1038 flatview_unref(old_view);
1039 }
1040
1041 /* Note that all the old MemoryRegions are still alive up to this
1042 * point. This relieves most MemoryListeners from the need to
1043 * ref/unref the MemoryRegions they get---unless they use them
1044 * outside the iothread mutex, in which case precise reference
1045 * counting is necessary.
1046 */
1047 if (old_view) {
1048 flatview_unref(old_view);
1049 }
1050 }
1051
1052 static void address_space_update_topology(AddressSpace *as)
1053 {
1054 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1055
1056 flatviews_init();
1057 if (!g_hash_table_lookup(flat_views, physmr)) {
1058 generate_memory_topology(physmr);
1059 }
1060 address_space_set_flatview(as);
1061 }
1062
1063 void memory_region_transaction_begin(void)
1064 {
1065 qemu_flush_coalesced_mmio_buffer();
1066 ++memory_region_transaction_depth;
1067 }
1068
1069 void memory_region_transaction_commit(void)
1070 {
1071 AddressSpace *as;
1072
1073 assert(memory_region_transaction_depth);
1074 assert(qemu_mutex_iothread_locked());
1075
1076 --memory_region_transaction_depth;
1077 if (!memory_region_transaction_depth) {
1078 if (memory_region_update_pending) {
1079 flatviews_reset();
1080
1081 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1082
1083 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1084 address_space_set_flatview(as);
1085 address_space_update_ioeventfds(as);
1086 }
1087 memory_region_update_pending = false;
1088 ioeventfd_update_pending = false;
1089 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1090 } else if (ioeventfd_update_pending) {
1091 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1092 address_space_update_ioeventfds(as);
1093 }
1094 ioeventfd_update_pending = false;
1095 }
1096 }
1097 }
1098
1099 static void memory_region_destructor_none(MemoryRegion *mr)
1100 {
1101 }
1102
1103 static void memory_region_destructor_ram(MemoryRegion *mr)
1104 {
1105 qemu_ram_free(mr->ram_block);
1106 }
1107
1108 static bool memory_region_need_escape(char c)
1109 {
1110 return c == '/' || c == '[' || c == '\\' || c == ']';
1111 }
1112
1113 static char *memory_region_escape_name(const char *name)
1114 {
1115 const char *p;
1116 char *escaped, *q;
1117 uint8_t c;
1118 size_t bytes = 0;
1119
1120 for (p = name; *p; p++) {
1121 bytes += memory_region_need_escape(*p) ? 4 : 1;
1122 }
1123 if (bytes == p - name) {
1124 return g_memdup(name, bytes + 1);
1125 }
1126
1127 escaped = g_malloc(bytes + 1);
1128 for (p = name, q = escaped; *p; p++) {
1129 c = *p;
1130 if (unlikely(memory_region_need_escape(c))) {
1131 *q++ = '\\';
1132 *q++ = 'x';
1133 *q++ = "0123456789abcdef"[c >> 4];
1134 c = "0123456789abcdef"[c & 15];
1135 }
1136 *q++ = c;
1137 }
1138 *q = 0;
1139 return escaped;
1140 }
1141
1142 static void memory_region_do_init(MemoryRegion *mr,
1143 Object *owner,
1144 const char *name,
1145 uint64_t size)
1146 {
1147 mr->size = int128_make64(size);
1148 if (size == UINT64_MAX) {
1149 mr->size = int128_2_64();
1150 }
1151 mr->name = g_strdup(name);
1152 mr->owner = owner;
1153 mr->ram_block = NULL;
1154
1155 if (name) {
1156 char *escaped_name = memory_region_escape_name(name);
1157 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1158
1159 if (!owner) {
1160 owner = container_get(qdev_get_machine(), "/unattached");
1161 }
1162
1163 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1164 object_unref(OBJECT(mr));
1165 g_free(name_array);
1166 g_free(escaped_name);
1167 }
1168 }
1169
1170 void memory_region_init(MemoryRegion *mr,
1171 Object *owner,
1172 const char *name,
1173 uint64_t size)
1174 {
1175 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1176 memory_region_do_init(mr, owner, name, size);
1177 }
1178
1179 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1180 void *opaque, Error **errp)
1181 {
1182 MemoryRegion *mr = MEMORY_REGION(obj);
1183 uint64_t value = mr->addr;
1184
1185 visit_type_uint64(v, name, &value, errp);
1186 }
1187
1188 static void memory_region_get_container(Object *obj, Visitor *v,
1189 const char *name, void *opaque,
1190 Error **errp)
1191 {
1192 MemoryRegion *mr = MEMORY_REGION(obj);
1193 gchar *path = (gchar *)"";
1194
1195 if (mr->container) {
1196 path = object_get_canonical_path(OBJECT(mr->container));
1197 }
1198 visit_type_str(v, name, &path, errp);
1199 if (mr->container) {
1200 g_free(path);
1201 }
1202 }
1203
1204 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1205 const char *part)
1206 {
1207 MemoryRegion *mr = MEMORY_REGION(obj);
1208
1209 return OBJECT(mr->container);
1210 }
1211
1212 static void memory_region_get_priority(Object *obj, Visitor *v,
1213 const char *name, void *opaque,
1214 Error **errp)
1215 {
1216 MemoryRegion *mr = MEMORY_REGION(obj);
1217 int32_t value = mr->priority;
1218
1219 visit_type_int32(v, name, &value, errp);
1220 }
1221
1222 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1223 void *opaque, Error **errp)
1224 {
1225 MemoryRegion *mr = MEMORY_REGION(obj);
1226 uint64_t value = memory_region_size(mr);
1227
1228 visit_type_uint64(v, name, &value, errp);
1229 }
1230
1231 static void memory_region_initfn(Object *obj)
1232 {
1233 MemoryRegion *mr = MEMORY_REGION(obj);
1234 ObjectProperty *op;
1235
1236 mr->ops = &unassigned_mem_ops;
1237 mr->enabled = true;
1238 mr->romd_mode = true;
1239 mr->global_locking = true;
1240 mr->destructor = memory_region_destructor_none;
1241 QTAILQ_INIT(&mr->subregions);
1242 QTAILQ_INIT(&mr->coalesced);
1243
1244 op = object_property_add(OBJECT(mr), "container",
1245 "link<" TYPE_MEMORY_REGION ">",
1246 memory_region_get_container,
1247 NULL, /* memory_region_set_container */
1248 NULL, NULL, &error_abort);
1249 op->resolve = memory_region_resolve_container;
1250
1251 object_property_add(OBJECT(mr), "addr", "uint64",
1252 memory_region_get_addr,
1253 NULL, /* memory_region_set_addr */
1254 NULL, NULL, &error_abort);
1255 object_property_add(OBJECT(mr), "priority", "uint32",
1256 memory_region_get_priority,
1257 NULL, /* memory_region_set_priority */
1258 NULL, NULL, &error_abort);
1259 object_property_add(OBJECT(mr), "size", "uint64",
1260 memory_region_get_size,
1261 NULL, /* memory_region_set_size, */
1262 NULL, NULL, &error_abort);
1263 }
1264
1265 static void iommu_memory_region_initfn(Object *obj)
1266 {
1267 MemoryRegion *mr = MEMORY_REGION(obj);
1268
1269 mr->is_iommu = true;
1270 }
1271
1272 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1273 unsigned size)
1274 {
1275 #ifdef DEBUG_UNASSIGNED
1276 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1277 #endif
1278 if (current_cpu != NULL) {
1279 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1280 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1281 }
1282 return 0;
1283 }
1284
1285 static void unassigned_mem_write(void *opaque, hwaddr addr,
1286 uint64_t val, unsigned size)
1287 {
1288 #ifdef DEBUG_UNASSIGNED
1289 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1290 #endif
1291 if (current_cpu != NULL) {
1292 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1293 }
1294 }
1295
1296 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1297 unsigned size, bool is_write,
1298 MemTxAttrs attrs)
1299 {
1300 return false;
1301 }
1302
1303 const MemoryRegionOps unassigned_mem_ops = {
1304 .valid.accepts = unassigned_mem_accepts,
1305 .endianness = DEVICE_NATIVE_ENDIAN,
1306 };
1307
1308 static uint64_t memory_region_ram_device_read(void *opaque,
1309 hwaddr addr, unsigned size)
1310 {
1311 MemoryRegion *mr = opaque;
1312 uint64_t data = (uint64_t)~0;
1313
1314 switch (size) {
1315 case 1:
1316 data = *(uint8_t *)(mr->ram_block->host + addr);
1317 break;
1318 case 2:
1319 data = *(uint16_t *)(mr->ram_block->host + addr);
1320 break;
1321 case 4:
1322 data = *(uint32_t *)(mr->ram_block->host + addr);
1323 break;
1324 case 8:
1325 data = *(uint64_t *)(mr->ram_block->host + addr);
1326 break;
1327 }
1328
1329 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1330
1331 return data;
1332 }
1333
1334 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1335 uint64_t data, unsigned size)
1336 {
1337 MemoryRegion *mr = opaque;
1338
1339 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1340
1341 switch (size) {
1342 case 1:
1343 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1344 break;
1345 case 2:
1346 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1347 break;
1348 case 4:
1349 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1350 break;
1351 case 8:
1352 *(uint64_t *)(mr->ram_block->host + addr) = data;
1353 break;
1354 }
1355 }
1356
1357 static const MemoryRegionOps ram_device_mem_ops = {
1358 .read = memory_region_ram_device_read,
1359 .write = memory_region_ram_device_write,
1360 .endianness = DEVICE_HOST_ENDIAN,
1361 .valid = {
1362 .min_access_size = 1,
1363 .max_access_size = 8,
1364 .unaligned = true,
1365 },
1366 .impl = {
1367 .min_access_size = 1,
1368 .max_access_size = 8,
1369 .unaligned = true,
1370 },
1371 };
1372
1373 bool memory_region_access_valid(MemoryRegion *mr,
1374 hwaddr addr,
1375 unsigned size,
1376 bool is_write,
1377 MemTxAttrs attrs)
1378 {
1379 int access_size_min, access_size_max;
1380 int access_size, i;
1381
1382 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1383 return false;
1384 }
1385
1386 if (!mr->ops->valid.accepts) {
1387 return true;
1388 }
1389
1390 access_size_min = mr->ops->valid.min_access_size;
1391 if (!mr->ops->valid.min_access_size) {
1392 access_size_min = 1;
1393 }
1394
1395 access_size_max = mr->ops->valid.max_access_size;
1396 if (!mr->ops->valid.max_access_size) {
1397 access_size_max = 4;
1398 }
1399
1400 access_size = MAX(MIN(size, access_size_max), access_size_min);
1401 for (i = 0; i < size; i += access_size) {
1402 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1403 is_write, attrs)) {
1404 return false;
1405 }
1406 }
1407
1408 return true;
1409 }
1410
1411 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t *pval,
1414 unsigned size,
1415 MemTxAttrs attrs)
1416 {
1417 *pval = 0;
1418
1419 if (mr->ops->read) {
1420 return access_with_adjusted_size(addr, pval, size,
1421 mr->ops->impl.min_access_size,
1422 mr->ops->impl.max_access_size,
1423 memory_region_read_accessor,
1424 mr, attrs);
1425 } else {
1426 return access_with_adjusted_size(addr, pval, size,
1427 mr->ops->impl.min_access_size,
1428 mr->ops->impl.max_access_size,
1429 memory_region_read_with_attrs_accessor,
1430 mr, attrs);
1431 }
1432 }
1433
1434 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
1437 unsigned size,
1438 MemTxAttrs attrs)
1439 {
1440 MemTxResult r;
1441
1442 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1443 *pval = unassigned_mem_read(mr, addr, size);
1444 return MEMTX_DECODE_ERROR;
1445 }
1446
1447 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1448 adjust_endianness(mr, pval, size);
1449 return r;
1450 }
1451
1452 /* Return true if an eventfd was signalled */
1453 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1454 hwaddr addr,
1455 uint64_t data,
1456 unsigned size,
1457 MemTxAttrs attrs)
1458 {
1459 MemoryRegionIoeventfd ioeventfd = {
1460 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1461 .data = data,
1462 };
1463 unsigned i;
1464
1465 for (i = 0; i < mr->ioeventfd_nb; i++) {
1466 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1467 ioeventfd.e = mr->ioeventfds[i].e;
1468
1469 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1470 event_notifier_set(ioeventfd.e);
1471 return true;
1472 }
1473 }
1474
1475 return false;
1476 }
1477
1478 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1479 hwaddr addr,
1480 uint64_t data,
1481 unsigned size,
1482 MemTxAttrs attrs)
1483 {
1484 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1485 unassigned_mem_write(mr, addr, data, size);
1486 return MEMTX_DECODE_ERROR;
1487 }
1488
1489 adjust_endianness(mr, &data, size);
1490
1491 if ((!kvm_eventfds_enabled()) &&
1492 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1493 return MEMTX_OK;
1494 }
1495
1496 if (mr->ops->write) {
1497 return access_with_adjusted_size(addr, &data, size,
1498 mr->ops->impl.min_access_size,
1499 mr->ops->impl.max_access_size,
1500 memory_region_write_accessor, mr,
1501 attrs);
1502 } else {
1503 return
1504 access_with_adjusted_size(addr, &data, size,
1505 mr->ops->impl.min_access_size,
1506 mr->ops->impl.max_access_size,
1507 memory_region_write_with_attrs_accessor,
1508 mr, attrs);
1509 }
1510 }
1511
1512 void memory_region_init_io(MemoryRegion *mr,
1513 Object *owner,
1514 const MemoryRegionOps *ops,
1515 void *opaque,
1516 const char *name,
1517 uint64_t size)
1518 {
1519 memory_region_init(mr, owner, name, size);
1520 mr->ops = ops ? ops : &unassigned_mem_ops;
1521 mr->opaque = opaque;
1522 mr->terminates = true;
1523 }
1524
1525 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1526 Object *owner,
1527 const char *name,
1528 uint64_t size,
1529 Error **errp)
1530 {
1531 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1532 }
1533
1534 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1535 Object *owner,
1536 const char *name,
1537 uint64_t size,
1538 bool share,
1539 Error **errp)
1540 {
1541 Error *err = NULL;
1542 memory_region_init(mr, owner, name, size);
1543 mr->ram = true;
1544 mr->terminates = true;
1545 mr->destructor = memory_region_destructor_ram;
1546 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1547 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1548 if (err) {
1549 mr->size = int128_zero();
1550 object_unparent(OBJECT(mr));
1551 error_propagate(errp, err);
1552 }
1553 }
1554
1555 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1556 Object *owner,
1557 const char *name,
1558 uint64_t size,
1559 uint64_t max_size,
1560 void (*resized)(const char*,
1561 uint64_t length,
1562 void *host),
1563 Error **errp)
1564 {
1565 Error *err = NULL;
1566 memory_region_init(mr, owner, name, size);
1567 mr->ram = true;
1568 mr->terminates = true;
1569 mr->destructor = memory_region_destructor_ram;
1570 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1571 mr, &err);
1572 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1573 if (err) {
1574 mr->size = int128_zero();
1575 object_unparent(OBJECT(mr));
1576 error_propagate(errp, err);
1577 }
1578 }
1579
1580 #ifdef CONFIG_POSIX
1581 void memory_region_init_ram_from_file(MemoryRegion *mr,
1582 struct Object *owner,
1583 const char *name,
1584 uint64_t size,
1585 uint64_t align,
1586 uint32_t ram_flags,
1587 const char *path,
1588 Error **errp)
1589 {
1590 Error *err = NULL;
1591 memory_region_init(mr, owner, name, size);
1592 mr->ram = true;
1593 mr->terminates = true;
1594 mr->destructor = memory_region_destructor_ram;
1595 mr->align = align;
1596 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1597 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1598 if (err) {
1599 mr->size = int128_zero();
1600 object_unparent(OBJECT(mr));
1601 error_propagate(errp, err);
1602 }
1603 }
1604
1605 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1606 struct Object *owner,
1607 const char *name,
1608 uint64_t size,
1609 bool share,
1610 int fd,
1611 Error **errp)
1612 {
1613 Error *err = NULL;
1614 memory_region_init(mr, owner, name, size);
1615 mr->ram = true;
1616 mr->terminates = true;
1617 mr->destructor = memory_region_destructor_ram;
1618 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1619 share ? RAM_SHARED : 0,
1620 fd, &err);
1621 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1622 if (err) {
1623 mr->size = int128_zero();
1624 object_unparent(OBJECT(mr));
1625 error_propagate(errp, err);
1626 }
1627 }
1628 #endif
1629
1630 void memory_region_init_ram_ptr(MemoryRegion *mr,
1631 Object *owner,
1632 const char *name,
1633 uint64_t size,
1634 void *ptr)
1635 {
1636 memory_region_init(mr, owner, name, size);
1637 mr->ram = true;
1638 mr->terminates = true;
1639 mr->destructor = memory_region_destructor_ram;
1640 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1641
1642 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1643 assert(ptr != NULL);
1644 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1645 }
1646
1647 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1648 Object *owner,
1649 const char *name,
1650 uint64_t size,
1651 void *ptr)
1652 {
1653 memory_region_init(mr, owner, name, size);
1654 mr->ram = true;
1655 mr->terminates = true;
1656 mr->ram_device = true;
1657 mr->ops = &ram_device_mem_ops;
1658 mr->opaque = mr;
1659 mr->destructor = memory_region_destructor_ram;
1660 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1661 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1662 assert(ptr != NULL);
1663 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1664 }
1665
1666 void memory_region_init_alias(MemoryRegion *mr,
1667 Object *owner,
1668 const char *name,
1669 MemoryRegion *orig,
1670 hwaddr offset,
1671 uint64_t size)
1672 {
1673 memory_region_init(mr, owner, name, size);
1674 mr->alias = orig;
1675 mr->alias_offset = offset;
1676 }
1677
1678 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1679 struct Object *owner,
1680 const char *name,
1681 uint64_t size,
1682 Error **errp)
1683 {
1684 Error *err = NULL;
1685 memory_region_init(mr, owner, name, size);
1686 mr->ram = true;
1687 mr->readonly = true;
1688 mr->terminates = true;
1689 mr->destructor = memory_region_destructor_ram;
1690 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1691 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1692 if (err) {
1693 mr->size = int128_zero();
1694 object_unparent(OBJECT(mr));
1695 error_propagate(errp, err);
1696 }
1697 }
1698
1699 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1700 Object *owner,
1701 const MemoryRegionOps *ops,
1702 void *opaque,
1703 const char *name,
1704 uint64_t size,
1705 Error **errp)
1706 {
1707 Error *err = NULL;
1708 assert(ops);
1709 memory_region_init(mr, owner, name, size);
1710 mr->ops = ops;
1711 mr->opaque = opaque;
1712 mr->terminates = true;
1713 mr->rom_device = true;
1714 mr->destructor = memory_region_destructor_ram;
1715 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1716 if (err) {
1717 mr->size = int128_zero();
1718 object_unparent(OBJECT(mr));
1719 error_propagate(errp, err);
1720 }
1721 }
1722
1723 void memory_region_init_iommu(void *_iommu_mr,
1724 size_t instance_size,
1725 const char *mrtypename,
1726 Object *owner,
1727 const char *name,
1728 uint64_t size)
1729 {
1730 struct IOMMUMemoryRegion *iommu_mr;
1731 struct MemoryRegion *mr;
1732
1733 object_initialize(_iommu_mr, instance_size, mrtypename);
1734 mr = MEMORY_REGION(_iommu_mr);
1735 memory_region_do_init(mr, owner, name, size);
1736 iommu_mr = IOMMU_MEMORY_REGION(mr);
1737 mr->terminates = true; /* then re-forwards */
1738 QLIST_INIT(&iommu_mr->iommu_notify);
1739 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1740 }
1741
1742 static void memory_region_finalize(Object *obj)
1743 {
1744 MemoryRegion *mr = MEMORY_REGION(obj);
1745
1746 assert(!mr->container);
1747
1748 /* We know the region is not visible in any address space (it
1749 * does not have a container and cannot be a root either because
1750 * it has no references, so we can blindly clear mr->enabled.
1751 * memory_region_set_enabled instead could trigger a transaction
1752 * and cause an infinite loop.
1753 */
1754 mr->enabled = false;
1755 memory_region_transaction_begin();
1756 while (!QTAILQ_EMPTY(&mr->subregions)) {
1757 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1758 memory_region_del_subregion(mr, subregion);
1759 }
1760 memory_region_transaction_commit();
1761
1762 mr->destructor(mr);
1763 memory_region_clear_coalescing(mr);
1764 g_free((char *)mr->name);
1765 g_free(mr->ioeventfds);
1766 }
1767
1768 Object *memory_region_owner(MemoryRegion *mr)
1769 {
1770 Object *obj = OBJECT(mr);
1771 return obj->parent;
1772 }
1773
1774 void memory_region_ref(MemoryRegion *mr)
1775 {
1776 /* MMIO callbacks most likely will access data that belongs
1777 * to the owner, hence the need to ref/unref the owner whenever
1778 * the memory region is in use.
1779 *
1780 * The memory region is a child of its owner. As long as the
1781 * owner doesn't call unparent itself on the memory region,
1782 * ref-ing the owner will also keep the memory region alive.
1783 * Memory regions without an owner are supposed to never go away;
1784 * we do not ref/unref them because it slows down DMA sensibly.
1785 */
1786 if (mr && mr->owner) {
1787 object_ref(mr->owner);
1788 }
1789 }
1790
1791 void memory_region_unref(MemoryRegion *mr)
1792 {
1793 if (mr && mr->owner) {
1794 object_unref(mr->owner);
1795 }
1796 }
1797
1798 uint64_t memory_region_size(MemoryRegion *mr)
1799 {
1800 if (int128_eq(mr->size, int128_2_64())) {
1801 return UINT64_MAX;
1802 }
1803 return int128_get64(mr->size);
1804 }
1805
1806 const char *memory_region_name(const MemoryRegion *mr)
1807 {
1808 if (!mr->name) {
1809 ((MemoryRegion *)mr)->name =
1810 object_get_canonical_path_component(OBJECT(mr));
1811 }
1812 return mr->name;
1813 }
1814
1815 bool memory_region_is_ram_device(MemoryRegion *mr)
1816 {
1817 return mr->ram_device;
1818 }
1819
1820 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1821 {
1822 uint8_t mask = mr->dirty_log_mask;
1823 if (global_dirty_log && mr->ram_block) {
1824 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1825 }
1826 return mask;
1827 }
1828
1829 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1830 {
1831 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1832 }
1833
1834 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1835 {
1836 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1837 IOMMUNotifier *iommu_notifier;
1838 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1839
1840 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1841 flags |= iommu_notifier->notifier_flags;
1842 }
1843
1844 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1845 imrc->notify_flag_changed(iommu_mr,
1846 iommu_mr->iommu_notify_flags,
1847 flags);
1848 }
1849
1850 iommu_mr->iommu_notify_flags = flags;
1851 }
1852
1853 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1854 IOMMUNotifier *n)
1855 {
1856 IOMMUMemoryRegion *iommu_mr;
1857
1858 if (mr->alias) {
1859 memory_region_register_iommu_notifier(mr->alias, n);
1860 return;
1861 }
1862
1863 /* We need to register for at least one bitfield */
1864 iommu_mr = IOMMU_MEMORY_REGION(mr);
1865 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1866 assert(n->start <= n->end);
1867 assert(n->iommu_idx >= 0 &&
1868 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1869
1870 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1871 memory_region_update_iommu_notify_flags(iommu_mr);
1872 }
1873
1874 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1875 {
1876 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1877
1878 if (imrc->get_min_page_size) {
1879 return imrc->get_min_page_size(iommu_mr);
1880 }
1881 return TARGET_PAGE_SIZE;
1882 }
1883
1884 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1885 {
1886 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1887 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1888 hwaddr addr, granularity;
1889 IOMMUTLBEntry iotlb;
1890
1891 /* If the IOMMU has its own replay callback, override */
1892 if (imrc->replay) {
1893 imrc->replay(iommu_mr, n);
1894 return;
1895 }
1896
1897 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1898
1899 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1900 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1901 if (iotlb.perm != IOMMU_NONE) {
1902 n->notify(n, &iotlb);
1903 }
1904
1905 /* if (2^64 - MR size) < granularity, it's possible to get an
1906 * infinite loop here. This should catch such a wraparound */
1907 if ((addr + granularity) < addr) {
1908 break;
1909 }
1910 }
1911 }
1912
1913 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1914 {
1915 IOMMUNotifier *notifier;
1916
1917 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1918 memory_region_iommu_replay(iommu_mr, notifier);
1919 }
1920 }
1921
1922 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1923 IOMMUNotifier *n)
1924 {
1925 IOMMUMemoryRegion *iommu_mr;
1926
1927 if (mr->alias) {
1928 memory_region_unregister_iommu_notifier(mr->alias, n);
1929 return;
1930 }
1931 QLIST_REMOVE(n, node);
1932 iommu_mr = IOMMU_MEMORY_REGION(mr);
1933 memory_region_update_iommu_notify_flags(iommu_mr);
1934 }
1935
1936 void memory_region_notify_one(IOMMUNotifier *notifier,
1937 IOMMUTLBEntry *entry)
1938 {
1939 IOMMUNotifierFlag request_flags;
1940
1941 /*
1942 * Skip the notification if the notification does not overlap
1943 * with registered range.
1944 */
1945 if (notifier->start > entry->iova + entry->addr_mask ||
1946 notifier->end < entry->iova) {
1947 return;
1948 }
1949
1950 if (entry->perm & IOMMU_RW) {
1951 request_flags = IOMMU_NOTIFIER_MAP;
1952 } else {
1953 request_flags = IOMMU_NOTIFIER_UNMAP;
1954 }
1955
1956 if (notifier->notifier_flags & request_flags) {
1957 notifier->notify(notifier, entry);
1958 }
1959 }
1960
1961 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1962 int iommu_idx,
1963 IOMMUTLBEntry entry)
1964 {
1965 IOMMUNotifier *iommu_notifier;
1966
1967 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1968
1969 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1970 if (iommu_notifier->iommu_idx == iommu_idx) {
1971 memory_region_notify_one(iommu_notifier, &entry);
1972 }
1973 }
1974 }
1975
1976 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1977 enum IOMMUMemoryRegionAttr attr,
1978 void *data)
1979 {
1980 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1981
1982 if (!imrc->get_attr) {
1983 return -EINVAL;
1984 }
1985
1986 return imrc->get_attr(iommu_mr, attr, data);
1987 }
1988
1989 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1990 MemTxAttrs attrs)
1991 {
1992 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1993
1994 if (!imrc->attrs_to_index) {
1995 return 0;
1996 }
1997
1998 return imrc->attrs_to_index(iommu_mr, attrs);
1999 }
2000
2001 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2002 {
2003 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2004
2005 if (!imrc->num_indexes) {
2006 return 1;
2007 }
2008
2009 return imrc->num_indexes(iommu_mr);
2010 }
2011
2012 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2013 {
2014 uint8_t mask = 1 << client;
2015 uint8_t old_logging;
2016
2017 assert(client == DIRTY_MEMORY_VGA);
2018 old_logging = mr->vga_logging_count;
2019 mr->vga_logging_count += log ? 1 : -1;
2020 if (!!old_logging == !!mr->vga_logging_count) {
2021 return;
2022 }
2023
2024 memory_region_transaction_begin();
2025 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2026 memory_region_update_pending |= mr->enabled;
2027 memory_region_transaction_commit();
2028 }
2029
2030 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2031 hwaddr size)
2032 {
2033 assert(mr->ram_block);
2034 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2035 size,
2036 memory_region_get_dirty_log_mask(mr));
2037 }
2038
2039 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2040 {
2041 MemoryListener *listener;
2042 AddressSpace *as;
2043 FlatView *view;
2044 FlatRange *fr;
2045
2046 /* If the same address space has multiple log_sync listeners, we
2047 * visit that address space's FlatView multiple times. But because
2048 * log_sync listeners are rare, it's still cheaper than walking each
2049 * address space once.
2050 */
2051 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2052 if (!listener->log_sync) {
2053 continue;
2054 }
2055 as = listener->address_space;
2056 view = address_space_get_flatview(as);
2057 FOR_EACH_FLAT_RANGE(fr, view) {
2058 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2059 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2060 listener->log_sync(listener, &mrs);
2061 }
2062 }
2063 flatview_unref(view);
2064 }
2065 }
2066
2067 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2068 hwaddr addr,
2069 hwaddr size,
2070 unsigned client)
2071 {
2072 assert(mr->ram_block);
2073 memory_region_sync_dirty_bitmap(mr);
2074 return cpu_physical_memory_snapshot_and_clear_dirty(
2075 memory_region_get_ram_addr(mr) + addr, size, client);
2076 }
2077
2078 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2079 hwaddr addr, hwaddr size)
2080 {
2081 assert(mr->ram_block);
2082 return cpu_physical_memory_snapshot_get_dirty(snap,
2083 memory_region_get_ram_addr(mr) + addr, size);
2084 }
2085
2086 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2087 {
2088 if (mr->readonly != readonly) {
2089 memory_region_transaction_begin();
2090 mr->readonly = readonly;
2091 memory_region_update_pending |= mr->enabled;
2092 memory_region_transaction_commit();
2093 }
2094 }
2095
2096 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2097 {
2098 if (mr->nonvolatile != nonvolatile) {
2099 memory_region_transaction_begin();
2100 mr->nonvolatile = nonvolatile;
2101 memory_region_update_pending |= mr->enabled;
2102 memory_region_transaction_commit();
2103 }
2104 }
2105
2106 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2107 {
2108 if (mr->romd_mode != romd_mode) {
2109 memory_region_transaction_begin();
2110 mr->romd_mode = romd_mode;
2111 memory_region_update_pending |= mr->enabled;
2112 memory_region_transaction_commit();
2113 }
2114 }
2115
2116 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2117 hwaddr size, unsigned client)
2118 {
2119 assert(mr->ram_block);
2120 cpu_physical_memory_test_and_clear_dirty(
2121 memory_region_get_ram_addr(mr) + addr, size, client);
2122 }
2123
2124 int memory_region_get_fd(MemoryRegion *mr)
2125 {
2126 int fd;
2127
2128 rcu_read_lock();
2129 while (mr->alias) {
2130 mr = mr->alias;
2131 }
2132 fd = mr->ram_block->fd;
2133 rcu_read_unlock();
2134
2135 return fd;
2136 }
2137
2138 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2139 {
2140 void *ptr;
2141 uint64_t offset = 0;
2142
2143 rcu_read_lock();
2144 while (mr->alias) {
2145 offset += mr->alias_offset;
2146 mr = mr->alias;
2147 }
2148 assert(mr->ram_block);
2149 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2150 rcu_read_unlock();
2151
2152 return ptr;
2153 }
2154
2155 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2156 {
2157 RAMBlock *block;
2158
2159 block = qemu_ram_block_from_host(ptr, false, offset);
2160 if (!block) {
2161 return NULL;
2162 }
2163
2164 return block->mr;
2165 }
2166
2167 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2168 {
2169 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2170 }
2171
2172 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2173 {
2174 assert(mr->ram_block);
2175
2176 qemu_ram_resize(mr->ram_block, newsize, errp);
2177 }
2178
2179 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2180 {
2181 FlatView *view;
2182 FlatRange *fr;
2183
2184 view = address_space_get_flatview(as);
2185 FOR_EACH_FLAT_RANGE(fr, view) {
2186 if (fr->mr == mr) {
2187 flat_range_coalesced_io_del(fr, as);
2188 flat_range_coalesced_io_add(fr, as);
2189 }
2190 }
2191 flatview_unref(view);
2192 }
2193
2194 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2195 {
2196 AddressSpace *as;
2197
2198 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2199 memory_region_update_coalesced_range_as(mr, as);
2200 }
2201 }
2202
2203 void memory_region_set_coalescing(MemoryRegion *mr)
2204 {
2205 memory_region_clear_coalescing(mr);
2206 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2207 }
2208
2209 void memory_region_add_coalescing(MemoryRegion *mr,
2210 hwaddr offset,
2211 uint64_t size)
2212 {
2213 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2214
2215 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2216 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2217 memory_region_update_coalesced_range(mr);
2218 memory_region_set_flush_coalesced(mr);
2219 }
2220
2221 void memory_region_clear_coalescing(MemoryRegion *mr)
2222 {
2223 CoalescedMemoryRange *cmr;
2224 bool updated = false;
2225
2226 qemu_flush_coalesced_mmio_buffer();
2227 mr->flush_coalesced_mmio = false;
2228
2229 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2230 cmr = QTAILQ_FIRST(&mr->coalesced);
2231 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2232 g_free(cmr);
2233 updated = true;
2234 }
2235
2236 if (updated) {
2237 memory_region_update_coalesced_range(mr);
2238 }
2239 }
2240
2241 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2242 {
2243 mr->flush_coalesced_mmio = true;
2244 }
2245
2246 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2247 {
2248 qemu_flush_coalesced_mmio_buffer();
2249 if (QTAILQ_EMPTY(&mr->coalesced)) {
2250 mr->flush_coalesced_mmio = false;
2251 }
2252 }
2253
2254 void memory_region_clear_global_locking(MemoryRegion *mr)
2255 {
2256 mr->global_locking = false;
2257 }
2258
2259 static bool userspace_eventfd_warning;
2260
2261 void memory_region_add_eventfd(MemoryRegion *mr,
2262 hwaddr addr,
2263 unsigned size,
2264 bool match_data,
2265 uint64_t data,
2266 EventNotifier *e)
2267 {
2268 MemoryRegionIoeventfd mrfd = {
2269 .addr.start = int128_make64(addr),
2270 .addr.size = int128_make64(size),
2271 .match_data = match_data,
2272 .data = data,
2273 .e = e,
2274 };
2275 unsigned i;
2276
2277 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2278 userspace_eventfd_warning))) {
2279 userspace_eventfd_warning = true;
2280 error_report("Using eventfd without MMIO binding in KVM. "
2281 "Suboptimal performance expected");
2282 }
2283
2284 if (size) {
2285 adjust_endianness(mr, &mrfd.data, size);
2286 }
2287 memory_region_transaction_begin();
2288 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2289 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2290 break;
2291 }
2292 }
2293 ++mr->ioeventfd_nb;
2294 mr->ioeventfds = g_realloc(mr->ioeventfds,
2295 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2296 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2297 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2298 mr->ioeventfds[i] = mrfd;
2299 ioeventfd_update_pending |= mr->enabled;
2300 memory_region_transaction_commit();
2301 }
2302
2303 void memory_region_del_eventfd(MemoryRegion *mr,
2304 hwaddr addr,
2305 unsigned size,
2306 bool match_data,
2307 uint64_t data,
2308 EventNotifier *e)
2309 {
2310 MemoryRegionIoeventfd mrfd = {
2311 .addr.start = int128_make64(addr),
2312 .addr.size = int128_make64(size),
2313 .match_data = match_data,
2314 .data = data,
2315 .e = e,
2316 };
2317 unsigned i;
2318
2319 if (size) {
2320 adjust_endianness(mr, &mrfd.data, size);
2321 }
2322 memory_region_transaction_begin();
2323 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2324 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2325 break;
2326 }
2327 }
2328 assert(i != mr->ioeventfd_nb);
2329 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2330 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2331 --mr->ioeventfd_nb;
2332 mr->ioeventfds = g_realloc(mr->ioeventfds,
2333 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2334 ioeventfd_update_pending |= mr->enabled;
2335 memory_region_transaction_commit();
2336 }
2337
2338 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2339 {
2340 MemoryRegion *mr = subregion->container;
2341 MemoryRegion *other;
2342
2343 memory_region_transaction_begin();
2344
2345 memory_region_ref(subregion);
2346 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2347 if (subregion->priority >= other->priority) {
2348 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2349 goto done;
2350 }
2351 }
2352 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2353 done:
2354 memory_region_update_pending |= mr->enabled && subregion->enabled;
2355 memory_region_transaction_commit();
2356 }
2357
2358 static void memory_region_add_subregion_common(MemoryRegion *mr,
2359 hwaddr offset,
2360 MemoryRegion *subregion)
2361 {
2362 assert(!subregion->container);
2363 subregion->container = mr;
2364 subregion->addr = offset;
2365 memory_region_update_container_subregions(subregion);
2366 }
2367
2368 void memory_region_add_subregion(MemoryRegion *mr,
2369 hwaddr offset,
2370 MemoryRegion *subregion)
2371 {
2372 subregion->priority = 0;
2373 memory_region_add_subregion_common(mr, offset, subregion);
2374 }
2375
2376 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2377 hwaddr offset,
2378 MemoryRegion *subregion,
2379 int priority)
2380 {
2381 subregion->priority = priority;
2382 memory_region_add_subregion_common(mr, offset, subregion);
2383 }
2384
2385 void memory_region_del_subregion(MemoryRegion *mr,
2386 MemoryRegion *subregion)
2387 {
2388 memory_region_transaction_begin();
2389 assert(subregion->container == mr);
2390 subregion->container = NULL;
2391 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2392 memory_region_unref(subregion);
2393 memory_region_update_pending |= mr->enabled && subregion->enabled;
2394 memory_region_transaction_commit();
2395 }
2396
2397 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2398 {
2399 if (enabled == mr->enabled) {
2400 return;
2401 }
2402 memory_region_transaction_begin();
2403 mr->enabled = enabled;
2404 memory_region_update_pending = true;
2405 memory_region_transaction_commit();
2406 }
2407
2408 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2409 {
2410 Int128 s = int128_make64(size);
2411
2412 if (size == UINT64_MAX) {
2413 s = int128_2_64();
2414 }
2415 if (int128_eq(s, mr->size)) {
2416 return;
2417 }
2418 memory_region_transaction_begin();
2419 mr->size = s;
2420 memory_region_update_pending = true;
2421 memory_region_transaction_commit();
2422 }
2423
2424 static void memory_region_readd_subregion(MemoryRegion *mr)
2425 {
2426 MemoryRegion *container = mr->container;
2427
2428 if (container) {
2429 memory_region_transaction_begin();
2430 memory_region_ref(mr);
2431 memory_region_del_subregion(container, mr);
2432 mr->container = container;
2433 memory_region_update_container_subregions(mr);
2434 memory_region_unref(mr);
2435 memory_region_transaction_commit();
2436 }
2437 }
2438
2439 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2440 {
2441 if (addr != mr->addr) {
2442 mr->addr = addr;
2443 memory_region_readd_subregion(mr);
2444 }
2445 }
2446
2447 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2448 {
2449 assert(mr->alias);
2450
2451 if (offset == mr->alias_offset) {
2452 return;
2453 }
2454
2455 memory_region_transaction_begin();
2456 mr->alias_offset = offset;
2457 memory_region_update_pending |= mr->enabled;
2458 memory_region_transaction_commit();
2459 }
2460
2461 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2462 {
2463 return mr->align;
2464 }
2465
2466 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2467 {
2468 const AddrRange *addr = addr_;
2469 const FlatRange *fr = fr_;
2470
2471 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2472 return -1;
2473 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2474 return 1;
2475 }
2476 return 0;
2477 }
2478
2479 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2480 {
2481 return bsearch(&addr, view->ranges, view->nr,
2482 sizeof(FlatRange), cmp_flatrange_addr);
2483 }
2484
2485 bool memory_region_is_mapped(MemoryRegion *mr)
2486 {
2487 return mr->container ? true : false;
2488 }
2489
2490 /* Same as memory_region_find, but it does not add a reference to the
2491 * returned region. It must be called from an RCU critical section.
2492 */
2493 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2494 hwaddr addr, uint64_t size)
2495 {
2496 MemoryRegionSection ret = { .mr = NULL };
2497 MemoryRegion *root;
2498 AddressSpace *as;
2499 AddrRange range;
2500 FlatView *view;
2501 FlatRange *fr;
2502
2503 addr += mr->addr;
2504 for (root = mr; root->container; ) {
2505 root = root->container;
2506 addr += root->addr;
2507 }
2508
2509 as = memory_region_to_address_space(root);
2510 if (!as) {
2511 return ret;
2512 }
2513 range = addrrange_make(int128_make64(addr), int128_make64(size));
2514
2515 view = address_space_to_flatview(as);
2516 fr = flatview_lookup(view, range);
2517 if (!fr) {
2518 return ret;
2519 }
2520
2521 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2522 --fr;
2523 }
2524
2525 ret.mr = fr->mr;
2526 ret.fv = view;
2527 range = addrrange_intersection(range, fr->addr);
2528 ret.offset_within_region = fr->offset_in_region;
2529 ret.offset_within_region += int128_get64(int128_sub(range.start,
2530 fr->addr.start));
2531 ret.size = range.size;
2532 ret.offset_within_address_space = int128_get64(range.start);
2533 ret.readonly = fr->readonly;
2534 ret.nonvolatile = fr->nonvolatile;
2535 return ret;
2536 }
2537
2538 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2539 hwaddr addr, uint64_t size)
2540 {
2541 MemoryRegionSection ret;
2542 rcu_read_lock();
2543 ret = memory_region_find_rcu(mr, addr, size);
2544 if (ret.mr) {
2545 memory_region_ref(ret.mr);
2546 }
2547 rcu_read_unlock();
2548 return ret;
2549 }
2550
2551 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2552 {
2553 MemoryRegion *mr;
2554
2555 rcu_read_lock();
2556 mr = memory_region_find_rcu(container, addr, 1).mr;
2557 rcu_read_unlock();
2558 return mr && mr != container;
2559 }
2560
2561 void memory_global_dirty_log_sync(void)
2562 {
2563 memory_region_sync_dirty_bitmap(NULL);
2564 }
2565
2566 static VMChangeStateEntry *vmstate_change;
2567
2568 void memory_global_dirty_log_start(void)
2569 {
2570 if (vmstate_change) {
2571 qemu_del_vm_change_state_handler(vmstate_change);
2572 vmstate_change = NULL;
2573 }
2574
2575 global_dirty_log = true;
2576
2577 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2578
2579 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2580 memory_region_transaction_begin();
2581 memory_region_update_pending = true;
2582 memory_region_transaction_commit();
2583 }
2584
2585 static void memory_global_dirty_log_do_stop(void)
2586 {
2587 global_dirty_log = false;
2588
2589 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2590 memory_region_transaction_begin();
2591 memory_region_update_pending = true;
2592 memory_region_transaction_commit();
2593
2594 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2595 }
2596
2597 static void memory_vm_change_state_handler(void *opaque, int running,
2598 RunState state)
2599 {
2600 if (running) {
2601 memory_global_dirty_log_do_stop();
2602
2603 if (vmstate_change) {
2604 qemu_del_vm_change_state_handler(vmstate_change);
2605 vmstate_change = NULL;
2606 }
2607 }
2608 }
2609
2610 void memory_global_dirty_log_stop(void)
2611 {
2612 if (!runstate_is_running()) {
2613 if (vmstate_change) {
2614 return;
2615 }
2616 vmstate_change = qemu_add_vm_change_state_handler(
2617 memory_vm_change_state_handler, NULL);
2618 return;
2619 }
2620
2621 memory_global_dirty_log_do_stop();
2622 }
2623
2624 static void listener_add_address_space(MemoryListener *listener,
2625 AddressSpace *as)
2626 {
2627 FlatView *view;
2628 FlatRange *fr;
2629
2630 if (listener->begin) {
2631 listener->begin(listener);
2632 }
2633 if (global_dirty_log) {
2634 if (listener->log_global_start) {
2635 listener->log_global_start(listener);
2636 }
2637 }
2638
2639 view = address_space_get_flatview(as);
2640 FOR_EACH_FLAT_RANGE(fr, view) {
2641 MemoryRegionSection section = section_from_flat_range(fr, view);
2642
2643 if (listener->region_add) {
2644 listener->region_add(listener, &section);
2645 }
2646 if (fr->dirty_log_mask && listener->log_start) {
2647 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2648 }
2649 }
2650 if (listener->commit) {
2651 listener->commit(listener);
2652 }
2653 flatview_unref(view);
2654 }
2655
2656 static void listener_del_address_space(MemoryListener *listener,
2657 AddressSpace *as)
2658 {
2659 FlatView *view;
2660 FlatRange *fr;
2661
2662 if (listener->begin) {
2663 listener->begin(listener);
2664 }
2665 view = address_space_get_flatview(as);
2666 FOR_EACH_FLAT_RANGE(fr, view) {
2667 MemoryRegionSection section = section_from_flat_range(fr, view);
2668
2669 if (fr->dirty_log_mask && listener->log_stop) {
2670 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2671 }
2672 if (listener->region_del) {
2673 listener->region_del(listener, &section);
2674 }
2675 }
2676 if (listener->commit) {
2677 listener->commit(listener);
2678 }
2679 flatview_unref(view);
2680 }
2681
2682 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2683 {
2684 MemoryListener *other = NULL;
2685
2686 listener->address_space = as;
2687 if (QTAILQ_EMPTY(&memory_listeners)
2688 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2689 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2690 } else {
2691 QTAILQ_FOREACH(other, &memory_listeners, link) {
2692 if (listener->priority < other->priority) {
2693 break;
2694 }
2695 }
2696 QTAILQ_INSERT_BEFORE(other, listener, link);
2697 }
2698
2699 if (QTAILQ_EMPTY(&as->listeners)
2700 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2701 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2702 } else {
2703 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2704 if (listener->priority < other->priority) {
2705 break;
2706 }
2707 }
2708 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2709 }
2710
2711 listener_add_address_space(listener, as);
2712 }
2713
2714 void memory_listener_unregister(MemoryListener *listener)
2715 {
2716 if (!listener->address_space) {
2717 return;
2718 }
2719
2720 listener_del_address_space(listener, listener->address_space);
2721 QTAILQ_REMOVE(&memory_listeners, listener, link);
2722 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2723 listener->address_space = NULL;
2724 }
2725
2726 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2727 {
2728 memory_region_ref(root);
2729 as->root = root;
2730 as->current_map = NULL;
2731 as->ioeventfd_nb = 0;
2732 as->ioeventfds = NULL;
2733 QTAILQ_INIT(&as->listeners);
2734 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2735 as->name = g_strdup(name ? name : "anonymous");
2736 address_space_update_topology(as);
2737 address_space_update_ioeventfds(as);
2738 }
2739
2740 static void do_address_space_destroy(AddressSpace *as)
2741 {
2742 assert(QTAILQ_EMPTY(&as->listeners));
2743
2744 flatview_unref(as->current_map);
2745 g_free(as->name);
2746 g_free(as->ioeventfds);
2747 memory_region_unref(as->root);
2748 }
2749
2750 void address_space_destroy(AddressSpace *as)
2751 {
2752 MemoryRegion *root = as->root;
2753
2754 /* Flush out anything from MemoryListeners listening in on this */
2755 memory_region_transaction_begin();
2756 as->root = NULL;
2757 memory_region_transaction_commit();
2758 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2759
2760 /* At this point, as->dispatch and as->current_map are dummy
2761 * entries that the guest should never use. Wait for the old
2762 * values to expire before freeing the data.
2763 */
2764 as->root = root;
2765 call_rcu(as, do_address_space_destroy, rcu);
2766 }
2767
2768 static const char *memory_region_type(MemoryRegion *mr)
2769 {
2770 if (memory_region_is_ram_device(mr)) {
2771 return "ramd";
2772 } else if (memory_region_is_romd(mr)) {
2773 return "romd";
2774 } else if (memory_region_is_rom(mr)) {
2775 return "rom";
2776 } else if (memory_region_is_ram(mr)) {
2777 return "ram";
2778 } else {
2779 return "i/o";
2780 }
2781 }
2782
2783 typedef struct MemoryRegionList MemoryRegionList;
2784
2785 struct MemoryRegionList {
2786 const MemoryRegion *mr;
2787 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2788 };
2789
2790 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2791
2792 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2793 int128_sub((size), int128_one())) : 0)
2794 #define MTREE_INDENT " "
2795
2796 static void mtree_expand_owner(const char *label, Object *obj)
2797 {
2798 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2799
2800 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2801 if (dev && dev->id) {
2802 qemu_printf(" id=%s", dev->id);
2803 } else {
2804 gchar *canonical_path = object_get_canonical_path(obj);
2805 if (canonical_path) {
2806 qemu_printf(" path=%s", canonical_path);
2807 g_free(canonical_path);
2808 } else {
2809 qemu_printf(" type=%s", object_get_typename(obj));
2810 }
2811 }
2812 qemu_printf("}");
2813 }
2814
2815 static void mtree_print_mr_owner(const MemoryRegion *mr)
2816 {
2817 Object *owner = mr->owner;
2818 Object *parent = memory_region_owner((MemoryRegion *)mr);
2819
2820 if (!owner && !parent) {
2821 qemu_printf(" orphan");
2822 return;
2823 }
2824 if (owner) {
2825 mtree_expand_owner("owner", owner);
2826 }
2827 if (parent && parent != owner) {
2828 mtree_expand_owner("parent", parent);
2829 }
2830 }
2831
2832 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2833 hwaddr base,
2834 MemoryRegionListHead *alias_print_queue,
2835 bool owner)
2836 {
2837 MemoryRegionList *new_ml, *ml, *next_ml;
2838 MemoryRegionListHead submr_print_queue;
2839 const MemoryRegion *submr;
2840 unsigned int i;
2841 hwaddr cur_start, cur_end;
2842
2843 if (!mr) {
2844 return;
2845 }
2846
2847 for (i = 0; i < level; i++) {
2848 qemu_printf(MTREE_INDENT);
2849 }
2850
2851 cur_start = base + mr->addr;
2852 cur_end = cur_start + MR_SIZE(mr->size);
2853
2854 /*
2855 * Try to detect overflow of memory region. This should never
2856 * happen normally. When it happens, we dump something to warn the
2857 * user who is observing this.
2858 */
2859 if (cur_start < base || cur_end < cur_start) {
2860 qemu_printf("[DETECTED OVERFLOW!] ");
2861 }
2862
2863 if (mr->alias) {
2864 MemoryRegionList *ml;
2865 bool found = false;
2866
2867 /* check if the alias is already in the queue */
2868 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2869 if (ml->mr == mr->alias) {
2870 found = true;
2871 }
2872 }
2873
2874 if (!found) {
2875 ml = g_new(MemoryRegionList, 1);
2876 ml->mr = mr->alias;
2877 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2878 }
2879 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2880 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2881 "-" TARGET_FMT_plx "%s",
2882 cur_start, cur_end,
2883 mr->priority,
2884 mr->nonvolatile ? "nv-" : "",
2885 memory_region_type((MemoryRegion *)mr),
2886 memory_region_name(mr),
2887 memory_region_name(mr->alias),
2888 mr->alias_offset,
2889 mr->alias_offset + MR_SIZE(mr->size),
2890 mr->enabled ? "" : " [disabled]");
2891 if (owner) {
2892 mtree_print_mr_owner(mr);
2893 }
2894 } else {
2895 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2896 " (prio %d, %s%s): %s%s",
2897 cur_start, cur_end,
2898 mr->priority,
2899 mr->nonvolatile ? "nv-" : "",
2900 memory_region_type((MemoryRegion *)mr),
2901 memory_region_name(mr),
2902 mr->enabled ? "" : " [disabled]");
2903 if (owner) {
2904 mtree_print_mr_owner(mr);
2905 }
2906 }
2907 qemu_printf("\n");
2908
2909 QTAILQ_INIT(&submr_print_queue);
2910
2911 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2912 new_ml = g_new(MemoryRegionList, 1);
2913 new_ml->mr = submr;
2914 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2915 if (new_ml->mr->addr < ml->mr->addr ||
2916 (new_ml->mr->addr == ml->mr->addr &&
2917 new_ml->mr->priority > ml->mr->priority)) {
2918 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2919 new_ml = NULL;
2920 break;
2921 }
2922 }
2923 if (new_ml) {
2924 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2925 }
2926 }
2927
2928 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2929 mtree_print_mr(ml->mr, level + 1, cur_start,
2930 alias_print_queue, owner);
2931 }
2932
2933 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2934 g_free(ml);
2935 }
2936 }
2937
2938 struct FlatViewInfo {
2939 int counter;
2940 bool dispatch_tree;
2941 bool owner;
2942 };
2943
2944 static void mtree_print_flatview(gpointer key, gpointer value,
2945 gpointer user_data)
2946 {
2947 FlatView *view = key;
2948 GArray *fv_address_spaces = value;
2949 struct FlatViewInfo *fvi = user_data;
2950 FlatRange *range = &view->ranges[0];
2951 MemoryRegion *mr;
2952 int n = view->nr;
2953 int i;
2954 AddressSpace *as;
2955
2956 qemu_printf("FlatView #%d\n", fvi->counter);
2957 ++fvi->counter;
2958
2959 for (i = 0; i < fv_address_spaces->len; ++i) {
2960 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2961 qemu_printf(" AS \"%s\", root: %s",
2962 as->name, memory_region_name(as->root));
2963 if (as->root->alias) {
2964 qemu_printf(", alias %s", memory_region_name(as->root->alias));
2965 }
2966 qemu_printf("\n");
2967 }
2968
2969 qemu_printf(" Root memory region: %s\n",
2970 view->root ? memory_region_name(view->root) : "(none)");
2971
2972 if (n <= 0) {
2973 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
2974 return;
2975 }
2976
2977 while (n--) {
2978 mr = range->mr;
2979 if (range->offset_in_region) {
2980 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
2981 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
2982 int128_get64(range->addr.start),
2983 int128_get64(range->addr.start)
2984 + MR_SIZE(range->addr.size),
2985 mr->priority,
2986 range->nonvolatile ? "nv-" : "",
2987 range->readonly ? "rom" : memory_region_type(mr),
2988 memory_region_name(mr),
2989 range->offset_in_region);
2990 } else {
2991 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
2992 " (prio %d, %s%s): %s",
2993 int128_get64(range->addr.start),
2994 int128_get64(range->addr.start)
2995 + MR_SIZE(range->addr.size),
2996 mr->priority,
2997 range->nonvolatile ? "nv-" : "",
2998 range->readonly ? "rom" : memory_region_type(mr),
2999 memory_region_name(mr));
3000 }
3001 if (fvi->owner) {
3002 mtree_print_mr_owner(mr);
3003 }
3004 qemu_printf("\n");
3005 range++;
3006 }
3007
3008 #if !defined(CONFIG_USER_ONLY)
3009 if (fvi->dispatch_tree && view->root) {
3010 mtree_print_dispatch(view->dispatch, view->root);
3011 }
3012 #endif
3013
3014 qemu_printf("\n");
3015 }
3016
3017 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3018 gpointer user_data)
3019 {
3020 FlatView *view = key;
3021 GArray *fv_address_spaces = value;
3022
3023 g_array_unref(fv_address_spaces);
3024 flatview_unref(view);
3025
3026 return true;
3027 }
3028
3029 void mtree_info(bool flatview, bool dispatch_tree, bool owner)
3030 {
3031 MemoryRegionListHead ml_head;
3032 MemoryRegionList *ml, *ml2;
3033 AddressSpace *as;
3034
3035 if (flatview) {
3036 FlatView *view;
3037 struct FlatViewInfo fvi = {
3038 .counter = 0,
3039 .dispatch_tree = dispatch_tree,
3040 .owner = owner,
3041 };
3042 GArray *fv_address_spaces;
3043 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3044
3045 /* Gather all FVs in one table */
3046 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3047 view = address_space_get_flatview(as);
3048
3049 fv_address_spaces = g_hash_table_lookup(views, view);
3050 if (!fv_address_spaces) {
3051 fv_address_spaces = g_array_new(false, false, sizeof(as));
3052 g_hash_table_insert(views, view, fv_address_spaces);
3053 }
3054
3055 g_array_append_val(fv_address_spaces, as);
3056 }
3057
3058 /* Print */
3059 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3060
3061 /* Free */
3062 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3063 g_hash_table_unref(views);
3064
3065 return;
3066 }
3067
3068 QTAILQ_INIT(&ml_head);
3069
3070 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3071 qemu_printf("address-space: %s\n", as->name);
3072 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3073 qemu_printf("\n");
3074 }
3075
3076 /* print aliased regions */
3077 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3078 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3079 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3080 qemu_printf("\n");
3081 }
3082
3083 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3084 g_free(ml);
3085 }
3086 }
3087
3088 void memory_region_init_ram(MemoryRegion *mr,
3089 struct Object *owner,
3090 const char *name,
3091 uint64_t size,
3092 Error **errp)
3093 {
3094 DeviceState *owner_dev;
3095 Error *err = NULL;
3096
3097 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3098 if (err) {
3099 error_propagate(errp, err);
3100 return;
3101 }
3102 /* This will assert if owner is neither NULL nor a DeviceState.
3103 * We only want the owner here for the purposes of defining a
3104 * unique name for migration. TODO: Ideally we should implement
3105 * a naming scheme for Objects which are not DeviceStates, in
3106 * which case we can relax this restriction.
3107 */
3108 owner_dev = DEVICE(owner);
3109 vmstate_register_ram(mr, owner_dev);
3110 }
3111
3112 void memory_region_init_rom(MemoryRegion *mr,
3113 struct Object *owner,
3114 const char *name,
3115 uint64_t size,
3116 Error **errp)
3117 {
3118 DeviceState *owner_dev;
3119 Error *err = NULL;
3120
3121 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3122 if (err) {
3123 error_propagate(errp, err);
3124 return;
3125 }
3126 /* This will assert if owner is neither NULL nor a DeviceState.
3127 * We only want the owner here for the purposes of defining a
3128 * unique name for migration. TODO: Ideally we should implement
3129 * a naming scheme for Objects which are not DeviceStates, in
3130 * which case we can relax this restriction.
3131 */
3132 owner_dev = DEVICE(owner);
3133 vmstate_register_ram(mr, owner_dev);
3134 }
3135
3136 void memory_region_init_rom_device(MemoryRegion *mr,
3137 struct Object *owner,
3138 const MemoryRegionOps *ops,
3139 void *opaque,
3140 const char *name,
3141 uint64_t size,
3142 Error **errp)
3143 {
3144 DeviceState *owner_dev;
3145 Error *err = NULL;
3146
3147 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3148 name, size, &err);
3149 if (err) {
3150 error_propagate(errp, err);
3151 return;
3152 }
3153 /* This will assert if owner is neither NULL nor a DeviceState.
3154 * We only want the owner here for the purposes of defining a
3155 * unique name for migration. TODO: Ideally we should implement
3156 * a naming scheme for Objects which are not DeviceStates, in
3157 * which case we can relax this restriction.
3158 */
3159 owner_dev = DEVICE(owner);
3160 vmstate_register_ram(mr, owner_dev);
3161 }
3162
3163 static const TypeInfo memory_region_info = {
3164 .parent = TYPE_OBJECT,
3165 .name = TYPE_MEMORY_REGION,
3166 .instance_size = sizeof(MemoryRegion),
3167 .instance_init = memory_region_initfn,
3168 .instance_finalize = memory_region_finalize,
3169 };
3170
3171 static const TypeInfo iommu_memory_region_info = {
3172 .parent = TYPE_MEMORY_REGION,
3173 .name = TYPE_IOMMU_MEMORY_REGION,
3174 .class_size = sizeof(IOMMUMemoryRegionClass),
3175 .instance_size = sizeof(IOMMUMemoryRegion),
3176 .instance_init = iommu_memory_region_initfn,
3177 .abstract = true,
3178 };
3179
3180 static void memory_register_types(void)
3181 {
3182 type_register_static(&memory_region_info);
3183 type_register_static(&iommu_memory_region_info);
3184 }
3185
3186 type_init(memory_register_types)
AR7 emulation for QEMU