target-sparc/int32_helper.c

   1 /*
   2  * Sparc32 interrupt helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "trace.h"
  22 #include "sysemu/sysemu.h"
  23
  24 #define DEBUG_PCALL
  25
  26 #ifdef DEBUG_PCALL
  27 static const char * const excp_names[0x80] = {
  28     [TT_TFAULT] = "Instruction Access Fault",
  29     [TT_ILL_INSN] = "Illegal Instruction",
  30     [TT_PRIV_INSN] = "Privileged Instruction",
  31     [TT_NFPU_INSN] = "FPU Disabled",
  32     [TT_WIN_OVF] = "Window Overflow",
  33     [TT_WIN_UNF] = "Window Underflow",
  34     [TT_UNALIGNED] = "Unaligned Memory Access",
  35     [TT_FP_EXCP] = "FPU Exception",
  36     [TT_DFAULT] = "Data Access Fault",
  37     [TT_TOVF] = "Tag Overflow",
  38     [TT_EXTINT | 0x1] = "External Interrupt 1",
  39     [TT_EXTINT | 0x2] = "External Interrupt 2",
  40     [TT_EXTINT | 0x3] = "External Interrupt 3",
  41     [TT_EXTINT | 0x4] = "External Interrupt 4",
  42     [TT_EXTINT | 0x5] = "External Interrupt 5",
  43     [TT_EXTINT | 0x6] = "External Interrupt 6",
  44     [TT_EXTINT | 0x7] = "External Interrupt 7",
  45     [TT_EXTINT | 0x8] = "External Interrupt 8",
  46     [TT_EXTINT | 0x9] = "External Interrupt 9",
  47     [TT_EXTINT | 0xa] = "External Interrupt 10",
  48     [TT_EXTINT | 0xb] = "External Interrupt 11",
  49     [TT_EXTINT | 0xc] = "External Interrupt 12",
  50     [TT_EXTINT | 0xd] = "External Interrupt 13",
  51     [TT_EXTINT | 0xe] = "External Interrupt 14",
  52     [TT_EXTINT | 0xf] = "External Interrupt 15",
  53     [TT_TOVF] = "Tag Overflow",
  54     [TT_CODE_ACCESS] = "Instruction Access Error",
  55     [TT_DATA_ACCESS] = "Data Access Error",
  56     [TT_DIV_ZERO] = "Division By Zero",
  57     [TT_NCP_INSN] = "Coprocessor Disabled",
  58 };
  59 #endif
  60
  61 void sparc_cpu_do_interrupt(CPUState *cs)
  62 {
  63     SPARCCPU *cpu = SPARC_CPU(cs);
  64     CPUSPARCState *env = &cpu->env;
  65     int cwp, intno = cs->exception_index;
  66
  67     /* Compute PSR before exposing state.  */
  68     if (env->cc_op != CC_OP_FLAGS) {
  69         cpu_get_psr(env);
  70     }
  71
  72 #ifdef DEBUG_PCALL
  73     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  74         static int count;
  75         const char *name;
  76
  77         if (intno < 0 || intno >= 0x100) {
  78             name = "Unknown";
  79         } else if (intno >= 0x80) {
  80             name = "Trap Instruction";
  81         } else {
  82             name = excp_names[intno];
  83             if (!name) {
  84                 name = "Unknown";
  85             }
  86         }
  87
  88         qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
  89         log_cpu_state(cs, 0);
  90 #if 0
  91         {
  92             int i;
  93             uint8_t *ptr;
  94
  95             qemu_log("       code=");
  96             ptr = (uint8_t *)env->pc;
  97             for (i = 0; i < 16; i++) {
  98                 qemu_log(" %02x", ldub(ptr + i));
  99             }
 100             qemu_log("\n");
 101         }
 102 #endif
 103         count++;
 104     }
 105 #endif
 106 #if !defined(CONFIG_USER_ONLY)
 107     if (env->psret == 0) {
 108         if (cs->exception_index == 0x80 &&
 109             env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
 110             qemu_system_shutdown_request();
 111         } else {
 112             cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
 113                       cs->exception_index);
 114         }
 115         return;
 116     }
 117 #endif
 118     env->psret = 0;
 119     cwp = cpu_cwp_dec(env, env->cwp - 1);
 120     cpu_set_cwp(env, cwp);
 121     env->regwptr[9] = env->pc;
 122     env->regwptr[10] = env->npc;
 123     env->psrps = env->psrs;
 124     env->psrs = 1;
 125     env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
 126     env->pc = env->tbr;
 127     env->npc = env->pc + 4;
 128     cs->exception_index = -1;
 129
 130 #if !defined(CONFIG_USER_ONLY)
 131     /* IRQ acknowledgment */
 132     if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
 133         env->qemu_irq_ack(env, env->irq_manager, intno);
 134     }
 135 #endif
 136 }
 137
 138 #if !defined(CONFIG_USER_ONLY)
 139 static void leon3_cache_control_int(CPUSPARCState *env)
 140 {
 141     uint32_t state = 0;
 142
 143     if (env->cache_control & CACHE_CTRL_IF) {
 144         /* Instruction cache state */
 145         state = env->cache_control & CACHE_STATE_MASK;
 146         if (state == CACHE_ENABLED) {
 147             state = CACHE_FROZEN;
 148             trace_int_helper_icache_freeze();
 149         }
 150
 151         env->cache_control &= ~CACHE_STATE_MASK;
 152         env->cache_control |= state;
 153     }
 154
 155     if (env->cache_control & CACHE_CTRL_DF) {
 156         /* Data cache state */
 157         state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 158         if (state == CACHE_ENABLED) {
 159             state = CACHE_FROZEN;
 160             trace_int_helper_dcache_freeze();
 161         }
 162
 163         env->cache_control &= ~(CACHE_STATE_MASK << 2);
 164         env->cache_control |= (state << 2);
 165     }
 166 }
 167
 168 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
 169 {
 170     leon3_irq_ack(irq_manager, intno);
 171     leon3_cache_control_int(env);
 172 }
 173 #endif