target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <assert.h>
  22 #include "cpu.h"
  23 #include "exec/helper-proto.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #define D(x)
  28
  29 #if !defined(CONFIG_USER_ONLY)
  30
  31 /* Try to fill the TLB and return an exception if error. If retaddr is
  32  * NULL, it means that the function was called in C code (i.e. not
  33  * from generated code or from helper.c)
  34  */
  35 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  36               uintptr_t retaddr)
  37 {
  38     int ret;
  39
  40     ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  41     if (unlikely(ret)) {
  42         if (retaddr) {
  43             /* now we have a real cpu fault */
  44             cpu_restore_state(cs, retaddr);
  45         }
  46         cpu_loop_exit(cs);
  47     }
  48 }
  49 #endif
  50
  51 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  52 {
  53     int test = ctrl & STREAM_TEST;
  54     int atomic = ctrl & STREAM_ATOMIC;
  55     int control = ctrl & STREAM_CONTROL;
  56     int nonblock = ctrl & STREAM_NONBLOCK;
  57     int exception = ctrl & STREAM_EXCEPTION;
  58
  59     qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  60              id, data,
  61              test ? "t" : "",
  62              nonblock ? "n" : "",
  63              exception ? "e" : "",
  64              control ? "c" : "",
  65              atomic ? "a" : "");
  66 }
  67
  68 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  69 {
  70     int test = ctrl & STREAM_TEST;
  71     int atomic = ctrl & STREAM_ATOMIC;
  72     int control = ctrl & STREAM_CONTROL;
  73     int nonblock = ctrl & STREAM_NONBLOCK;
  74     int exception = ctrl & STREAM_EXCEPTION;
  75
  76     qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
  77              id,
  78              test ? "t" : "",
  79              nonblock ? "n" : "",
  80              exception ? "e" : "",
  81              control ? "c" : "",
  82              atomic ? "a" : "");
  83     return 0xdead0000 | id;
  84 }
  85
  86 void helper_raise_exception(CPUMBState *env, uint32_t index)
  87 {
  88     CPUState *cs = CPU(mb_env_get_cpu(env));
  89
  90     cs->exception_index = index;
  91     cpu_loop_exit(cs);
  92 }
  93
  94 void helper_debug(CPUMBState *env)
  95 {
  96     int i;
  97
  98     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
  99     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
 100              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 101              env->debug, env->imm, env->iflags);
 102     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 103              env->btaken, env->btarget,
 104              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 105              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 106              (env->sregs[SR_MSR] & MSR_EIP),
 107              (env->sregs[SR_MSR] & MSR_IE));
 108     for (i = 0; i < 32; i++) {
 109         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 110         if ((i + 1) % 4 == 0)
 111             qemu_log("\n");
 112     }
 113     qemu_log("\n\n");
 114 }
 115
 116 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 117 {
 118     uint32_t cout = 0;
 119
 120     if ((b == ~0) && cin)
 121         cout = 1;
 122     else if ((~0 - a) < (b + cin))
 123         cout = 1;
 124     return cout;
 125 }
 126
 127 uint32_t helper_cmp(uint32_t a, uint32_t b)
 128 {
 129     uint32_t t;
 130
 131     t = b + ~a + 1;
 132     if ((b & 0x80000000) ^ (a & 0x80000000))
 133         t = (t & 0x7fffffff) | (b & 0x80000000);
 134     return t;
 135 }
 136
 137 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 138 {
 139     uint32_t t;
 140
 141     t = b + ~a + 1;
 142     if ((b & 0x80000000) ^ (a & 0x80000000))
 143         t = (t & 0x7fffffff) | (a & 0x80000000);
 144     return t;
 145 }
 146
 147 uint32_t helper_clz(uint32_t t0)
 148 {
 149     return clz32(t0);
 150 }
 151
 152 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 153 {
 154     uint32_t ncf;
 155     ncf = compute_carry(a, b, cf);
 156     return ncf;
 157 }
 158
 159 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
 160 {
 161     if (b == 0) {
 162         env->sregs[SR_MSR] |= MSR_DZ;
 163
 164         if ((env->sregs[SR_MSR] & MSR_EE)
 165             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 166             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 167             helper_raise_exception(env, EXCP_HW_EXCP);
 168         }
 169         return 0;
 170     }
 171     env->sregs[SR_MSR] &= ~MSR_DZ;
 172     return 1;
 173 }
 174
 175 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
 176 {
 177     if (!div_prepare(env, a, b)) {
 178         return 0;
 179     }
 180     return (int32_t)a / (int32_t)b;
 181 }
 182
 183 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 184 {
 185     if (!div_prepare(env, a, b)) {
 186         return 0;
 187     }
 188     return a / b;
 189 }
 190
 191 /* raise FPU exception.  */
 192 static void raise_fpu_exception(CPUMBState *env)
 193 {
 194     env->sregs[SR_ESR] = ESR_EC_FPU;
 195     helper_raise_exception(env, EXCP_HW_EXCP);
 196 }
 197
 198 static void update_fpu_flags(CPUMBState *env, int flags)
 199 {
 200     int raise = 0;
 201
 202     if (flags & float_flag_invalid) {
 203         env->sregs[SR_FSR] |= FSR_IO;
 204         raise = 1;
 205     }
 206     if (flags & float_flag_divbyzero) {
 207         env->sregs[SR_FSR] |= FSR_DZ;
 208         raise = 1;
 209     }
 210     if (flags & float_flag_overflow) {
 211         env->sregs[SR_FSR] |= FSR_OF;
 212         raise = 1;
 213     }
 214     if (flags & float_flag_underflow) {
 215         env->sregs[SR_FSR] |= FSR_UF;
 216         raise = 1;
 217     }
 218     if (raise
 219         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 220         && (env->sregs[SR_MSR] & MSR_EE)) {
 221         raise_fpu_exception(env);
 222     }
 223 }
 224
 225 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
 226 {
 227     CPU_FloatU fd, fa, fb;
 228     int flags;
 229
 230     set_float_exception_flags(0, &env->fp_status);
 231     fa.l = a;
 232     fb.l = b;
 233     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 234
 235     flags = get_float_exception_flags(&env->fp_status);
 236     update_fpu_flags(env, flags);
 237     return fd.l;
 238 }
 239
 240 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
 241 {
 242     CPU_FloatU fd, fa, fb;
 243     int flags;
 244
 245     set_float_exception_flags(0, &env->fp_status);
 246     fa.l = a;
 247     fb.l = b;
 248     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 249     flags = get_float_exception_flags(&env->fp_status);
 250     update_fpu_flags(env, flags);
 251     return fd.l;
 252 }
 253
 254 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
 255 {
 256     CPU_FloatU fd, fa, fb;
 257     int flags;
 258
 259     set_float_exception_flags(0, &env->fp_status);
 260     fa.l = a;
 261     fb.l = b;
 262     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 263     flags = get_float_exception_flags(&env->fp_status);
 264     update_fpu_flags(env, flags);
 265
 266     return fd.l;
 267 }
 268
 269 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
 270 {
 271     CPU_FloatU fd, fa, fb;
 272     int flags;
 273
 274     set_float_exception_flags(0, &env->fp_status);
 275     fa.l = a;
 276     fb.l = b;
 277     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 278     flags = get_float_exception_flags(&env->fp_status);
 279     update_fpu_flags(env, flags);
 280
 281     return fd.l;
 282 }
 283
 284 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
 285 {
 286     CPU_FloatU fa, fb;
 287     uint32_t r = 0;
 288
 289     fa.l = a;
 290     fb.l = b;
 291
 292     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 293         update_fpu_flags(env, float_flag_invalid);
 294         r = 1;
 295     }
 296
 297     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 298         r = 1;
 299     }
 300
 301     return r;
 302 }
 303
 304 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
 305 {
 306     CPU_FloatU fa, fb;
 307     int r;
 308     int flags;
 309
 310     set_float_exception_flags(0, &env->fp_status);
 311     fa.l = a;
 312     fb.l = b;
 313     r = float32_lt(fb.f, fa.f, &env->fp_status);
 314     flags = get_float_exception_flags(&env->fp_status);
 315     update_fpu_flags(env, flags & float_flag_invalid);
 316
 317     return r;
 318 }
 319
 320 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
 321 {
 322     CPU_FloatU fa, fb;
 323     int flags;
 324     int r;
 325
 326     set_float_exception_flags(0, &env->fp_status);
 327     fa.l = a;
 328     fb.l = b;
 329     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 330     flags = get_float_exception_flags(&env->fp_status);
 331     update_fpu_flags(env, flags & float_flag_invalid);
 332
 333     return r;
 334 }
 335
 336 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
 337 {
 338     CPU_FloatU fa, fb;
 339     int flags;
 340     int r;
 341
 342     fa.l = a;
 343     fb.l = b;
 344     set_float_exception_flags(0, &env->fp_status);
 345     r = float32_le(fa.f, fb.f, &env->fp_status);
 346     flags = get_float_exception_flags(&env->fp_status);
 347     update_fpu_flags(env, flags & float_flag_invalid);
 348
 349
 350     return r;
 351 }
 352
 353 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
 354 {
 355     CPU_FloatU fa, fb;
 356     int flags, r;
 357
 358     fa.l = a;
 359     fb.l = b;
 360     set_float_exception_flags(0, &env->fp_status);
 361     r = float32_lt(fa.f, fb.f, &env->fp_status);
 362     flags = get_float_exception_flags(&env->fp_status);
 363     update_fpu_flags(env, flags & float_flag_invalid);
 364     return r;
 365 }
 366
 367 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
 368 {
 369     CPU_FloatU fa, fb;
 370     int flags, r;
 371
 372     fa.l = a;
 373     fb.l = b;
 374     set_float_exception_flags(0, &env->fp_status);
 375     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 376     flags = get_float_exception_flags(&env->fp_status);
 377     update_fpu_flags(env, flags & float_flag_invalid);
 378
 379     return r;
 380 }
 381
 382 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
 383 {
 384     CPU_FloatU fa, fb;
 385     int flags, r;
 386
 387     fa.l = a;
 388     fb.l = b;
 389     set_float_exception_flags(0, &env->fp_status);
 390     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 391     flags = get_float_exception_flags(&env->fp_status);
 392     update_fpu_flags(env, flags & float_flag_invalid);
 393
 394     return r;
 395 }
 396
 397 uint32_t helper_flt(CPUMBState *env, uint32_t a)
 398 {
 399     CPU_FloatU fd, fa;
 400
 401     fa.l = a;
 402     fd.f = int32_to_float32(fa.l, &env->fp_status);
 403     return fd.l;
 404 }
 405
 406 uint32_t helper_fint(CPUMBState *env, uint32_t a)
 407 {
 408     CPU_FloatU fa;
 409     uint32_t r;
 410     int flags;
 411
 412     set_float_exception_flags(0, &env->fp_status);
 413     fa.l = a;
 414     r = float32_to_int32(fa.f, &env->fp_status);
 415     flags = get_float_exception_flags(&env->fp_status);
 416     update_fpu_flags(env, flags);
 417
 418     return r;
 419 }
 420
 421 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
 422 {
 423     CPU_FloatU fd, fa;
 424     int flags;
 425
 426     set_float_exception_flags(0, &env->fp_status);
 427     fa.l = a;
 428     fd.l = float32_sqrt(fa.f, &env->fp_status);
 429     flags = get_float_exception_flags(&env->fp_status);
 430     update_fpu_flags(env, flags);
 431
 432     return fd.l;
 433 }
 434
 435 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 436 {
 437     unsigned int i;
 438     uint32_t mask = 0xff000000;
 439
 440     for (i = 0; i < 4; i++) {
 441         if ((a & mask) == (b & mask))
 442             return i + 1;
 443         mask >>= 8;
 444     }
 445     return 0;
 446 }
 447
 448 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
 449                      uint32_t mask)
 450 {
 451     if (addr & mask) {
 452             qemu_log_mask(CPU_LOG_INT,
 453                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 454                           addr, mask, wr, dr);
 455             env->sregs[SR_EAR] = addr;
 456             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 457                                  | (dr & 31) << 5;
 458             if (mask == 3) {
 459                 env->sregs[SR_ESR] |= 1 << 11;
 460             }
 461             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 462                 return;
 463             }
 464             helper_raise_exception(env, EXCP_HW_EXCP);
 465     }
 466 }
 467
 468 void helper_stackprot(CPUMBState *env, uint32_t addr)
 469 {
 470     if (addr < env->slr || addr > env->shr) {
 471         qemu_log("Stack protector violation at %x %x %x\n",
 472                  addr, env->slr, env->shr);
 473         env->sregs[SR_EAR] = addr;
 474         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 475         helper_raise_exception(env, EXCP_HW_EXCP);
 476     }
 477 }
 478
 479 #if !defined(CONFIG_USER_ONLY)
 480 /* Writes/reads to the MMU's special regs end up here.  */
 481 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
 482 {
 483     return mmu_read(env, rn);
 484 }
 485
 486 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 487 {
 488     mmu_write(env, rn, v);
 489 }
 490
 491 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 492                               bool is_write, bool is_exec, int is_asi,
 493                               unsigned size)
 494 {
 495     MicroBlazeCPU *cpu;
 496     CPUMBState *env;
 497
 498     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 499              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
 500     if (cs == NULL) {
 501         return;
 502     }
 503     cpu = MICROBLAZE_CPU(cs);
 504     env = &cpu->env;
 505     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 506         return;
 507     }
 508
 509     env->sregs[SR_EAR] = addr;
 510     if (is_exec) {
 511         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 512             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 513             helper_raise_exception(env, EXCP_HW_EXCP);
 514         }
 515     } else {
 516         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 517             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 518             helper_raise_exception(env, EXCP_HW_EXCP);
 519         }
 520     }
 521 }
 522 #endif